CN111786426A - Passive CMS equalization circuit and method based on super capacitor - Google Patents
Passive CMS equalization circuit and method based on super capacitor Download PDFInfo
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- CN111786426A CN111786426A CN202010430952.2A CN202010430952A CN111786426A CN 111786426 A CN111786426 A CN 111786426A CN 202010430952 A CN202010430952 A CN 202010430952A CN 111786426 A CN111786426 A CN 111786426A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
Abstract
The invention discloses a passive CMS equalization circuit and method based on a super capacitor. The self-powered module is used for converting the super capacitor group in a power-off state into a power supply of the equalizing circuit, collecting real-time voltage of each capacitor unit, controlling the real-time voltage by the equalizing control module and the main control module, and maintaining potential balance among the super capacitor units by the equalizing module in a resistor consumption mode. When the external power supply of the super capacitor bank is stopped, the electric energy stored in the super capacitor bank is used as the power supply of the equalizing circuit, so that after the super capacitor bank is electrified again, extra time is not needed to wait for each capacitor monomer to realize voltage equalizing work, and the running efficiency of a machine depending on the work of the super capacitor bank is greatly improved.
Description
Technical Field
The invention relates to the field of super capacitors, in particular to a passive CMS equalization circuit and method based on a super capacitor.
Background
Super capacitors are well known for their advantages of high power density, long charge-discharge cycle life, proper energy density, high reliability, wide working temperature range, and low environmental requirements. Compared with other existing energy storage technologies, the super-capacitor energy storage technology has the obvious advantages of no pollution and high efficiency, accords with the mainstream trend of developing green energy at present, and is mainly applied to military related fields such as consumer electronics, smart watches, smart grids, electric vehicles, petroleum machinery, UPS (uninterrupted power supply), aerospace and the like.
The rated voltage of the single super-capacitor is very low, and the rated voltage of the organic electrolyte double-layer super-capacitor is only about 2.5V/2.7V, so that in practical application, a plurality of super-capacitors are combined in series and parallel to form a super-capacitor energy storage module to meet the requirements of energy storage capacity and voltage level. However, the dispersion degree of the capacity of the electric double layer capacitor on the market is-10% to 20% limited by manufacturing equipment, process level and the like. The voltages at two ends of the double-layer capacitor rise along with the accumulation of the charged charges and fall along with the discharge, and the monomer voltage imbalance in the charging and discharging process can be caused by the capacity imbalance and the leakage difference, so that the output power of each capacitor in the system is inconsistent. With the increasing of the charging and discharging times, the inconsistent parameter attenuation phenomenon occurs to each capacitor monomer in the system, which inevitably causes the terminal voltage of each monomer to be more and more unbalanced, the individual monomer can fail in advance, and a series of continuous failure phenomena are caused, and finally the whole system fails. Therefore, the voltage balance control between the capacitors is directly related to the service life of the capacitors and the reliability of the system.
At present, in most application scenarios, a super capacitor system adopts external power supply, and after the super capacitor system is used, control power (DC12V, DC24V and AC220V) is completely disconnected, so that an equalization circuit cannot work, and the work of powering on again needs a certain time (depending on the work stop time) for equalization to normally work, and a certain resource needs to be consumed; meanwhile, the problems of power supply line, communication line arrangement, fixation, EMC, communication interference and the like of the balance board need to be considered. The invention provides a passive CMS equalization circuit based on a super capacitor. Under the condition that the super capacitor system controls power to be disconnected or no external power supply exists, the super capacitor can be guaranteed to realize voltage-sharing work by maintaining the work of the balancing circuit by using the self electric quantity of the super capacitor; meanwhile, the problems of power line arrangement, fixation, interference with a communication line and the like are solved.
Disclosure of Invention
In order to solve the above problems, and enable the balancing circuit to keep the potential balance among the capacitor units after the external control electricity of the super capacitor bank is disconnected, the invention provides a super capacitor passive CMS balancing circuit, which comprises a super capacitor bank, a self-powered module, a sampling module, a balancing control module, a main control module and a balancing module, wherein:
the super capacitor bank comprises a plurality of capacitor units and is used for providing a direct current power supply for the equalizing circuit when the external control power supply is cut off;
the self-powered module is used for converting the direct-current power supply into a direct-current working power supply under a preset safety threshold value and providing a working power supply for other modules;
the sampling module is used for acquiring the real-time voltage of each capacitor monomer;
the balance control module is used for converting the real-time voltage into a real-time sampling signal;
the main control module is used for generating a first control signal according to the real-time sampling signal and sending the first control signal to the equalization control module to generate a second control signal;
and the balancing module is used for adjusting the voltage balance of each capacitor monomer through the resistor according to the second control signal.
Further, the self-powered module includes:
a first switch (S1), one end of the first switch is connected with the positive output end of the super capacitor bank, the other end of the first switch is connected with a first fuse (FA1), and the other end of the first fuse is connected with a first thermistor (RTA 1); the other end of the first thermistor is simultaneously connected with a twentieth resistor (R20), a first transient suppression diode (D1) and a twenty-first capacitor (C21), and the other ends of the twentieth resistor, the first transient suppression diode and the twenty-first capacitor are connected with the negative electrode output end of the super capacitor group in parallel;
the first inductor (L1) comprises first to fourth pins, and the first pin of the first inductor is connected with the negative output end of the super capacitor bank; the second pin of the middle first inductor is connected with the first fuse through the first thermistor; the third pin of the first inductor is simultaneously connected with one ends of twenty-second to twenty-fourth capacitors (C22-C24), and the other ends of the twenty-second to twenty-fourth capacitors are connected with the fourth pin of the first inductor in parallel; a fourth pin of the first inductor is grounded;
a ninth power chip (U9) including first to third pins, the first pin of the ninth power chip being connected to the third pin of the first inductor; the second pin of the ninth power supply chip is simultaneously connected with the fourth pin of the first inductor and one end of a twenty-second resistor (R22); a third pin of the ninth power supply chip is connected with one end of a twenty-first resistor (R21);
the other ends of the twenty-first resistor and the twenty-second resistor are connected with the anode of a second diode (D2) in parallel, and the cathode of the second diode is simultaneously connected with one end of a twenty-third resistor (R23) and the base electrode of the first triode; the other end of the twenty-third resistor and the emitting electrode of the first triode are connected in parallel with a fourth pin of the first inductor; a collector of the first triode is simultaneously connected with a third pin of a ninth power supply chip and a source electrode of a second transistor (K2) through a twenty-fifth resistor (R25), and the second transistor is sequentially connected with a drain electrode of the second transistor through a twenty-seventh resistor (R27) and a twenty-sixth capacitor (C26); the grid electrode of the second transistor is simultaneously connected with the cathode of a fourth diode (D4) and one end of a twenty-eighth resistor (R28), and the other ends of the fourth diode and the twenty-eighth resistor are connected with the source electrode of the second transistor in parallel; the drain electrode of the second transistor is used as the output end of the direct-current working power supply of the self-powered module;
the second triode (Q2), the one end of twenty-sixth resistance (R26) and the negative pole of third diode are connected simultaneously to the base of second triode, the collecting electrode of first diode is connected to the positive pole of third diode, the fourth pin of the first inductance of emitter parallel connection of the other end of twenty-sixth resistance and second third pipe, the grid of second transistor is connected to the collecting electrode of second triode.
Further, the plurality of capacitor cells includes sixteenth to fifty-second capacitors (C47-C52); the equalization control module comprises a thirteenth control chip (U13) comprising first to forty-eighth pins; the main control module comprises a first control chip (U1) including first to sixty-fourth pins.
Further, the sampling module includes:
eighth to fourteenth inductors (L8-L14) and forty-eighth to fifty-fourth resistors (R48-R54) connected in series in this order two by two to form first to seventh RL series circuits; the resistance end of the first RL series circuit is connected with a fourteenth pin of a thirteenth control chip, the resistance end of the second RL series circuit is connected with a sixteenth pin of the thirteenth control chip, the resistance end of the third RL series circuit is connected with an eighteenth pin of the thirteenth control chip, the resistance end of the fourth RL series circuit is connected with a twentieth pin of the thirteenth control chip, the resistance end of the fifth RL series circuit is connected with a twenty-second pin of the thirteenth control chip, the resistance end of the sixth RL series circuit is connected with a twenty-fourth pin of the thirteenth control chip, and the resistance end of the seventh RL series circuit is connected with a twenty-sixth pin of the thirteenth control chip; the inductance end of the first RL series circuit is respectively connected with the second pin, the fourth pin, the sixth pin, the eighth pin, the tenth pin and the twelfth pin of the thirteenth control chip through a seventy-nine resistor (R79); the inductance end of the seventh RL series circuit is respectively grounded and one end of a seventy-third capacitor (C73) through a fifteenth resistor (R55), and the other end of the seventy-third capacitor is connected with a twenty-sixth pin of a thirteenth control chip;
a fourteenth pin of the thirteenth control chip is simultaneously connected with the anode of a seventh diode (D7) and one end of a forty-seventh capacitor, and the cathode of the seventh diode and the other end of the forty-seventh capacitor are connected with a sixteenth pin in parallel; the sixteenth pin is simultaneously connected with the anode of an eighth diode (D8) and one end of a forty-eighth capacitor, and the cathode of the eighth diode and the other end of the forty-eighth capacitor are connected with the eighteenth pin in parallel; the eighteenth pin is simultaneously connected with the anode of a ninth diode (D9) and one end of a forty-ninth capacitor, and the cathode of the ninth diode and the other end of the forty-ninth capacitor are connected with the twentieth pin in parallel; the twentieth pin is simultaneously connected with the anode of a twelfth polar tube (D10) and one end of a fifty-th capacitor, and the cathode of the twelfth polar tube and the other end of the fifty-th capacitor are connected with the twenty-second pin in parallel; the twenty-second pin is simultaneously connected with the anode of an eleventh diode (D11) and one end of a fifty-first capacitor, and the cathode of the eleventh capacitor and the other end of the fifty-first capacitor are connected with a twenty-fourth pin in parallel; and the twenty-fourth pin is simultaneously connected with the anode of a twelfth diode (D12) and one end of a fifty-second capacitor, and the cathode of the twelfth diode and the other end of the fifty-second capacitor are connected with a twenty-sixth pin in parallel.
Further, the equalization module includes first to sixth equalization units, wherein each equalization unit includes:
a first field effect transistor (Q1A), the grid of which is used as a second control signal input end through a ninety-four resistor (R94), and simultaneously connects one end of a ninety-fifth resistor (R95) and the cathode of a first voltage-stabilizing diode (ZA1), and the other end of the ninety-fifth resistor and the anode of the first voltage-stabilizing diode are connected in parallel with the source electrode of the first field effect transistor; the source electrode of the first field effect transistor is used as a second port; the drain of the field effect transistor is sequentially connected with a first equalizing resistor (R1A) and a second equalizing resistor (R2A) as a first port.
Further, the method comprises the following steps:
a first port of the first equalizing unit is connected with an inductance end of the seventh RL series circuit, and a second port of the first equalizing unit is connected with an inductance end of the sixth RL series circuit; a first port of the second equalizing unit is connected with an inductance end of the sixth RL series circuit, and a second port of the second equalizing unit is connected with an inductance end of the fifth RL series circuit; a first port of the third equalizing unit is connected with an inductance end of the fifth RL series circuit, and a second port of the third equalizing unit is connected with an inductance end of the fourth RL series circuit; a first port of the fourth equalizing unit is connected with an inductance end of the fourth RL series circuit, and a second port of the fourth equalizing unit is connected with an inductance end of the third RL series circuit; a first port of the fifth equalizing unit is connected with an inductance end of the third RL series circuit, and a second port of the fifth equalizing unit is connected with an inductance end of the second RL series circuit; and a first port of the sixth equalizing unit is connected with an inductance end of the second RL series circuit, and a second port of the sixth equalizing unit is connected with an inductance end of the first RL series circuit.
Further, still include SPI module and CAN communication module, wherein:
the SPI module is used for balancing signal communication between the control module and the main control module;
and the CAN communication module is used for the signal communication between the main control module and external equipment.
The invention also provides a super capacitor passive CMS balancing method, which is characterized by comprising a super capacitor group, a self-powered module, a sampling module, a balancing control module, a main control module and a balancing module, and the method comprises the following steps:
s1: the external control power supply is powered off, and the output voltage of the super capacitor bank is used as a direct current power supply;
s2: converting the direct-current power supply into a direct-current working power supply under a preset safety threshold value by using a self-powered module to supply power to other modules;
s3: collecting real-time voltage of each capacitor monomer through a sampling module;
s4: converting the real-time voltage into a real-time sampling signal through a balance control module;
s5: generating a first control signal by using a main control module according to the real-time sampling signal;
s6: and according to the first control signal, generating a second control signal through the balance control module to control the balance module to adjust the voltage balance of each capacitor monomer.
Compared with the prior art, the invention at least has the following beneficial effects:
(1) according to the passive CMS equalization circuit and method for the super capacitor, when the external power supply of the super capacitor bank is stopped, the electric energy stored in the super capacitor bank is used as the power supply of the equalization circuit, so that the super capacitor can still keep a voltage-equalizing state under the condition of power failure, and the capacitor loss caused by the damage of the voltage-equalizing state due to the power failure is avoided;
(2) after the super capacitor bank is electrified again, extra time is not needed to wait for each capacitor monomer to realize voltage-sharing work, and the running efficiency of a machine depending on the work of the super capacitor bank is greatly improved;
(3) the triode K2 is matched with each capacitor, resistor and diode in the self-powered module, so that the output voltage of the self-powered module is not more than a preset safety threshold value, and the safety and reliability of circuit operation are ensured;
(4) by adopting the modular design, the modules can be arranged on the circuit board independently, so that most interference can be eliminated or inhibited, and the stability of the circuit is enhanced.
Drawings
Fig. 1 is a block diagram of a super capacitor passive CMS equalization circuit and method;
FIG. 2 is a schematic diagram of a self-powered module circuit;
FIG. 3 is a schematic circuit diagram of a sampling module and an equalization control module;
FIG. 4 is a circuit diagram of a first voltage conversion module;
FIG. 5 is a schematic circuit diagram of the SPI module;
FIG. 6 is a schematic circuit diagram of a main control module;
FIG. 7 is a schematic circuit diagram of a CAN communication module;
FIG. 8 is a circuit diagram of a second voltage conversion module;
fig. 9 is a schematic diagram of an equalizing unit circuit.
Detailed Description
The following are specific embodiments of the present invention and are further described with reference to the drawings, but the present invention is not limited to these embodiments.
In order to enable the balancing circuit to keep the potential balance among the capacitor units after the external control electricity of the super capacitor bank is disconnected, the invention provides a super capacitor passive CMS balancing circuit, as shown in FIG. 1, which comprises a super capacitor bank, a self-powered module, a sampling module, a balancing control module, a main control module and a balancing module, wherein:
a super capacitor bank, including a plurality of capacitor cells (a super capacitor bank composed of 6 capacitor cells adopted in this embodiment), configured to provide a dc power supply (the voltage of the capacitor bank is 5.5V to 36V) for the equalizing circuit when the external control power is off (or no power is supplied);
the self-powered module is used for converting the direct-current power supply into a direct-current working power supply (5V forward direct-current power supply) under a preset safety threshold value and providing a working power supply for other modules;
the sampling module is used for acquiring the real-time voltage of each capacitor monomer;
the balance control module is used for converting the real-time voltage into a real-time sampling signal;
the main control module is used for generating a first control signal according to the real-time sampling signal and sending the first control signal to the equalization control module to generate a second control signal;
and the balancing module is used for adjusting the voltage balance of each capacitor monomer through the resistor according to the second control signal.
By adopting the modular design, the modules can be arranged on the circuit board independently, so that most interference can be eliminated or inhibited, and the stability of the circuit is enhanced.
As shown in fig. 2, a specific connection manner of the self-powered module includes:
a first switch (S1), one end of the first switch is connected with the positive output end of the super capacitor bank, the other end of the first switch is connected with a first fuse (FA1), and the other end of the first fuse is connected with a first thermistor (RTA 1); the other end of the first thermistor is simultaneously connected with a twentieth resistor (R20), a first transient suppression diode (D1) and a twenty-first capacitor (C21), and the other ends of the twentieth resistor, the first transient suppression diode and the twenty-first capacitor are connected with the negative electrode output end of the super capacitor group in parallel;
the first inductor (L1) comprises first to fourth pins, and the first pin of the first inductor is connected with the negative output end of the super capacitor bank; the second pin of the middle first inductor is connected with the first fuse through the first thermistor; the third pin of the first inductor is simultaneously connected with one ends of twenty-second to twenty-fourth capacitors (C22-C24), and the other ends of the twenty-second to twenty-fourth capacitors are connected with the fourth pin of the first inductor in parallel; a fourth pin of the first inductor is grounded;
a ninth power chip (U9) including first to third pins, the first pin of the ninth power chip being connected to the third pin of the first inductor; the second pin of the ninth power supply chip is simultaneously connected with the fourth pin of the first inductor and one end of a twenty-second resistor (R22); a third pin of the ninth power supply chip is connected with one end of a twenty-first resistor (R21);
the other ends of the twenty-first resistor and the twenty-second resistor are connected with the anode of a second diode (D2) in parallel, and the cathode of the second diode is simultaneously connected with one end of a twenty-third resistor (R23) and the base electrode of the first triode; the other end of the twenty-third resistor and the emitting electrode of the first triode are connected in parallel with a fourth pin of the first inductor; a collector of the first triode is simultaneously connected with a third pin of a ninth power supply chip and a source electrode of a second transistor (K2) through a twenty-fifth resistor (R25), and the second transistor is sequentially connected with a drain electrode of the second transistor through a twenty-seventh resistor (R27) and a twenty-sixth capacitor (C26); the grid electrode of the second transistor is simultaneously connected with the cathode of a fourth diode (D4) and one end of a twenty-eighth resistor (R28), and the other ends of the fourth diode and the twenty-eighth resistor are connected with the source electrode of the second transistor in parallel; the drain electrode of the second transistor is used as the output end of the direct-current working power supply of the self-powered module;
the second triode (Q2), the one end of twenty-sixth resistance (R26) and the negative pole of third diode are connected simultaneously to the base of second triode, the collecting electrode of first diode is connected to the positive pole of third diode, the fourth pin of the first inductance of emitter parallel connection of the other end of twenty-sixth resistance and second third pipe, the grid of second transistor is connected to the collecting electrode of second triode.
When a direct-current power supply is input into the self-powered module by the super capacitor bank, and the first switch (S1) is switched on, the current firstly passes through the first fuse (FA1) to judge the current flowing through, when the current exceeding the preset current (the type of the fuse can be selected according to actual requirements) passes through, the current is timely fused to protect the circuit, the damage of the components caused by the large current flowing through the components is avoided, and the noise in the direct current is filtered by utilizing the characteristics of the transient secondary suppression tube and the inductor L1; then, the voltage is reduced by a ninth power chip (U9, the model is K7805-1000R3), 5V output voltage is output, meanwhile, the input voltage is judged by a second transistor (K2, an MOS tube), the output voltage is guaranteed not to exceed a preset safety threshold (5.5V), and the overall safety and reliability of the circuit are guaranteed.
In the present embodiment, the plurality of capacitor cells includes sixteenth to fifty-second capacitors (C47-C52); the balance control module comprises a thirteenth control chip (U13, the chip model is LTC6804-2) and comprises first to forty-eighth pins; the main control module comprises a first control chip (U1, the chip model is STM32F107RCT6) and comprises first to sixty-fourth pins.
In order to balance the electric potential of each capacitor unit of the super capacitor, in this embodiment, a method that a sampling module is combined with a balance control module is adopted to collect real-time voltage data of each capacitor unit, the real-time voltage data is converted into a real-time sampling signal through the balance control module and is transmitted to a main control module, the main control module generates a first control signal according to the real-time sampling signal, the balance control module generates a second control signal according to the first control signal, and the balance module balances the electric potential of each capacitor unit according to the second control signal.
The circuit connection mode of the sampling circuit and the equalization control module is shown in fig. 3, and includes:
eighth to fourteenth inductors (L8-L14) and forty-eighth to fifty-fourth resistors (R48-R54) connected in series in this order two by two to form first to seventh RL series circuits; the resistance end of the first RL series circuit is connected with a fourteenth pin of a thirteenth control chip, the resistance end of the second RL series circuit is connected with a sixteenth pin of the thirteenth control chip, the resistance end of the third RL series circuit is connected with an eighteenth pin of the thirteenth control chip, the resistance end of the fourth RL series circuit is connected with a twentieth pin of the thirteenth control chip, the resistance end of the fifth RL series circuit is connected with a twenty-second pin of the thirteenth control chip, the resistance end of the sixth RL series circuit is connected with a twenty-fourth pin of the thirteenth control chip, and the resistance end of the seventh RL series circuit is connected with a twenty-sixth pin of the thirteenth control chip; the inductance end of the first RL series circuit is respectively connected with the second pin, the fourth pin, the sixth pin, the eighth pin, the tenth pin and the twelfth pin of the thirteenth control chip through a seventy-nine resistor (R79); the inductance end of the seventh RL series circuit is respectively grounded and one end of a seventy-third capacitor (C73) through a fifteenth resistor (R55), and the other end of the seventy-third capacitor is connected with a twenty-sixth pin of a thirteenth control chip;
a fourteenth pin of the thirteenth control chip is simultaneously connected with the anode of a seventh diode (D7) and one end of a forty-seventh capacitor, and the cathode of the seventh diode and the other end of the forty-seventh capacitor are connected with a sixteenth pin in parallel; the sixteenth pin is simultaneously connected with the anode of an eighth diode (D8) and one end of a forty-eighth capacitor, and the cathode of the eighth diode and the other end of the forty-eighth capacitor are connected with the eighteenth pin in parallel; the eighteenth pin is simultaneously connected with the anode of a ninth diode (D9) and one end of a forty-ninth capacitor, and the cathode of the ninth diode and the other end of the forty-ninth capacitor are connected with the twentieth pin in parallel; the twentieth pin is simultaneously connected with the anode of a twelfth polar tube (D10) and one end of a fifty-th capacitor, and the cathode of the twelfth polar tube and the other end of the fifty-th capacitor are connected with the twenty-second pin in parallel; the twenty-second pin is simultaneously connected with the anode of an eleventh diode (D11) and one end of a fifty-first capacitor, and the cathode of the eleventh capacitor and the other end of the fifty-first capacitor are connected with a twenty-fourth pin in parallel; and the twenty-fourth pin is simultaneously connected with the anode of a twelfth diode (D12) and one end of a fifty-second capacitor, and the cathode of the twelfth diode and the other end of the fifty-second capacitor are connected with a twenty-sixth pin in parallel.
And because the commonly used supporting circuit of the control chip such as power input, crystal oscillator and program downloading port, etc. belongs to the conventional technology, no additional figure is added to explain the circuit.
Further, the uniform constant control module further comprises a first voltage conversion module for converting a 5V dc working power output from the power supply module into a 24V working power to provide a proper working power for the balance control module, an input end of the first voltage conversion module is connected to an output end of the dc working power of the power supply module, and an output end of the first voltage conversion module is connected to the first pin of the thirteenth control chip. Since the power conversion module belongs to the conventional technology, the present embodiment does not describe in detail the specific connection manner thereof, and in case of doubt, refer to fig. 4.
Continuing with the above-mentioned main control module, in order to implement signal communication between the equalizing control module and the main control module, the present embodiment adopts an SPI communication manner, including a twelfth control chip (U12, with a chip model of ADUM2401) including first to sixteenth pins, where the eleventh to fourteenth pins are respectively connected to the fourteenth, forty-first, forty-third and forty-second pins of the thirteenth control chip (U13), and the third to sixth pins are respectively connected to the twenty-first, twenty-third, twentieth and twenty-second pins of the first control chip (U1), and the specific connection manner thereof refers to fig. 5 and 6.
In order to realize data transmission between the main control module and the external device, the embodiment further includes a CAN communication module, which is configured to transmit operation data (potential data of each capacitor unit, an alarm signal, and the like) of the main control module to the external device, and meanwhile, may also receive a control signal sent by the external device. The circuit comprises a fifth chip (U5, the model of the chip is TD301DCAN), and the fifth chip comprises first to eighth pins, wherein the fourth pin (namely, an input end) of the fifth chip is connected with the forty-first pin of the first control chip (U1) through a thirty-first resistor (R31), the third pin (namely, an output end) of the fifth chip is connected with the forty-sixth pin of the first control chip (U1) through a thirty-twelve resistor (R32), and specific circuits of the fifth chip refer to FIG. 6 and FIG. 7. However, the circuit connection mode of other pins of the first control chip in the main control module belongs to a conventional circuit connection mode, and this embodiment will not be described in detail, and specifically refer to fig. 6.
Meanwhile, the power supply device further comprises a second voltage conversion module, which is used for converting a 5V direct-current working power supply output by the self-power supply module into a 3.3V working power supply to provide a working power supply for the main control module and the CAN communication module, wherein an input end of the second voltage conversion module is connected with a direct-current working power supply output end of the self-power supply module, and an output end of the second voltage conversion module outputs a 3.3V working voltage, which belongs to a conventional circuit connection mode, so that the connection mode of the second voltage conversion module is not described in detail in this embodiment, and a specific connection mode of the second voltage conversion module.
Further, in order to match with the six configured single capacitors, the equalizing module in this embodiment includes first to sixth equalizing units, where a connection manner of each equalizing unit is as shown in fig. 9, and includes:
a first field effect transistor (Q1A), the grid of which is used as a second control signal input end through a ninety-four resistor (R94), and simultaneously connects one end of a ninety-fifth resistor (R95) and the cathode of a first voltage-stabilizing diode (ZA1), and the other end of the ninety-fifth resistor and the anode of the first voltage-stabilizing diode are connected in parallel with the source electrode of the first field effect transistor; the source electrode of the first field effect transistor is used as a second port; the drain of the field effect transistor is sequentially connected with a first equalizing resistor (R1A) and a second equalizing resistor (R2A) as a first port.
The connection mode of each equalization unit is specifically as follows:
a first port of the first equalizing unit is connected with an inductance end of the seventh RL series circuit, and a second port of the first equalizing unit is connected with an inductance end of the sixth RL series circuit; a first port of the second equalizing unit is connected with an inductance end of the sixth RL series circuit, and a second port of the second equalizing unit is connected with an inductance end of the fifth RL series circuit; a first port of the third equalizing unit is connected with an inductance end of the fifth RL series circuit, and a second port of the third equalizing unit is connected with an inductance end of the fourth RL series circuit; a first port of the fourth equalizing unit is connected with an inductance end of the fourth RL series circuit, and a second port of the fourth equalizing unit is connected with an inductance end of the third RL series circuit; a first port of the fifth equalizing unit is connected with an inductance end of the third RL series circuit, and a second port of the fifth equalizing unit is connected with an inductance end of the second RL series circuit; and a first port of the sixth equalizing unit is connected with an inductance end of the second RL series circuit, and a second port of the sixth equalizing unit is connected with an inductance end of the first RL series circuit.
When the equalization module receives a second control signal sent by the equalization control module through the second control signal input end, the conduction state of the first field effect transistor is adjusted according to the control signal, and the electric energy above the equalization line of each capacitor monomer in the capacitor monomers (the equalization line with the lowest electric potential in the capacitor monomers) is consumed by the first equalization resistor and the second equalization resistor, so that the electric potential of each capacitor monomer is balanced in a power-off state.
According to the passive CMS equalization circuit of the super capacitor, when the external power supply of the super capacitor bank stops, the electric energy stored in the super capacitor bank is used as the power supply of the equalization circuit, so that the super capacitor can still self-power and maintain the operation of the equalization circuit under the condition of power failure, and the capacitor loss caused by the damage of a voltage-sharing state due to the power failure is avoided; meanwhile, after the super capacitor bank is electrified again, extra time is not needed to wait for the capacitor monomers to realize voltage-sharing work, and the running efficiency of a machine depending on the work of the super capacitor bank is greatly improved.
Real-time example two
In order to more clearly understand the core content of the present invention, the present embodiment briefly describes the invention point by means of method steps, and a super capacitor passive CMS balancing method:
s1: the external control power supply is powered off, and the output voltage of the super capacitor bank is used as a direct current power supply;
s2: converting the direct-current power supply into a direct-current working power supply under a preset safety threshold value by using a self-powered module to supply power to other modules;
s3: collecting real-time voltage of each capacitor monomer through a sampling module;
s4: converting the real-time voltage into a real-time sampling signal through a balance control module;
s5: generating a first control signal by using a main control module according to the real-time sampling signal;
s6: and according to the first control signal, generating a second control signal through the balance control module to control the balance module to adjust the voltage balance of each capacitor monomer.
By combining the above embodiments, according to the super capacitor passive CMS balancing circuit and method provided by the invention, when external power supply of the super capacitor bank is stopped, the electric energy stored in the super capacitor bank is used as a power supply of the balancing circuit, so that the super capacitor can still keep a voltage-sharing state under the condition of power failure, and capacitor loss caused by damage of the voltage-sharing state due to power failure is avoided. Therefore, after the super capacitor bank is electrified again, extra time is not needed to wait for the capacitor monomers to realize voltage-sharing work, and the running efficiency of a machine depending on the work of the super capacitor bank is greatly improved.
The triode K2 is matched with each capacitor, resistor and diode in the self-powered module, so that the output voltage of the self-powered module is not more than a preset safety threshold value, and the safety and reliability of circuit operation are ensured; meanwhile, the modular design is adopted, the modules can be arranged on the circuit board independently, most interference can be eliminated or restrained, and the stability of the circuit is enhanced.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (8)
1. The utility model provides a based on passive CMS equalizer circuit of super capacitor, its characterized in that includes super capacitor group, self-powered module, sampling module, balanced control module, host system and balanced module, wherein:
the super capacitor bank comprises a plurality of capacitor units and is used for providing a direct current power supply for the equalizing circuit when the external control power supply is cut off;
the self-powered module is used for converting the direct-current power supply into a direct-current working power supply under a preset safety threshold value and providing a working power supply for other modules;
the sampling module is used for acquiring the real-time voltage of each capacitor monomer;
the balance control module is used for converting the real-time voltage into a real-time sampling signal;
the main control module is used for generating a first control signal according to the real-time sampling signal and sending the first control signal to the equalization control module to generate a second control signal;
and the balancing module is used for adjusting the voltage balance of each capacitor monomer through the resistor according to the second control signal.
2. The supercapacitor passive CMS equalization circuit of claim 1, wherein said self-powered module comprises:
a first switch (S1), one end of the first switch is connected with the positive output end of the super capacitor bank, the other end of the first switch is connected with a first fuse (FA1), and the other end of the first fuse is connected with a first thermistor (RTA 1); the other end of the first thermistor is simultaneously connected with a twentieth resistor (R20), a first transient suppression diode (D1) and a twenty-first capacitor (C21), and the other ends of the twentieth resistor, the first transient suppression diode and the twenty-first capacitor are connected with the negative electrode output end of the super capacitor group in parallel;
the first inductor (L1) comprises first to fourth pins, and the first pin of the first inductor is connected with the negative output end of the super capacitor bank; the second pin of the middle first inductor is connected with the first fuse through the first thermistor; the third pin of the first inductor is simultaneously connected with one ends of twenty-second to twenty-fourth capacitors (C22-C24), and the other ends of the twenty-second to twenty-fourth capacitors are connected with the fourth pin of the first inductor in parallel; a fourth pin of the first inductor is grounded;
a ninth power chip (U9) including first to third pins, the first pin of the ninth power chip being connected to the third pin of the first inductor; the second pin of the ninth power supply chip is simultaneously connected with the fourth pin of the first inductor and one end of a twenty-second resistor (R22); a third pin of the ninth power supply chip is connected with one end of a twenty-first resistor (R21);
the other ends of the twenty-first resistor and the twenty-second resistor are connected with the anode of a second diode (D2) in parallel, and the cathode of the second diode is simultaneously connected with one end of a twenty-third resistor (R23) and the base electrode of the first triode; the other end of the twenty-third resistor and the emitting electrode of the first triode are connected in parallel with a fourth pin of the first inductor; a collector of the first triode is simultaneously connected with a third pin of a ninth power supply chip and a source electrode of a second transistor (K2) through a twenty-fifth resistor (R25), and the second transistor is sequentially connected with a drain electrode of the second transistor through a twenty-seventh resistor (R27) and a twenty-sixth capacitor (C26); the grid electrode of the second transistor is simultaneously connected with the cathode of a fourth diode (D4) and one end of a twenty-eighth resistor (R28), and the other ends of the fourth diode and the twenty-eighth resistor are connected with the source electrode of the second transistor in parallel; the drain electrode of the second transistor is used as the output end of the direct-current working power supply of the self-powered module;
the second triode (Q2), the one end of twenty-sixth resistance (R26) and the negative pole of third diode are connected simultaneously to the base of second triode, the collecting electrode of first diode is connected to the positive pole of third diode, the fourth pin of the first inductance of emitter parallel connection of the other end of twenty-sixth resistance and second third pipe, the grid of second transistor is connected to the collecting electrode of second triode.
3. The supercapacitor passive CMS equalizing circuit of claim 1, wherein said plurality of capacitive cells includes six capacitive cells of forty-seventeen to fifty-second capacitance (C47-C52); the equalization control module comprises a thirteenth control chip (U13) comprising first to forty-eighth pins; the main control module comprises a first control chip (U1) including first to sixty-fourth pins.
4. The supercapacitor passive CMS equalization circuit of claim 3, wherein the sampling module comprises:
eighth to fourteenth inductors (L8-L14) and forty-eighth to fifty-fourth resistors (R48-R54) connected in series in this order two by two to form first to seventh RL series circuits; the resistance end of the first RL series circuit is connected with a fourteenth pin of a thirteenth control chip, the resistance end of the second RL series circuit is connected with a sixteenth pin of the thirteenth control chip, the resistance end of the third RL series circuit is connected with an eighteenth pin of the thirteenth control chip, the resistance end of the fourth RL series circuit is connected with a twentieth pin of the thirteenth control chip, the resistance end of the fifth RL series circuit is connected with a twenty-second pin of the thirteenth control chip, the resistance end of the sixth RL series circuit is connected with a twenty-fourth pin of the thirteenth control chip, and the resistance end of the seventh RL series circuit is connected with a twenty-sixth pin of the thirteenth control chip; the inductance end of the first RL series circuit is respectively connected with the second pin, the fourth pin, the sixth pin, the eighth pin, the tenth pin and the twelfth pin of the thirteenth control chip through a seventy-nine resistor (R79); the inductance end of the seventh RL series circuit is respectively grounded and one end of a seventy-third capacitor (C73) through a fifteenth resistor (R55), and the other end of the seventy-third capacitor is connected with a twenty-sixth pin of a thirteenth control chip;
a fourteenth pin of the thirteenth control chip is simultaneously connected with the anode of a seventh diode (D7) and one end of a forty-seventh capacitor, and the cathode of the seventh diode and the other end of the forty-seventh capacitor are connected with a sixteenth pin in parallel; the sixteenth pin is simultaneously connected with the anode of an eighth diode (D8) and one end of a forty-eighth capacitor, and the cathode of the eighth diode and the other end of the forty-eighth capacitor are connected with the eighteenth pin in parallel; the eighteenth pin is simultaneously connected with the anode of a ninth diode (D9) and one end of a forty-ninth capacitor, and the cathode of the ninth diode and the other end of the forty-ninth capacitor are connected with the twentieth pin in parallel; the twentieth pin is simultaneously connected with the anode of a twelfth polar tube (D10) and one end of a fifty-th capacitor, and the cathode of the twelfth polar tube and the other end of the fifty-th capacitor are connected with the twenty-second pin in parallel; the twenty-second pin is simultaneously connected with the anode of an eleventh diode (D11) and one end of a fifty-first capacitor, and the cathode of the eleventh capacitor and the other end of the fifty-first capacitor are connected with a twenty-fourth pin in parallel; and the twenty-fourth pin is simultaneously connected with the anode of a twelfth diode (D12) and one end of a fifty-second capacitor, and the cathode of the twelfth diode and the other end of the fifty-second capacitor are connected with a twenty-sixth pin in parallel.
5. The supercapacitor passive CMS equalizing circuit according to any of claims 3 or 4, wherein the equalizing module comprises first to sixth equalizing units, each of which comprises:
a first field effect transistor (Q1A), the grid of which is used as a second control signal input end through a ninety-four resistor (R94), and simultaneously connects one end of a ninety-fifth resistor (R95) and the cathode of a first voltage-stabilizing diode (ZA1), and the other end of the ninety-fifth resistor and the anode of the first voltage-stabilizing diode are connected in parallel with the source electrode of the first field effect transistor; the source electrode of the first field effect transistor is used as a second port; the drain of the field effect transistor is sequentially connected with a first equalizing resistor (R1A) and a second equalizing resistor (R2A) as a first port.
6. The supercapacitor passive CMS equalization circuit of claim 5, wherein said:
a first port of the first equalizing unit is connected with an inductance end of the seventh RL series circuit, and a second port of the first equalizing unit is connected with an inductance end of the sixth RL series circuit; a first port of the second equalizing unit is connected with an inductance end of the sixth RL series circuit, and a second port of the second equalizing unit is connected with an inductance end of the fifth RL series circuit; a first port of the third equalizing unit is connected with an inductance end of the fifth RL series circuit, and a second port of the third equalizing unit is connected with an inductance end of the fourth RL series circuit; a first port of the fourth equalizing unit is connected with an inductance end of the fourth RL series circuit, and a second port of the fourth equalizing unit is connected with an inductance end of the third RL series circuit; a first port of the fifth equalizing unit is connected with an inductance end of the third RL series circuit, and a second port of the fifth equalizing unit is connected with an inductance end of the second RL series circuit; and a first port of the sixth equalizing unit is connected with an inductance end of the second RL series circuit, and a second port of the sixth equalizing unit is connected with an inductance end of the first RL series circuit.
7. The supercapacitor passive CMS equalization circuit of claim 1, further comprising an SPI module and a CAN communication module, wherein:
the SPI module is used for balancing signal communication between the control module and the main control module;
and the CAN communication module is used for the signal communication between the main control module and external equipment.
8. A super capacitor passive CMS balancing method is characterized by comprising a super capacitor bank, a self-powered module, a sampling module, a balancing control module, a main control module and a balancing module, and comprises the following steps:
s1: the external control power supply is powered off, and the output voltage of the super capacitor bank is used as a direct current power supply;
s2: converting the direct-current power supply into a direct-current working power supply under a preset safety threshold value by using a self-powered module to supply power to other modules;
s3: collecting real-time voltage of each capacitor monomer through a sampling module;
s4: converting the real-time voltage into a real-time sampling signal through a balance control module;
s5: generating a first control signal by using a main control module according to the real-time sampling signal;
s6: and according to the first control signal, generating a second control signal through the balance control module to control the balance module to adjust the voltage balance of each capacitor monomer.
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| CN202010430952.2A CN111786426B (en) | 2020-05-20 | 2020-05-20 | Passive CMS equalization circuit and method based on super capacitor |
| PCT/CN2021/094473 WO2021233318A1 (en) | 2020-05-20 | 2021-05-19 | Passive cms equalization circuit and method based on super-capacitor |
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| CN202010430952.2A CN111786426B (en) | 2020-05-20 | 2020-05-20 | Passive CMS equalization circuit and method based on super capacitor |
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| WO2021233318A1 (en) * | 2020-05-20 | 2021-11-25 | 宁波中车新能源科技有限公司 | Passive cms equalization circuit and method based on super-capacitor |
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| CN114179666B (en) * | 2022-01-25 | 2024-03-15 | 广东高标智能科技股份有限公司 | Electric vehicle control system |
| CN115061964B (en) * | 2022-06-30 | 2023-10-20 | 东风汽车集团股份有限公司 | Input expansion circuit with low cost and low static power consumption and expansion method |
| CN116068699B (en) * | 2023-03-07 | 2023-08-29 | 南京迪威普光电技术股份有限公司 | Annular high-voltage arc generator with controllable strength and generation method |
| CN116800284B (en) * | 2023-07-18 | 2024-03-12 | 北京捷星电子科技有限公司 | Bluetooth multimedia radio |
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