CN111782268B - Method, apparatus, device and computer readable medium for allocating hardware resources - Google Patents
Method, apparatus, device and computer readable medium for allocating hardware resources Download PDFInfo
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- 238000004590 computer program Methods 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 abstract description 8
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The invention discloses a method, a device, equipment and a computer readable medium for distributing hardware resources, and relates to the technical field of computers. One embodiment of the method comprises the following steps: assigning a device identification of a device register of a hardware device and an address index of a queue register of the hardware device to a client; binding a device identification of the allocated device register with an address index of the allocated queue register, and storing a queue index base address of the queue register and a number of allocated queues to allocate queue resources of the hardware device to the client; an access request of the client to the hardware device is received, the access request including a device identification of a device register. According to the embodiment, hardware resources are not required to be distributed through the software intermediate layer, so that the system overhead can be reduced, and the transmission efficiency is improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a computer readable medium for allocating hardware resources.
Background
The configuration register is an interface to configure software or read hardware states. To meet the high performance requirement, most peripheral hardware will employ a multi-queue architecture. In a multi-queue configuration, there is one configuration register set for each queue, and multiple queues form a configuration register queue. The configuration register sets and queues are in one-to-one correspondence.
In the prior art, a software intermediate layer is adopted, such as: hypervisor simulates the virtualization effect of hardware. Wherein, the configuration register of the hardware is also simulated by the device simulation software.
In the process of implementing the present invention, the inventor finds that at least the following problems exist in the prior art: the peripheral hardware directly utilizes virtualization to realize seamless connection with the client, but adopts a software intermediate layer to allocate hardware resources, and meanwhile, the system overhead is increased, and the transmission efficiency is reduced.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, apparatus, device, and computer readable medium for allocating hardware resources, which can reduce system overhead and improve transmission efficiency without allocating hardware resources through a software intermediate layer.
To achieve the above object, according to one aspect of the embodiments of the present invention, there is provided a method for allocating hardware resources, including:
Assigning a device identification of a device register of a hardware device and an address index of a queue register of the hardware device to a client;
binding a device identification of the allocated device register with an address index of the allocated queue register, and storing a queue index base address of the queue register and a number of allocated queues to allocate queue resources of the hardware device to the client;
An access request of the client to the hardware device is received, the access request including a device identification of a device register.
After binding the device identifier of the allocated device register with the address index of the allocated queue register and storing the queue index base address of the queue register and the number of allocated queues, the method further comprises:
reallocating queue resources of the target hardware device according to the device identifier of the device register and the number of the allocated queues;
The device identifier of the device register is bound to the address index of the reassigned queue register and the queue index base address of the reassigned queue register and the number of assigned queues are stored to migrate the client to the target hardware device.
After binding the device identifier of the allocated device register with the address index of the allocated queue register and storing the queue index base address of the queue register and the number of allocated queues, the method further comprises:
deleting the binding relationship of the device identification of the allocated device register and the address index of the allocated queue register, and deleting the queue index base address of the queue register and the number of allocated queues to release the allocated device register and the allocated queue register.
The binding the device identification of the allocated device register with the address index of the allocated queue register and storing the queue index base address of the queue register and the number of allocated queues, comprising:
a queue index base table and a queue index offset table are set,
The queue index base table records a correspondence of device identifications with queue register base addresses, the queue index base addresses of the queue registers being determined by a number of clients and a number of the allocated queues,
The queue index offset table records a relationship of device identifications to offsets, the offsets being determined by the number of allocated queues.
The access request further includes an offset of the queue register, a maximum of the offset being determined by the number of allocated queues.
The binding the device identification of the allocated device register with the address index of the allocated queue register comprises:
The device identification of the assigned device register is bound to the address index of the assigned first queue register.
The device register maps to a first device register address and a second device register address, the queue register maps to a first queue register address and a second queue register address,
The client accesses the device register via a first device register address, the host accesses the device register via a second device register address,
The client accesses the queue register via a first queue register address and the host accesses the queue register via a second queue register address.
According to a second aspect of an embodiment of the present invention, there is provided an apparatus for allocating hardware resources, including:
An allocation module, configured to allocate, for a client, a device identifier of a device register of a hardware device and an address index of a queue register of the hardware device;
A binding module for binding a device identifier of an allocated device register with an address index of the allocated queue register, and storing a queue index base address of the queue register and the number of allocated queues to allocate queue resources of the hardware device to the client;
and the access module is used for receiving an access request of the client to the hardware device, wherein the access request comprises the device identification of the device register.
According to a third aspect of an embodiment of the present invention, there is provided an electronic device for allocating hardware resources, including:
one or more processors;
Storage means for storing one or more programs,
The one or more programs, when executed by the one or more processors, cause the one or more processors to implement the methods as described above.
According to a fourth aspect of embodiments of the present invention, there is provided a computer readable medium having stored thereon a computer program which when executed by a processor implements a method as described above.
One embodiment of the above invention has the following advantages or benefits: firstly, distributing a device identifier of a device register of a hardware device and an address index of a queue register of the hardware device to a client; then binding the device identification of the allocated device register with the address index of the allocated queue register, and storing the queue index base address of the queue register and the number of allocated queues to allocate the queue resources of the hardware device to the client; finally, an access request of the client to the hardware device is received, the access request including a device identification of the device register. In the process of distributing hardware equipment resources, the queue resources of the hardware equipment can be distributed to clients without adopting a software middle layer, so that the system overhead can be reduced, and the transmission efficiency is improved.
Further effects of the above-described non-conventional alternatives are described below in connection with the embodiments.
Drawings
The drawings are included to provide a better understanding of the invention and are not to be construed as unduly limiting the invention. Wherein:
FIG. 1 is a schematic diagram of the main flow of a method of allocating hardware resources according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a method application scenario for allocating hardware resources according to an embodiment of the present invention;
FIG. 3 is a flow diagram of a migration hardware device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a differentiated-access configuration channel according to an embodiment of the invention;
FIG. 5 is a flow diagram of an access configuration channel according to an embodiment of the present invention;
FIG. 6 is a flow diagram of a host accessing registers according to an embodiment of the present invention;
FIG. 7 is a flow diagram of a client accessing registers according to an embodiment of the present invention;
FIG. 8 is a flow diagram of a hardware device accepting host access according to an embodiment of the invention;
FIG. 9 is a flow diagram of a hardware device accepting client access according to an embodiment of the invention;
FIG. 10 is a schematic diagram of the main structure of an apparatus for allocating hardware resources according to an embodiment of the present invention;
FIG. 11 is an exemplary system architecture diagram in which embodiments of the present invention may be applied;
fig. 12 is a schematic diagram of a computer system suitable for use in implementing an embodiment of the invention.
Detailed Description
Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, in which various details of the embodiments of the present invention are included to facilitate understanding, and are to be considered merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Currently, the configuration registers and hardware subordinate queues are fixed bindings. The hardware cannot be created, offloaded or migrated, and thus it is difficult to dynamically allocate hardware resources. Dynamic allocation of hardware resources can only be simulated by adding a software intermediate layer. At the same time, the use of a software middle layer also increases overhead. The transmission efficiency is reduced.
In order to solve the technical problems of increasing the system overhead and reducing the transmission efficiency, the following technical scheme in the embodiment of the invention can be adopted.
Referring to fig. 1, fig. 1 is a schematic diagram of a main flow of a method for allocating hardware resources according to an embodiment of the present invention, allocating a device identifier of a device register of a hardware device and an address index of a queue register of the hardware device to a client, and binding the device identifier and the address index, so as to receive an access request of the client to the hardware device. As shown in fig. 1, the method specifically comprises the following steps:
S101, distributing device identification of a device register of the hardware device and address index of a queue register of the hardware device for the client.
The client is a system which is operated on the host by a user, and the user can freely build a server on the system to operate own programs. The client obtains various hardware resources mainly through the host.
Referring to fig. 2, fig. 2 is a schematic view of an application scenario of a method for allocating hardware resources according to an embodiment of the present invention, and fig. 2 includes a client 1, a client 2, and a host.
The host may be located on a cloud computing platform, and the host may provide hardware resource services for the client 1 and the client 2, respectively.
As one example, client 1 may need to store 20 gigabytes (TB) of material at the host, which may provide 20TB of storage space for client 1 as required by client 1. As another example, client 2 requires a host to provide network capabilities to transfer large amounts of data. The host may provide the client 2 with the required network capabilities according to the requirements of the client 2.
In the embodiment of the present invention, the host may be an execution body of each step in fig. 1. The host includes a plurality of hardware devices. The registers of the hardware device are divided into device registers and queue registers according to different addressing modes. It will be appreciated that the device register and the queue register are addressed differently.
The device register is bound to each hardware device and accessed by a device identification and an address of the device register. As one example, the address of the device register may be preset. The queue register is bound with the queue and accessed through the queue index and the base address of the queue register. In conventional hardware devices, the number of queues to which each hardware device belongs is fixed.
In the embodiment of the invention, the queue under each hardware device is not fixed. With the establishment/unloading of the client, the hardware devices can be dynamically configured, and the number of queues to which each hardware device belongs can be dynamically configured.
From the client's perspective, the hardware is a single hardware device that belongs to several queues. As one example, the host may dynamically configure the relationship between the hardware device and the queue. Such as: the hardware device a is configured with 20 queues. Thus, the host can allocate queue resources for the client according to the 20 queues configured by the hardware device a.
The host allocates queue resources for the client, and may allocate device identification of a device register of the hardware device and an address index of the queue register of the hardware device for the client.
Specifically, the device identifier is a parameter of the hardware device accessed by the client, and the hardware device accessed by the client can be known according to the device identifier. For a hardware device, one device register may be mapped, then the client may be assigned a device identification of the device register of the hardware device.
Each hardware device belongs to a plurality of queues, the queues are bound with the queue registers, and the queue registers can be accessed through the address indexes of the queue registers, so that the address indexes of the queue registers of the hardware device can be allocated for clients.
S102, binding the device identification of the allocated device register with the address index of the allocated queue register, and storing the queue index base address of the queue register and the number of the allocated queues to allocate the queue resources of the hardware device to the client.
After the device identifier of the device register of the hardware device and the address index of the queue register of the hardware device are allocated to the client, the hardware device may also correspond to other queues because the hardware device and the queue are not in a fixed correspondence.
To facilitate client access to hardware devices, the device identification of the assigned device register may be bound to the address index of the assigned queue register. As one example, the address index of the allocated queue register may be stored in a device-specific register.
One or more queues are allocated to clients, each queue being bound to a queue register. In the case of a plurality of queues allocated for clients, the address indexes of the plurality of queue registers are consecutive.
The queue index base address is the base address of the first address index of the address indices of the plurality of queue registers. The offset of the queue index may be known from a queue offset register in the device register. In combination with the offset of the queue index based on the base of the queue index, the client can access the assigned queue register of the hardware device.
Thus, the queue index base address of the queue register and the number of queues may be stored. In this way, queue resources of the hardware device may be allocated to the client. The queue offset is self-configuring when the client accesses the queue resource.
In one embodiment of the invention, the device identification and address index may be bound by setting a queue index base table and a queue index offset table, as well as storing the queue index base of the queue register and the number of allocated queues.
The queue index base table records a correspondence of device identifications to queue register base addresses. The base address of the queue register can be obtained by looking up the queue index base address table based on the device identification. The queue index base of the queue register is determined by the number of clients and the number of queues allocated per client.
The base of the queue index of the queue register is the address of the queue register of the first queue allocated to the client. The addresses of queues assigned to the same client by the hosts must be consecutive. For example, the host has allocated 3 queues to the current client. The first queue has a queue register address of base0, the second queue has a queue register address of base0+1, and the third queue has a queue register address of base0+2.
The queue index offset table records the relationship of the device identification to the offset, which is determined by the number of allocated queues. It will be appreciated that the maximum offset is equal to the number of queues allocated to the client minus 1.
S103, receiving an access request of the client to the hardware device, wherein the access request comprises a device identifier of a device register.
The host may send the device identification of the assigned device register to the client to allocate queue resources of the hardware device. The client may send an access request to the host to access the hardware device, the access request including a device identification of a device register of the hardware device.
As one example, a host receives a client access request to a hardware device, the access request including a device identification of a device register. The client may access the device register based on the device flag of the device register.
It should be noted that the address of the device register is preset, and both the host and the client have knowledge of the address of the device register, since it is not necessary to separately send the address of the device register to the client. As one example, the address of the device register is set in accordance with the high speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI-Express).
In one embodiment of the invention, a host receives a client access request to a hardware device, the access request including a device identification of a device register and an offset of a queue register. The client may access the queue register based on the device identification of the device register and the offset of the queue register.
In one embodiment of the invention, the host allocates queue resources of the hardware device for the client. In the case where the hardware device needs to be migrated, such as: the host allocates queue resources of hardware device a for the client. Because of the failure of hardware device a, in order not to apply the normal use of queue resources by the client, it is necessary to migrate the client from hardware device a to hardware device b, which is referred to as the target hardware device.
Referring to fig. 3, fig. 3 is a schematic flow chart of a migration hardware device according to an embodiment of the present invention, which specifically includes:
S301, reallocating the queue resources of the target hardware device according to the device identification of the device register and the number of the allocated queues.
In the embodiment of the invention, the hardware device to which the client is migrated is referred to as a target hardware device. The target hardware device is subordinate to the plurality of queues. Considering that migration of the hardware device affects the client as little as possible, the client accesses the host based on the device identifier of the device register, and then the queues of the target hardware device may be reassigned according to the device identifier of the device register and the number of assigned queues. In this way, the device identification of the device register in the access request is unchanged for the client.
S302, binding the device identification of the device register with the address index of the reassigned queue register, and storing the queue index base address of the reassigned queue register and the number of assigned queues to migrate the client to the target hardware device.
Similar to the process of assigning a hardware device to a client, it is necessary to bind the device identification of the device register with the address index of the reassigned queue register and store the queue index base address of the reassigned queue register and the number of assigned queues to migrate the client to the target hardware device.
In the embodiment of fig. 3, it is desirable to migrate a client from one hardware device to another, and to reduce the impact on the client, reassignment may be performed according to the device identification of the original device register and the number of assigned queues.
In one embodiment of the invention, the assigned device registers and assigned queue registers may be released in the event that a client on a hardware device has migrated to another hardware device, or in the event that the client no longer needs to use the hardware device.
Specifically, the binding relationship of the device identification of the allocated device register and the address index of the allocated queue register is deleted, and the queue index base address of the queue register and the number of allocated queues are deleted. In this way, the allocated device registers and allocated queue registers may also be allocated to other clients.
In one embodiment of the invention, the device identification of the assigned device register may be bound to the address index of the assigned first queue register. The purpose of this is to: all queue registers may be accessed sequentially based on the address index of the first queue register and the number of allocated queues.
As an example, for device identity a, the address index of the allocated first queue register is base1, binding device identity a and base1. The number of allocated queues is 10, the address index of the queue register is consecutive, the offset is equal to the number of allocated queues-1, i.e. the offset ranges from 0 to 9. By changing base1 and offset from small to large, 10 queue registers can be accessed sequentially.
In one embodiment of the invention, the host needs to allocate queue resources for the hardware device and the client needs to access the hardware device. In order to facilitate the hardware device to identify the host and the client, different addresses need to be set for the host and the client. Wherein the hardware device involves a device register and a queue register.
Specifically, the client accesses the device register through a first device register address, and the host accesses the device register through a second device register address; the client accesses the queue register via the first queue register address and the host accesses the queue register via the second queue register address.
As an example, the first device register address and the second device register address belong to different device register address segments by which it is possible to distinguish between a client accessing a device register, or a host accessing a device register.
Similarly, the first queue register address and the second queue register address belong to different queue register address segments by which it can be distinguished whether a client accesses a queue register or a host accesses a queue register.
In the above embodiment, first, the device identifier of the device register of the hardware device and the address index of the queue register of the hardware device are allocated to the client; then binding the device identification of the allocated device register with the address index of the allocated queue register, and storing the queue index base address of the queue register and the number of allocated queues to allocate the queue resources of the hardware device to the client; finally, an access request of the client to the hardware device is received, the access request including a device identification of the device register. After the hardware equipment resources are allocated, the client can directly access the queue resources without adopting a software middle layer, so that the system overhead can be reduced, and the transmission efficiency is improved.
The technical scheme of the present invention is exemplarily described below with reference to specific embodiments and drawings.
In an embodiment of the invention, the channel in which the client accesses the hardware configuration registers is referred to as the front-end configuration channel. The channel in which the host accesses the hardware configuration registers is referred to as the backend configuration channel. The hardware configuration register is a register for storing configuration parameters of client access hardware.
Referring to fig. 4, fig. 4 is a schematic diagram of a differentiated-access configuration channel according to an embodiment of the present invention, which specifically includes:
s401, a register access request.
The hardware device receives the register access request.
S402, the base address of the access address belongs to the front-end configuration channel.
Judging whether the access address belongs to the front-end configuration channel or the back-end configuration channel according to the base address of the access address. Because the address field of the front-end configuration channel is different from the address field of the back-end configuration channel, the base address of the front-end configuration channel is different from the base address of the back-end configuration channel. It is understood that the access address is a preset address.
If the base address of the access address belongs to the front-end configuration channel, executing S403; if the base address of the access address belongs to the back-end configuration channel, S404 is executed.
S403, entering a front end configuration channel.
The access request is of a client, and then enters the front-end configuration channel.
S404, entering a back end configuration channel.
The access request is of the host, and enters the back-end configuration channel.
Referring to fig. 5, fig. 5 is a schematic diagram of an access configuration channel according to an embodiment of the present invention, which specifically includes:
the client can directly access the device register by using the device identifier and the address of the device register through the front-end configuration channel, and access the queue register by using the queue index base address and the offset.
The host can directly access the device registers and the queue registers through the back-end configuration channel.
Referring to fig. 6, fig. 6 is a schematic flow chart of accessing a register by a host according to an embodiment of the present invention, which specifically includes:
S601, judging whether to access a queue register.
Whether the host accesses the queue register can be judged, and if the host accesses the queue register, S602 is executed; if the host does not access the queue register, the device register is accessed, and S603 is executed. As one example, the host may access the queue register or the device register by an address determination.
S602, accessing a queue index register.
The host may access a queue index register in which a queue index is stored. The host obtains the queue index from the queue index register according to the address.
S603, accessing a device number register.
The host can access the device number register in which the device number, i.e., the device identification, is stored. The host obtains the device number from the device number register according to the address.
S604, accessing a queue register.
The host accesses the queue register based on the address and the queue index.
S605, accessing a device register.
The host accesses the device register based on the address and the device number.
Referring to fig. 7, fig. 7 is a schematic flow chart of accessing a register by a client according to an embodiment of the present invention, specifically including:
S701, judging whether to access a queue register.
The client can determine whether to access the queue register itself. If the client accesses the queue register, then S702 is performed; if the client does not access the queue register, the device register is accessed, and S703 is executed.
As one example, a client may send an access request that includes a device number and does not include an offset, then accessing a device register; the access request includes the device number and the offset, the queue register is accessed.
S702, setting an offset.
The queue index base address table stores base addresses, and the client searches the queue index base address table based on the device number to obtain the base addresses. And setting an offset on the basis of the base address to obtain the address of the queue register.
S703, directly accessing a device register.
The client can directly access the device register by means of the device number and the address of the device register.
S704, accessing a queue register.
The client can access the queue register allocated by the host through the address of the queue register.
Referring to fig. 8, fig. 8 is a schematic flow chart of a hardware device accepting host access according to an embodiment of the present invention, which specifically includes:
S801, a back-end access request.
The hardware device receives an access request of the host, namely, a back-end access request.
S802, judging whether to access a device register.
And judging whether to access the device register according to the access address. If the host accesses the device register, then S803 is performed; if the host does not access the device register and accesses the queue register, S804 is performed.
S803, the device number is fetched from the back-end access device number register.
The relationship between the device number and the address is recorded in the back-end access device number register, and the device number can be fetched from the back-end access device number register based on the address.
S804, the queue index is fetched from the rear end access queue index register.
The relation between the queue index and the address is recorded in the back-end access queue index register, and the queue index can be fetched from the back-end access queue index register based on the address.
S805, accessing a device register.
The host accesses the device register according to the address and device number.
S806, accessing a queue register.
The host queues the registers according to the address and queue index.
Referring to fig. 9, fig. 9 is a schematic flow chart of accepting access of a client by a hardware device according to an embodiment of the present invention, which specifically includes:
s901, a client access request.
The client sends an access request and the address of the device register is preset.
S902, judging whether to access a device register.
Judging whether to access the device register according to the address of the device register, if so, executing S903; if the device register is not accessed, and the address of the device register is not included in the access request, S904 is performed.
S903, accessing a device register.
The client accesses the device register based on the device number and the address of the device register.
S904, accessing the queue index base address table.
And acquiring the queue index base address from the queue index base address table according to the equipment number.
S905, accessing a queue index offset table.
And acquiring the offset in the queue index offset table according to the equipment number.
S906, obtaining a queue index.
And combining the base address of the queue index and the offset to obtain the address of the queue register.
S907, accessing a queue register.
The queue register is accessed according to the address of the queue register.
Referring to fig. 10, fig. 10 is a schematic diagram of a main structure of an apparatus for allocating hardware resources according to an embodiment of the present invention, where the apparatus for allocating hardware resources may implement a method for allocating hardware resources, and as shown in fig. 10, the apparatus for allocating hardware resources specifically includes:
An allocation module 1001 is configured to allocate, for a client, a device identifier of a device register of a hardware device and an address index of a queue register of the hardware device.
A binding module 1002 for binding the device identification of the allocated device register with the address index of the allocated queue register, and storing the queue index base address of the queue register and the number of allocated queues to allocate the queue resources of the hardware device to the client.
An access module 1003 is configured to receive an access request from a client to a hardware device, where the access request includes a device identifier of a device register.
In one embodiment of the present invention, the binding module 1002 is further configured to reallocate queue resources of the target hardware device according to the device identifier of the device register and the number of allocated queues;
The device that binds the device register identifies an address index with the reassigned queue register and stores a queue index base address of the reassigned queue register and a number of assigned queues to migrate the client to the target hardware device.
In one embodiment of the present invention, the binding module 1002 is further configured to delete the binding relationship between the device identifier of the allocated device register and the address index of the allocated queue register, and delete the queue index base address of the queue register and the number of allocated queues to release the allocated device register and the allocated queue register.
In one embodiment of the invention, the binding module 1002 is specifically configured to set a queue index base table and a queue index offset table,
The queue index base table records a correspondence of device identifications with queue register base addresses, the queue index base addresses of the queue registers being determined by the number of clients and the number of allocated queues,
The queue index offset table records the relationship of the device identification to the offset, which is determined by the number of allocated queues.
In one embodiment of the invention, the access request further includes an offset of the queue register, the offset being determined by the number of allocated queues.
In one embodiment of the invention, the binding module 1002 is specifically configured to bind the device identifier of the allocated device register with the address index of the allocated first queue register.
In one embodiment of the invention, the device register maps to a first device register address and a second device register address, the queue register maps to a first queue register address and a second queue register address,
The client accesses the device register via the first device register address, the host accesses the device register via the second device register address,
The client accesses the queue register via the first queue register address and the host accesses the queue register via the second queue register address.
Fig. 11 illustrates an exemplary system architecture 1100 to which a method of allocating hardware resources or an apparatus of allocating hardware resources of an embodiment of the present invention may be applied.
As shown in fig. 11, system architecture 1100 may include terminal devices 1101, 1102, 1103, a network 1104, and a server 1105. Network 1104 is the medium used to provide communication links between terminal devices 1101, 1102, 1103 and server 1105. Network 1104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, among others.
A user may interact with the server 1105 via the network 1104 using the terminal devices 1101, 1102, 1103 to receive or transmit messages, etc. Various communication client applications such as shopping class applications, web browser applications, search class applications, instant messaging tools, mailbox clients, social platform software, and the like (by way of example only) may be installed on terminal devices 1101, 1102, 1103.
The terminal devices 1101, 1102, 1103 may be a variety of electronic devices having a display screen and supporting web browsing, including but not limited to smartphones, tablets, laptop and desktop computers, and the like.
The server 1105 may be a server that provides various services, such as a background management server (by way of example only) that provides support for shopping-type websites browsed by users using the terminal devices 1101, 1102, 1103. The background management server may analyze and process the received data such as the product information query request, and feedback the processing result (e.g., the target push information, the product information—only an example) to the terminal device.
It should be noted that, the method for allocating hardware resources provided in the embodiment of the present invention is generally executed by the server 1105, and accordingly, the device for allocating hardware resources is generally disposed in the server 1105.
It should be understood that the number of terminal devices, networks and servers in fig. 11 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.
Referring now to FIG. 12, there is illustrated a schematic diagram of a computer system 1200 suitable for use in implementing an embodiment of the present invention. The terminal device shown in fig. 12 is only an example, and should not impose any limitation on the functions and the scope of use of the embodiment of the present invention.
As shown in fig. 12, the computer system 1200 includes a Central Processing Unit (CPU) 1201, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1202 or a program loaded from a storage section 1208 into a Random Access Memory (RAM) 1203. In the RAM 1203, various programs and data required for the operation of the system 1200 are also stored. The CPU 1201, ROM 1202, and RAM 1203 are connected to each other through a bus 1204. An input/output (I/O) interface 1205 is also connected to the bus 1204.
The following components are connected to the I/O interface 1205: an input section 1206 including a keyboard, a mouse, and the like; an output portion 1207 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage section 1208 including a hard disk or the like; and a communication section 1209 including a network interface card such as a LAN card, a modem, or the like. The communication section 1209 performs communication processing via a network such as the internet. The drive 1210 is also connected to the I/O interface 1205 as needed. A removable medium 1211 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on the drive 1210 so that a computer program read out therefrom is installed into the storage section 1208 as needed.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flow chart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication portion 1209, and/or installed from the removable media 1211. The above-described functions defined in the system of the present invention are performed when the computer program is executed by a Central Processing Unit (CPU) 1201.
The computer readable medium shown in the present invention may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present invention, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules involved in the embodiments of the present invention may be implemented in software or in hardware. The described modules may also be provided in a processor, for example, as: a processor includes a transmitting unit, an acquiring unit, a determining unit, and a first processing unit. The names of these units do not constitute a limitation on the unit itself in some cases, and for example, the transmitting unit may also be described as "a unit that transmits a picture acquisition request to a connected server".
As another aspect, the present invention also provides a computer-readable medium that may be contained in the apparatus described in the above embodiments; or may be present alone without being fitted into the device. The computer readable medium carries one or more programs which, when executed by a device, cause the device to include:
Assigning a device identification of a device register of a hardware device and an address index of a queue register of the hardware device to a client;
binding a device identification of the allocated device register with an address index of the allocated queue register, and storing a queue index base address of the queue register and a number of allocated queues to allocate queue resources of the hardware device to the client;
An access request of the client to the hardware device is received, the access request including a device identification of a device register.
According to the technical scheme of the embodiment of the invention, firstly, equipment identification of equipment registers of hardware equipment and address indexes of queue registers of the hardware equipment are allocated for clients; then binding the device identification of the allocated device register with the address index of the allocated queue register, and storing the queue index base address of the queue register and the number of allocated queues to allocate the queue resources of the hardware device to the client; finally, an access request of the client to the hardware device is received, the access request including a device identification of the device register. In the process of distributing hardware equipment resources, the queue resources of the hardware equipment can be distributed to clients without adopting a software middle layer, so that the system overhead can be reduced, and the transmission efficiency is improved.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives can occur depending upon design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (9)
1. A method of allocating hardware resources, comprising:
Assigning a device identification of a device register of a hardware device and an address index of a queue register of the hardware device to a client;
binding a device identification of the allocated device register with an address index of the allocated queue register, and storing a queue index base address of the queue register and a number of allocated queues to allocate queue resources of the hardware device to the client;
receiving an access request of the client to the hardware device, wherein the access request comprises a device identifier of a device register;
The binding the device identification of the allocated device register with the address index of the allocated queue register and storing the queue index base address of the queue register and the number of allocated queues, comprising:
a queue index base table and a queue index offset table are set,
The queue index base table records a correspondence of device identifications with queue register base addresses, the queue index base addresses of the queue registers being determined by a number of clients and a number of the allocated queues,
The queue index offset table records a relationship of device identifications to offsets, the offsets being determined by the number of allocated queues.
2. The method of allocating hardware resources of claim 1, wherein said binding the device identification of the allocated device register with the address index of the allocated queue register, and after storing the queue index base address of the queue register and the number of allocated queues, further comprises:
reallocating queue resources of the target hardware device according to the device identifier of the device register and the number of the allocated queues;
The device identifier of the device register is bound to the address index of the reassigned queue register and the queue index base address of the reassigned queue register and the number of assigned queues are stored to migrate the client to the target hardware device.
3. The method of allocating hardware resources of claim 1, wherein said binding the device identification of the allocated device register with the address index of the allocated queue register, and after storing the queue index base address of the queue register and the number of allocated queues, further comprises:
deleting the binding relationship of the device identification of the allocated device register and the address index of the allocated queue register, and deleting the queue index base address of the queue register and the number of allocated queues to release the allocated device register and the allocated queue register.
4. The method of allocating hardware resources of claim 1, wherein the access request further comprises an offset of the queue register, a maximum of the offset being determined by the number of allocated queues.
5. The method of allocating hardware resources of claim 1, wherein said binding the device identification of the allocated device register with the address index of the allocated queue register comprises:
The device identification of the assigned device register is bound to the address index of the assigned first queue register.
6. The method of allocating hardware resources of claim 1, wherein the device register maps to a first device register address and a second device register address, the queue register maps to a first queue register address and a second queue register address,
The client accesses the device register via a first device register address, the host accesses the device register via a second device register address,
The client accesses the queue register via a first queue register address and the host accesses the queue register via a second queue register address.
7. An apparatus for allocating hardware resources, comprising:
An allocation module, configured to allocate, for a client, a device identifier of a device register of a hardware device and an address index of a queue register of the hardware device;
A binding module for binding a device identifier of an allocated device register with an address index of the allocated queue register, and storing a queue index base address of the queue register and the number of allocated queues to allocate queue resources of the hardware device to the client; setting a queue index base address table and a queue index offset table, wherein the queue index base address table records the corresponding relation between equipment identification and a queue register base address, the queue index base address of the queue register is determined by the number of clients and the number of allocated queues, the queue index offset table records the relation between equipment identification and offset, and the offset is determined by the number of allocated queues;
and the access module is used for receiving an access request of the client to the hardware device, wherein the access request comprises the device identification of the device register.
8. An electronic device for allocating hardware resources, comprising:
one or more processors;
Storage means for storing one or more programs,
When executed by the one or more processors, causes the one or more processors to implement the method of any of claims 1-6.
9. A computer readable medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method according to any of claims 1-6.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106445628A (en) * | 2015-08-11 | 2017-02-22 | 华为技术有限公司 | Virtualization method, apparatus and system |
| CN107015845A (en) * | 2015-12-02 | 2017-08-04 | 想象技术有限公司 | GPU vitualization |
| CN110199512A (en) * | 2017-12-26 | 2019-09-03 | 华为技术有限公司 | The management method and device of equipment are stored in storage system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9606936B2 (en) * | 2010-12-16 | 2017-03-28 | Advanced Micro Devices, Inc. | Generalized control registers |
| WO2018152688A1 (en) * | 2017-02-22 | 2018-08-30 | Intel Corporation | Virtualization of process address space identifiers for scalable virtualization of input/output devices |
-
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106445628A (en) * | 2015-08-11 | 2017-02-22 | 华为技术有限公司 | Virtualization method, apparatus and system |
| CN107015845A (en) * | 2015-12-02 | 2017-08-04 | 想象技术有限公司 | GPU vitualization |
| CN110199512A (en) * | 2017-12-26 | 2019-09-03 | 华为技术有限公司 | The management method and device of equipment are stored in storage system |
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