CN111781204A - Method for testing annular faults of semiconductor round silicon wafer - Google Patents
Method for testing annular faults of semiconductor round silicon wafer Download PDFInfo
- Publication number
- CN111781204A CN111781204A CN202010548224.1A CN202010548224A CN111781204A CN 111781204 A CN111781204 A CN 111781204A CN 202010548224 A CN202010548224 A CN 202010548224A CN 111781204 A CN111781204 A CN 111781204A
- Authority
- CN
- China
- Prior art keywords
- silicon wafer
- test points
- round silicon
- positions
- particles
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8851—Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/32—Polishing; Etching
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/34—Purifying; Cleaning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/44—Sample treatment involving radiation, e.g. heat
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/9501—Semiconductor wafers
- G01N21/9505—Wafer internal defects, e.g. microcracks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N2021/8477—Investigating crystals, e.g. liquid crystals
Abstract
The invention discloses a method for testing an annular fault of a semiconductor round silicon wafer, which comprises the following steps: selecting a plurality of groups of radially symmetrical test points on the plane of the circular silicon wafer; carrying out microdefect particle analysis on the positions of the round silicon wafer corresponding to the test points, wherein the microdefect particles corresponding to each group of test points are consistent in number or have a difference value, and the positions of a plurality of adjacent groups of test points which are located between the positions of the group of test points corresponding to the largest microdefect particle number and correspond to the small microdefect particle number are all on the annular staggered positions of the round silicon wafer; and an annular area which is positioned between the positions of the group of test points corresponding to the maximum number of the micro-defect particles and is formed by drawing circles by taking the positions of the adjacent groups of test points with the small number of the micro-defect particles as radii is the annular fault. The method adopts a physical testing method, is easy to judge and can accurately represent the specific position of OISF in the silicon wafer, particularly, the macroscopic position judgment is more accurate, the detection steps are simplified, the detection time is shortened, the environment is protected, and the testing efficiency is high.
Description
Technical Field
The invention belongs to the technical field of defect analysis of semiconductor material silicon single crystal and silicon wafers, and particularly relates to a method for testing annular stacking faults of a semiconductor round silicon wafer.
Background
The Czochralski silicon single crystal is influenced by a series of factors such as a crystal furnace, auxiliary material materials, polycrystalline material purity, furnace body environment, temperature gradient, crystal pulling speed, thermal history curve and the like in the growth process, so that impurities and lattice defects are inevitably generated in the single crystal. The conventional defects of the silicon single crystal mainly comprise defects such as faults, dislocation, vortex and the like, some defects can be directly analyzed and tested by using a primary silicon wafer, and some defects need to be tested after high-temperature oxidation induction. However, whether the original defects or the induced defects exist, the traditional detection mode is to analyze the defects by using a chemical corrosion method when needed.
Among these lattice defects, particularly Oxidation Induced Stacking Faults (OISF) are a very common defect phenomenon, which forms recombination-generating centers and scattering centers for carriers, and may also cause adverse phenomena such as leakage channels and other defect nucleation centers, which have a great influence on the performance of semiconductor devices.
In a commonly used chemical etching method for detecting oxidation induced stacking faults, a relatively commonly used chemical etching solution is a mixed solution prepared from chromium trioxide, hydrofluoric acid and ultrapure water according to a certain proportion. The method has high requirement on the purity of chemicals, has certain influence on the corrosion effect if the chemicals have more metal impurities, is easy to have fog on the surface of a silicon wafer, has certain interference on analysis and observation after corrosion, and has certain requirement on the corrosion conditions, such as corrosion temperature, time, the use frequency of a corrosion solution and the like. But the most important is that chromium trioxide can pollute water bodies, and used chemicals belonging to environmental control classes need to have certain qualifications for use, so that the development of a physical method instead of a chemical method is not slow, the development of the physical method not only can improve the test accuracy, but also makes positive contribution to environmental protection, and the development of a new method has certain social significance.
Disclosure of Invention
The invention provides a method for testing annular faults of a semiconductor round silicon wafer, which mainly adopts a physical method to test the annular faults on the surface of the round silicon wafer with a large diameter and solves the technical problems of complicated testing process flow, discharge of chromium-containing chemicals, long testing time and low efficiency caused by adopting a chemical method in the prior art.
In order to solve the technical problems, the invention adopts the technical scheme that:
a method for testing the ring-shaped stacking fault of a semiconductor round silicon wafer comprises the following steps:
selecting a plurality of groups of radially symmetrical test points on the plane of the circular silicon wafer;
analyzing the micro-defect particles at the positions of the round silicon chip corresponding to the test points, wherein the number of the micro-defect particles corresponding to each group of the test points is consistent or is a difference value,
the positions of a plurality of adjacent test points which are positioned between the positions of the test points corresponding to the group with the largest number of the micro-defect particles and correspond to the small number of the micro-defect particles are all on the annular staggered positions of the round silicon wafer;
and an annular area which is positioned between the positions of a group of test points corresponding to the largest number of the micro-defect particles and is formed by drawing circles by taking the positions of a plurality of adjacent groups of test points with the smaller number of the micro-defect particles as radii is the annular fault.
Furthermore, the positions of the test points are all located in the same semicircle of the round silicon wafer, and the radial distance between the outermost test point and the edge of the excircle of the round silicon wafer is at least 10-15 mm.
Furthermore, the test points are arranged at equal intervals along the diameter direction of the semicircle of the round silicon wafer, and the test points are symmetrical relative to the circle center of the round silicon wafer.
Furthermore, the test points are all arranged on the same straight line parallel to the diameter of the round silicon wafer; the spacing distance between adjacent test points is not more than 10 mm.
Further, the ratio of the difference of the number of the microdefect particles corresponding to each group of the test points to the average number of the microdefect particles is greater than 0 and less than 3%.
Furthermore, the positions of the test points are used as an X axis, the number of the micro-defect particles is used as a Y axis, the micro-defect particles corresponding to the test points are sequentially connected to form a curve waveform distribution diagram, and the waveform distribution diagram is symmetrical relative to the axis of the position of the circle center.
Furthermore, the two micro-defect particle number peak values in the waveform distribution diagram are the same or within the difference range, and the corresponding test point positions are symmetrical relative to the circle center; the positions of the test points corresponding to the valleys between the peaks of the number of the micro-defect particles are within the annular stacking faults.
Further, before the test points are arranged on the plane of the round silicon wafer, the method also comprises the step of cleaving the round silicon wafer to form a semi-round silicon wafer.
Further, the cleavage comprises the step of decomposing the round silicon wafer along the diameter side of the V-shaped groove arranged at the outer edge of the round silicon wafer.
Further, the V-shaped groove is arranged in the crystal orientation of the round silicon wafer (110).
Compared with the prior art, the physical test method designed by the invention replaces the traditional chemical treatment method, and through analyzing the radial distribution diagram of the defect number, the radial distribution of the silicon wafer presents a symmetrical distribution trend of high and low, which shows that the number density of the positions of the annular region is obviously lower than that of the position of the central region, and after passing through the annular region, the density is increased sharply and then is reduced, namely, the distribution diagram presents a regular low-density symmetrical position macroscopically. The method is easy to judge and can accurately represent the specific position of OISF in the silicon wafer, particularly, the macroscopic position judgment is more accurate, the detection steps are simplified, the detection time is shortened, the test effect is good, the efficiency is high, the use of toxic and harmful chemicals is saved, the discharge of chromium-containing wastewater is avoided, and the effect of environmental protection is achieved.
Drawings
FIG. 1 is a diagram of the position of a test point on a circular silicon wafer according to the present invention;
FIG. 2 is a waveform distribution diagram of the number of micro-defect particles in a 1-1# wafer according to a first embodiment of the present invention;
FIG. 3 is a waveform distribution diagram of the number of micro-defect particles in a 2-1# round silicon wafer according to example two of the present invention;
FIG. 4 is a macroscopic photograph of the surface of a 1-2# round silicon wafer after chemical etching under the irradiation of a darkroom strong light;
FIG. 5 is a macroscopic photograph of the surface of a 2-2# round silicon wafer after chemical etching under the irradiation of a darkroom strong light;
FIG. 6 is a photomicrograph under a microscope of a 1-2# round silicon wafer after chemical etching;
FIG. 7 is a photomicrograph under a microscope of a 2-2# round silicon wafer after chemical etching.
In the figure:
10. round silicon chip 20, test point 30, annular fault
40. Straight line 50, V-shaped groove
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
In the prior art, the conventional testing method comprises the following steps: firstly, the round silicon wafer after high-temperature oxidation induction is acid-washed to remove an oxidation film, namely, HF and H with specific configuration proportion are used at a certain temperature2The mixed solution of O is applied to a layer of SiO on the surface of the round silicon chip2Cleaning the oxide film with HF and SiO2The reaction produces H which is easily dissolved in water2SiF6A complex compound; the second step is that: carrying out at least two times of pure water washing on the round silicon wafer after the acid washing to remove particulate impurities and residual acid washing liquid medicine on the surface of the round silicon wafer; the third step: then, carrying out slow lifting and drying on the cleaned round silicon wafer in sequence; the fourth step: then carrying out chemical corrosion on the surface of the dried round silicon wafer, even if the round silicon wafer is placed in a mixed solution prepared by chromium trioxide, hydrofluoric acid and ultrapure water according to a certain proportion at a certain temperature for corrosion, corroding for a certain time under the condition of keeping the mixed solution unchanged, and then taking out the round silicon wafer; the fifth step: washing the corroded round silicon wafer with pure water in sequence to remove corrosion residual solution and microscopic impurities on the surface of the corroded round silicon wafer; and a sixth step: slowly pulling, drying and drying the cleaned round silicon wafer; the seventh step: and then, carrying out macroscopic observation and microscopic observation on the corroded round silicon wafer in a darkroom under certain strong light in sequence to determine whether the ring-shaped distributed faults exist or not under a microscope.
The embodiment provides a method for testing an annular stacking fault of a semiconductor wafer, which comprises the following steps:
s1: firstly, cleaning the surface of the round silicon wafer 10, and then carrying out high-temperature oxidation induction on annular faults in the cleaned round silicon wafer, wherein the method specifically comprises the following steps:
the method comprises the steps of carrying out mechanical chemical polishing on the round silicon wafer 10, then cleaning the round silicon wafer by using a mixed liquid medicine of ammonia water and hydrogen peroxide in a certain proportion, washing the round silicon wafer by using pure water, finally cleaning the round silicon wafer by using a mixed liquid medicine of hydrochloric acid and hydrogen peroxide in a certain proportion, and finally cleaning the round silicon wafer by using ultrapure water, and then drying the round silicon wafer 10. Of course, the required mixture ratio of the ammonia water and the hydrogen peroxide solution and the mixture ratio of the hydrochloric acid and the hydrogen peroxide solution are different for different sizes and numbers of the silicon wafers 10, and are not particularly limited herein. After cleaning, the round silicon wafer 10 is put into a furnace in a dry oxygen furnace at 800 +/-5 ℃, the temperature is raised to 1100 +/-5 ℃ within 60 +/-1 min under the dry oxygen atmosphere, then the temperature is kept constant for 60 +/-1 min under the wet oxygen atmosphere, the temperature is lowered to 800 +/-5 ℃ within 100 +/-1 min under the dry oxygen atmosphere, and the round silicon wafer 10 is taken out of the furnace at 800 +/-5 ℃. The main purpose of the high temperature oxidation process is to nucleate and grow micro-defects in the wafer 10, and to amplify the micro-defects by further etching, thereby facilitating observation.
The whole round silicon wafer 10 is cleaved along the diameter direction to form a semi-circle silicon wafer 10, and the crystal orientation of the reference position (110) of the round silicon wafer 10 is generally selected for cleavage; in the national standard, a V-shaped groove 50 of a reference position convenient for identification and positioning is usually processed in a (110) crystal direction of a round silicon wafer 10, and the (110) crystal direction is the edge point of the round semiconductor silicon wafer 10 in the single crystal growth process and is cleaved along the diameter of the central axis of the V-shaped groove 50, so that the cleavage position can be ensured to verify the lattice direction for natural cleavage, and cracks or fragments of the round silicon wafer 10 can be prevented from occurring in the decomposition process, because the crossed part of the edge line of the non-silicon round rod of the round silicon wafer 10 and the round silicon wafer 10 has more dislocations, once the decomposition is not smooth, cracks, bumps and the like are easy to generate, and the test effect of annular stacking faults is influenced.
S2: selecting a plurality of groups of radially symmetrical test points 20 on the plane of the circular silicon wafer 10, then carrying out microdefect particle analysis on the positions corresponding to the test points 20 on the circular silicon wafer 10 in an infrared optical imaging device, and judging the region of the annular dislocation position according to the microdefect particle distribution diagram.
Specifically, as shown in fig. 1, the test points 20 are all located in the same semicircle of the circular silicon wafer 10, and the radial distance D between the outermost test point 20 and the outer edge of the circular silicon wafer 10 is at least 10-15mm, because the closer the edge of the circular silicon wafer is, the farther the distance between the outermost test point 20 and the outer edge of the circular silicon wafer is relative to the annular stacking fault 30, the smaller the number of micro-defect particles in the position point is, the weaker the reference value for the number of micro-defect particles in the annular stacking fault 30 is, and meanwhile, in the interval of 10-15mm from the edge of the outer circle of the circular silicon wafer, the point taking is not easily set, the operation difficulty is large, and the time is wasted.
Furthermore, the selected test points 20 are all arranged at equal intervals along the semi-circle diameter direction of the round silicon wafer 10, the test points 20 are all arranged on a straight line 40 parallel to the diameter of the round silicon wafer 10, the test points 20 are all symmetrically arranged relative to the central point of the straight line 40, and the vertical distance H between the straight line 40 and the semi-circle diameter is at least larger than 3mm and not larger than the minimum radius of the annular faults 30. That is, the test points 20 are symmetrically arranged along the diameter direction at a certain distance from the left to the right with the center of the circular silicon wafer 10 as 0 point, and all the test points 20 are located on the straight line 40.
Preferably, the distance between adjacent test points 20 is not more than 10mm, and the smaller the distance is, for example, 5mm,3mm,2mm, etc., the distribution of the number of the microdefect particles corresponding to the test points is measured to be more detailed, so that the variation rule of the number of the microdefect particles can be more easily seen.
After the positions of the test points 20 are determined, the round silicon wafer 10 is pushed into an infrared optical imaging device for continuous testing, the infrared optical imaging device can automatically focus and pick up the round silicon wafer 10, carry out alignment according to the positions of the test points 20 set in advance, and display the number of the micro-defect particles at the position of each group of the test points 20 on the working platform interface. In this example, LST-2500 infrared optical imaging equipment was selected for testing and analysis. Because the internal lattice defects nucleate and grow in the high-temperature process after the round silicon wafer 10 is induced by high-temperature oxidation, the nucleation centers are presented in the form of punctiform particles in the infrared optical imaging equipment, and the infrared optical imaging equipment can automatically calculate the number of the punctiform micro-defect particles in each group of test points 20. When there are faults in the bulk of the wafer 10, the defect sites are larger in size but fewer in number than the sites without defects. By utilizing the difference and the growth change rule of the original defects in the single crystal growth process, the positions of the peak value and the inflection point with less defects and mutation of the defects are tested by an optical method, and the error position area of the oxide layer can be judged. That is, the positions of the circular silicon wafer 10 corresponding to the test points 20 are subjected to microdefect particle analysis, and the microdefect particles corresponding to each group of test points 20 are consistent in number, wherein the positions of the adjacent groups of test points 20, which are located between the positions of the group of test points 20 corresponding to the largest microdefect particle number and correspond to the smaller microdefect particle number, are all located at the position of the region of the ring-shaped stacking fault 30 of the circular silicon wafer 10. Correspondingly, the ring-shaped fault region is formed by taking the position of the group of test points 20 corresponding to the largest number of micro-defect particles and the position of a plurality of adjacent groups of test points 20 with the smaller number of micro-defect particles as the diameter.
Further, the positions of the test points 20 on the circular silicon wafer 10 are taken as an X axis, the number of the micro-defect particles is taken as a Y axis, the number of the micro-defect particles corresponding to the test points 20 is sequentially connected to form a curve waveform distribution diagram, the waveform distribution diagram is symmetrical relative to the axis of the circle center position, the peak values of the two micro-defect numbers in the waveform distribution diagram are consistent or have a difference, and the positions of the corresponding test points 20 are symmetrical relative to the circle center. That is, the test points 20 of each group are symmetrical with respect to the center of the circle, but due to the test deviation, the number of the microdefect particles corresponding to each group of test points 20 is not the same, and if the number of the microdefect particles corresponding to the group of test points 20 has a deviation, the ratio of the corresponding difference to the average microdefect particle number has a certain range, and the ratio is greater than 0 and less than 3%. In this embodiment, the number distribution of the microdefect particles corresponding to the test points 20 near the ring-shaped stacking fault 30 is dense, and the variation of the microdefect particle number difference value of each group of the test points 20 is small, within 0-3%; the test points 20 far away from the annular faults 30 and close to the outer edge of the round silicon wafer 10 are relatively small in the number of micro-defect particles and distributed relatively dispersedly, the difference value of the number of the micro-defect particles at the positions of the symmetrical test points 20 is relatively large in change, and the change rule of the difference value does not accord with the rule of 0-3%. Two groups of valleys between the peak values of the number of the micro-defect particles are basically the same, the positions of the test points 20 corresponding to the valleys are symmetrically arranged relative to the circle center, the positions of the test points 20 corresponding to the valleys are also in the region of the annular faults 30, and the annular region surrounded by the diameters of the positions of the test points 20 corresponding to the adjacent valleys is the position of the annular faults 30.
Take a lightly doped silicon single crystal P-type round silicon wafer with a diameter of 300mm as an example.
And cleavage is carried out along the position of the V-shaped groove 50 of each round silicon wafer to divide the round silicon wafers into two groups of semi-round silicon wafers, namely 1-1# round silicon wafer, 1-2# round silicon wafer, 2-1# round silicon wafer and 2-2# round silicon wafer. The number distribution rule of the micro-defect particles obtained by respectively testing the 1-1# round silicon wafer and the 1-2# round silicon wafer by adopting the physical method provided by the invention is compared with the number distribution rule of the micro-defect particles obtained by respectively testing the 2-1# round silicon wafer and the 2-2# round silicon wafer by adopting the traditional chemical corrosion method.
The first embodiment is as follows:
s1: the surface of the 1# round silicon wafer 10 is cleaned, and then the high-temperature oxidation induction is carried out on the ring-shaped faults in the cleaned 1# round silicon wafer 10.
S2: and cleaving the 1# circular silicon wafer 10 into two semicircular wafers along the V-shaped groove of the 1# circular silicon wafer 10, wherein the two semicircular wafers are respectively the 1-1# circular silicon wafer and the 1-2# circular silicon wafer.
Set up test point 20 that a plurality of groups symmetry set up on 1-1# circle silicon chip, test point 20 all sets up on the straight line 40 apart from the diameter limit 10mm department of semicircle silicon chip 10, and test point 20 uses the nodical dot O bilateral symmetry setting of centre of circle axis and straight line 40, and test point 20's interval distance is 5mm, is promptly from dot O left side to dot right side on straight line 40 respectively: -140mm, -135mm, -130mm, -125mm, -120mm.
After the positions of the test points 20 are determined, the 1-1# round silicon wafer is pushed into an infrared optical imaging device for continuous testing, the number of the micro-defect particles at the position of each group of the test points 20 is tested, and the distribution of the number of the measured micro-defect particles is shown in fig. 2. Referring to fig. 2, the X-axis represents the positions of the test points 20 on the # 1-1 semicircular silicon wafer 10, the Y-axis represents the number of the microdefect particles, and the waveform distribution diagram of the curve shows that the number of the microdefect particles obtained from each set of test points 20 symmetrical with respect to the dots O is the same, i.e., the number of the microdefect particles has two sets of peak values along the radial direction and two sets of valley values located between the peak values are symmetrically distributed with respect to the axis perpendicular to the dots O. Meanwhile, as can be seen from fig. 2, the value of the test point 20 corresponding to the peak position is 60-70mm, and the number value of the corresponding micro-defect particles is large and concentrated when the value is in the vicinity of the peak value, i.e. in the interval of 60-70 mm. And two groups of wave trough values begin to drop sharply again between the two wave peak values, the two groups of wave trough values are located within 40-50mm relative to the circle center, the number of micro-defect particles within 40-50mm of the wave trough values is small, the position of the test point 20 corresponding to the wave trough value is located at the position of the annular fault 30, and the position of the test point 20 corresponding to the adjacent wave trough value is taken as the position of the annular fault 30 surrounded by the diameter.
Example two:
s1: cleaning the surface of the 2# round silicon wafer, and then carrying out high-temperature oxidation induction on the annular faults in the cleaned 2# round silicon wafer.
S2: and (3) cleaving the 2# round silicon wafer along the V-shaped groove of the 2# round silicon wafer to form two semi-round wafers, namely a 2-1# round silicon wafer and a 2-2# round silicon wafer.
Set up test point 20 that a plurality of groups symmetry set up on 2-1# circle silicon chip, test point 20 all sets up on the straight line 40 apart from the diameter limit 10mm department of 2-1# semicircle silicon chip 10, and test point 20 uses the nodical point of central axis and straight line 40 to set up for dot O bilateral symmetry, and the interval distance of test point 20 is 5mm, is promptly from dot O left side to dot right side on straight line 40 respectively: -140mm, -135mm, -130mm, -125mm, -120mm.
After the positions of the test points 20 are determined, the 2-1# round silicon wafer is pushed into an infrared optical imaging device for continuous testing, the number of the micro-defect particles at the position of each group of the test points 20 is tested, and the distribution of the number of the measured micro-defect particles is shown in fig. 3. As shown in fig. 3, the X-axis is the position of the test point 20 on the # 2-1 semicircular silicon wafer 10, the Y-axis is the number of the microdefect particles, and the waveform distribution diagram of the curve shows that the number of the microdefect particles obtained from each set of test points 20 symmetrical with respect to the dot O has a small difference and is substantially consistent, that is, the microdefect particles have two sets of wave peak values in the radial direction and two sets of wave trough values between the two sets of wave peak values are symmetrical with respect to the axis perpendicular to the dot O. The positions of the two groups of wave peak values are within 75-90mm, the corresponding defect particles are more and concentrated, and the peak value is reached at the position of 80 mm; the two sets of valleys between the two valleys correspond to positions of 55mm to 70mm, with a lower number of defect particles and reach a low value at positions of 60 to 65 mm. That is, the region corresponding to 60-65mm in the valley is the radial position of the annular stacking fault 30, and the annular region obtained with 60-65mm as the radius is the region position of the annular stacking fault 30.
Meanwhile, the 1-2# semicircular silicon and the 2-2# semicircular silicon wafer are observed by adopting a traditional chemical method, which comprises the following specific steps:
sequentially carrying out high-temperature oxidation induction, acid washing to remove an oxidation film, two rounds of pure water washing, full lifting, drying and drying on the 1-2# semicircular silicon wafer and the 2-2# semicircular silicon wafer. Then, at the temperature of 25-30 ℃, the mixture of 75 g of chromium trioxide, 2000ml of hydrofluoric acid and 2500ml of ultrapure water is etched in the solution, and after 5min of etching, the 1-2# semicircular silicon wafer and the 2-2# semicircular silicon wafer are taken out. And then sequentially washing the corroded 1-2# semicircular silicon wafer and the corroded 2-2# semicircular silicon wafer with pure water to remove the corrosion residual solution and microscopic impurities on the surface of the corroded circular silicon wafer. Finally, the corroded 1-2# semicircular silicon wafer and 2-2# semicircular silicon wafer are visually inspected under a strong light with the illuminance of 130-. As can be seen from FIGS. 4 and 5, the 1-2# semicircular silicon wafer and the 2-2# semicircular silicon wafer can macroscopically observe the ring-shaped stacking faults under the strong light. As can be seen from FIGS. 6 and 7, when the 1-2# semicircular silicon wafer and the 2-2# semicircular silicon wafer are microscopically observed under a microscope, more OISF characteristic features are also found; and after the 1-2# semicircular silicon wafer and the 2-2# semicircular silicon wafer are rotated to be observed, the silicon wafers are in annular distribution in a microscopic mode, and the layer dislocation positions 30 of the 1-2# semicircular silicon wafer and the 2-2# semicircular silicon wafer are respectively in the range of 40-50mm and in the range of 60-65 mm. The accuracy of macroscopic observation of the round silicon wafer 10 is different from that of actual test, and the difference of difficulty degree of observation of the 1-2# semicircular silicon wafer and the 2-2# semicircular silicon wafer can be seen under a strong light.
From the above analysis, it can be seen that the physical method provided by the present application for radial in vivo microdefect particle number distribution analysis results in the occurrence of significant low-density defects in the range of the dislocation position near the high peak, and the position width of the defects corresponds to the macroscopic observation and microscopic observation measured by the chemical method.
Meanwhile, compared with the traditional OISF test flow, the test method is the same in the high-temperature oxidation process of the round silicon wafer 10, but a physical method is used in the post-treatment process, so that the flow is simplified. In the traditional method, the circular silicon wafer 10 needs to be subjected to HF corrosion and film removal, pure water washing and drying, then mixed solution of chromium trioxide, hydrofluoric acid and pure water in a certain proportion is used for corrosion, the pure water washing and drying, the inspection under a strong light, the observation and confirmation under a microscope, the data arrangement and the report are carried out, and the process is complicated.
The time used by the test method of the invention and the traditional test method is shown in table 1, only single chip treatment can be carried out each time by adopting the test method of the invention, chemical corrosion is not needed, and the obtained single chip test time is 45 min/chip. By adopting the traditional test method, chemical corrosion is necessary, and each chemical corrosion can process 8 pieces at most, finally, the time required for each test reaches 270min, and the average test time to a single piece is 55 min/piece. The testing method can complete the test and the data report 45 minutes after the high-temperature oxidation of the silicon chip is finished; whereas the conventional test method requires 270 minutes before 1 data result can be reported. Moreover, the traditional test method has invisible time consumption on the logistics transfer of the round silicon wafer 10, so that the timeliness of the round silicon wafer 10 is longer. Meanwhile, in the traditional test method, not only are more resources of chemicals and pure water consumed, but also the used chemical liquid medicine belongs to a dangerous chemical operation mode, the influence of the discharge of the chromium-containing waste liquid and the waste water on water pollution is large, the waste water needs to be collected and treated specially, and the waste water can be treated only by a unit approved and certified by an environmental protection department.
TABLE 1 comparison of the technical effects of the test method of the present invention and the conventional chemical method
The test method provided by the invention is adopted to analyze the annular OISF, the positioning is accurate, the distribution characteristics of the annular OISF are consistent with the defect formation and distribution in the crystal pulling process, the specific position of the OISF in the silicon wafer can be easily judged and accurately represented, particularly, the macroscopic position judgment is more accurate, the detection steps are simplified, the detection time is shortened, the production cost is reduced, and the efficiency is improved. Meanwhile, the use of chemicals and the discharge of chromium-containing wastewater are saved, the purpose of environmental protection is achieved, and the aspects of analysis and test flow are reduced by highlight lamp observation and microscopic analysis.
The embodiments of the present invention have been described in detail, and the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.
Claims (10)
1. A method for testing the annular stacking faults of a semiconductor round silicon wafer is characterized by comprising the following steps:
selecting a plurality of groups of radially symmetrical test points on the plane of the circular silicon wafer;
analyzing the micro-defect particles at the positions of the round silicon chip corresponding to the test points, wherein the number of the micro-defect particles corresponding to each group of the test points is consistent or is a difference value,
the positions of a plurality of adjacent test points which are positioned between the positions of the test points corresponding to the group with the largest number of the micro-defect particles and correspond to the small number of the micro-defect particles are all on the annular staggered positions of the round silicon wafer;
and an annular area which is positioned between the positions of a group of test points corresponding to the largest number of the micro-defect particles and is formed by drawing circles by taking the positions of a plurality of adjacent groups of test points with the smaller number of the micro-defect particles as radii is the annular fault.
2. The method of claim 1, wherein the test points are all located in the same semicircle of the round silicon wafer, and the distance between the outermost test point and the edge of the excircle of the round silicon wafer is at least 10-15 mm.
3. The method for testing the annular stacking faults of the semiconductor round silicon wafer as claimed in claim 2, wherein the test points are arranged at equal intervals along the diameter direction of the semicircle of the round silicon wafer, and the test points are symmetrical relative to the center of the circle of the round silicon wafer.
4. The method for testing the annular stacking fault of the semiconductor round silicon wafer according to any one of claims 1 to 3, wherein the test points are all arranged on the same straight line parallel to the diameter of the round silicon wafer; the spacing distance between adjacent test points is not more than 10 mm.
5. The method as claimed in claim 4, wherein the ratio of the difference in the number of the microdefect particles corresponding to each group of the test points to the average number of the microdefect particles is greater than 0 and less than 3%.
6. The method for testing the ring-shaped stacking fault of the semiconductor round silicon wafer as claimed in any one of claims 1 to 3 and 5, wherein the positions of the test points are taken as an X axis, the number of the microdefect particles is taken as a Y axis, the number of the microdefect particles corresponding to the test points are sequentially connected to form a curve waveform distribution diagram, and the waveform distribution diagram is symmetrical relative to the axis of the circle center position.
7. The method as claimed in claim 6, wherein the two peak values of the number of the microdefect particles in the waveform distribution diagram are the same or within the range of the difference, and the corresponding positions of the test points are symmetrical with respect to the center of the circle; the positions of the test points corresponding to the valleys between the peaks of the number of the micro-defect particles are within the annular stacking faults.
8. The method for testing the ring-shaped stacking fault of the semiconductor round silicon wafer as claimed in any one of claims 1 to 3, 5 and 7, wherein the method further comprises the step of cleaving the round silicon wafer to form a semi-round silicon wafer before the test point is arranged on the plane of the round silicon wafer.
9. The method as claimed in claim 8, wherein the cleaving step comprises the step of splitting the wafer along a diameter of a V-shaped groove formed in the outer periphery of the wafer.
10. The method for testing the ring-shaped stacking fault of the semiconductor round silicon wafer as claimed in claim 9, wherein the V-shaped groove is arranged in the crystal orientation of the round silicon wafer (110).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010548224.1A CN111781204A (en) | 2020-06-16 | 2020-06-16 | Method for testing annular faults of semiconductor round silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010548224.1A CN111781204A (en) | 2020-06-16 | 2020-06-16 | Method for testing annular faults of semiconductor round silicon wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111781204A true CN111781204A (en) | 2020-10-16 |
Family
ID=72756911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010548224.1A Pending CN111781204A (en) | 2020-06-16 | 2020-06-16 | Method for testing annular faults of semiconductor round silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111781204A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190452B1 (en) * | 1998-06-11 | 2001-02-20 | Shin-Etsu Handotai Co., Ltd. | Silicon single crystal wafer and method for producing it |
| US20020046694A1 (en) * | 2000-09-04 | 2002-04-25 | Hong-Woo Lee | Single crystalline silicon wafer, ingot, and producing method thereof |
| US20070269361A1 (en) * | 2006-05-19 | 2007-11-22 | Memc Electronic Materials, Inc. | Silicon material with controlled agglomerated point defects and oxygen clusters induced by the lateral surface |
| US20140327112A1 (en) * | 2011-10-14 | 2014-11-06 | Sunedison, Inc. | Method to delineate crystal related defects |
| US20180312994A1 (en) * | 2015-11-17 | 2018-11-01 | Shin-Etsu Handotai Co., Ltd. | Method for determining defect region |
| CN109968136A (en) * | 2019-04-25 | 2019-07-05 | 内蒙古中环协鑫光伏材料有限公司 | A kind of polygon silicon single crystal rod and its processing method |
-
2020
- 2020-06-16 CN CN202010548224.1A patent/CN111781204A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6190452B1 (en) * | 1998-06-11 | 2001-02-20 | Shin-Etsu Handotai Co., Ltd. | Silicon single crystal wafer and method for producing it |
| US20020046694A1 (en) * | 2000-09-04 | 2002-04-25 | Hong-Woo Lee | Single crystalline silicon wafer, ingot, and producing method thereof |
| US20070269361A1 (en) * | 2006-05-19 | 2007-11-22 | Memc Electronic Materials, Inc. | Silicon material with controlled agglomerated point defects and oxygen clusters induced by the lateral surface |
| US20140327112A1 (en) * | 2011-10-14 | 2014-11-06 | Sunedison, Inc. | Method to delineate crystal related defects |
| US20180312994A1 (en) * | 2015-11-17 | 2018-11-01 | Shin-Etsu Handotai Co., Ltd. | Method for determining defect region |
| CN109968136A (en) * | 2019-04-25 | 2019-07-05 | 内蒙古中环协鑫光伏材料有限公司 | A kind of polygon silicon single crystal rod and its processing method |
Non-Patent Citations (1)
| Title |
|---|
| K. NAKAMURA等: "Simulation of oxygen precipitation in CZ-Si crystal during the pulling process", 《MATERIALS SCIENCEAND ENGINEERING》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102931118B (en) | The analytical method of epitaxy defect analytical structure and manufacture method and epitaxy defect | |
| JP6102277B2 (en) | Method for evaluating metal contamination of semiconductor wafer and method for manufacturing semiconductor wafer | |
| CN101187065B (en) | Method of identifying crystal defect region in monocrystalline silicon using metal contamination and heat treatment | |
| CN106783687A (en) | A kind of method for improving ion implanting monitoring | |
| CN101957324B (en) | Method for detecting defects of SiGe epitaxy | |
| CN105405811B (en) | A kind of Sapphire Substrate manufacture craft | |
| CN111781204A (en) | Method for testing annular faults of semiconductor round silicon wafer | |
| US6753955B2 (en) | Inspection device for crystal defect of silicon wafer and method for detecting crystal defect of the same | |
| CN106057981A (en) | Preparation method of black silicon | |
| CN105742409B (en) | A kind of black Silicon Surface Cleaning method and black silion cell preparation method | |
| CN107316822A (en) | Silicon crystal defect inspection method | |
| CN109273377A (en) | Preprocess method before the detection at monocrystalline silicon concentric circles and black angle | |
| CN102403248A (en) | Nondestructive testing method of fault and dislocation defects of silicon polished wafers or epitaxial wafers | |
| CN112585734A (en) | Method for evaluating defective area of wafer | |
| JPH0862122A (en) | Method for evaluating oxygen precipitation defect density of silicon water | |
| CN111781243A (en) | Silicon wafer micro-defect testing method | |
| TWI476942B (en) | Texturing method for mono-like silicon chip | |
| CN111829941A (en) | Corrosive liquid for detecting gallium oxide single crystal processing surface damage layer and detection method | |
| KR100384680B1 (en) | A Method for detecting micro defects | |
| CN112447544A (en) | Silicon wafer quality detection method and classification method | |
| JP2022175082A (en) | Crystal defect evaluation method for semiconductor single crystal substrate | |
| CN109166812A (en) | The monitoring method of control wafer and its manufacturing method and chemical mechanical grinding defect | |
| JP3994523B2 (en) | Inspection method of mirror chamfered part of silicon wafer | |
| CN113782465B (en) | Method for detecting metal on surface of wafer | |
| KR100783440B1 (en) | Method of testing defect of low interstitial oxygen concentration silicon wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |