CN111769130A - CMOS pixel sensor - Google Patents
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Abstract
The invention discloses a CMOS (complementary metal oxide semiconductor) pixel sensor which comprises a P-type substrate, a P-type high-resistance epitaxial layer, an N well, a P well, a deep N well and a deep P isolating layer, wherein the P-type high-resistance epitaxial layer is arranged on the P well; the deep N well and the P-type high-resistance epitaxial layer form a P-N diode; the N trap on the deep N trap and the N-type active region form a passage and are connected with other reading circuits through metal wires; the deep P isolation layer is used for isolating devices in the deep N trap, the N trap and the P type active area in the deep P isolation layer are used for manufacturing PMOS transistors, and the P trap and the N type active area in the deep P isolation layer are used for manufacturing NMOS tubes.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a CMOS (complementary metal oxide semiconductor) pixel sensor.
Background
With the development of semiconductor technology industry and lithography technology, CMOS pixel sensors are more and more widely used in X-ray imaging and particle detection, and have the characteristics of high spatial resolution, fast readout speed, high integration level, low power consumption, low cost, and the like, and are gradually becoming important detection technologies.
However, the inventor finds that the pixel in the CMOS pixel sensor collects charges by using a small-area diode, the proportion of the diode area in the pixel unit is small, the charges are compounded in the collection process, the charge collection time is long, and the collection efficiency is low.
Disclosure of Invention
In view of the shortcomings of the prior art, it is an object of the present invention to provide a CMOS pixel sensor and a pixel unit, which can effectively shorten the charge collection time and improve the collection efficiency and sensitivity.
In order to achieve the purpose, the invention is realized by the following technical scheme:
in a first aspect, the invention provides a CMOS pixel sensor, which includes a P-type substrate, a P-type high-resistance epitaxial layer, an N-well, a P-well, a deep N-well, and a deep P-isolation layer;
the deep N well and the P-type high-resistance epitaxial layer form a P-N diode;
the N trap on the deep N trap and the N-type active region (N +) form a path which is connected with other reading circuits through metal wires;
the deep P isolation layer is used for isolating devices in the deep N well, so that charge competition between a PMOS transistor and a sensitive diode is avoided, the PMOS transistor and the NMOS transistor can be simultaneously manufactured in the deep P isolation layer, a complex CMOS circuit can be realized, the complex circuit can be realized in a pixel, and the pixel signal is amplified and subjected to noise reduction;
the N well and the P type active region (P +) are used for manufacturing a PMOS transistor, and the P well and the N type active region (N +) are used for manufacturing an NMOS transistor.
As a further technical scheme, the resistivity of the P-type high-resistance epitaxial layer is larger than 1K omega cm.
Furthermore, the anode region of the P-N diode is connected with a reverse bias voltage for accelerating charge collection.
As a further technical solution, the CMOS pixel sensor further includes a plurality of pixel units, the plurality of pixel units form a pixel array, and a deep N well is fully laid in each pixel unit, so that the whole pixel unit functions as a diode.
As a further technical scheme, each pixel unit comprises a calibration test circuit, a charge sensitive amplifier, a shaper, a comparator and a case driving circuit which are connected in sequence.
Calibration test circuit routing CinjThe capacitor and the external trigger signal are used for simulating external charge injection and calibrating the performance of the internal circuit of the pixel.
The gain of the charge sensitive amplifier is about 1/Cf, and the MOM capacitor is customized to be used as a feedback capacitor.
The shaper adopts a CR-RC structure.
The comparator adopts a two-stage structure, the first stage completes the differential amplification function, and the second stage completes the positive feedback comparison function.
The case driving circuit completes the priority judging function, and if a certain pixel is hit by particles, the case driving circuit transmits a judging signal to the column end to complete the priority triggering.
As a further technical scheme, the CMOS pixel sensor is also provided with a pixel configuration circuit, a sequential logic, a bias circuit, a clock circuit and a control interface; the pixel configuration circuit, the sequential logic, the bias circuit and the clock circuit are all connected with the pixel array.
The control interface is mainly used for adjusting the bias parameters and the enabling signals so that the chip works in the optimal state. The pixel configuration circuit is used for calibrating the performance of the pixel internal circuit. The sequential logic is used for the pixel internal logic circuit. The bias circuit mainly provides a static operating point to the pixel cell circuit. The clock circuit mainly provides a high-speed clock for the data processing module.
The beneficial effects of the invention are as follows:
the CMOS pixel sensor provided by the invention adopts the high-resistance epitaxial layer, the width of a depletion region of the diode can be increased, the charge collection time is shortened, the charge collection efficiency is improved, the deep N well is adopted as a cathode end of the diode, the P-type high-resistance epitaxial layer is adopted as an anode end of the diode, and the deep N well is fully distributed in the whole pixel unit, namely the area of the diode is equal to that of the pixel unit, the collection area of the diode is greatly increased, the charge recombination rate is reduced, the charge collection quantity is increased, namely the charge collection efficiency is improved. The influence brought by diode capacitance is eliminated by adopting a charge sensitive preamplifier in the pixel, and meanwhile, the MOM capacitance is customized to be used as a feedback capacitance, so that the gain of the amplifier is effectively improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
FIG. 1 is a schematic diagram of the CMOS pixel sensor operation principle;
FIG. 2 is a schematic diagram of the overall structure of a CMOS pixel sensor;
FIG. 3 is a schematic diagram of an internal circuit of a pixel cell;
FIG. 4 is a schematic diagram of a MOM capacitor implementation;
fig. 5 is an overall configuration diagram of the pixel sensor chip.
Detailed Description
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an", and/or "the" are intended to include the plural forms as well, unless the invention expressly state otherwise, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof;
interpretation of terms:
CMOS, Complementary Metal Oxide Semiconductor
CMOS pixel sensor: based on the CMOS process, a pixel unit and a particle detection chip of a functional circuit are integrated on the same wafer substrate.
As described in the background, the present invention provides a CMOS pixel sensor to solve the above problems.
In an exemplary embodiment of the present invention, a CMOS pixel sensor is capable of effectively shortening a charge collection time and improving a charge collection efficiency. On the one hand, the deep N well and the P-type high-resistance epitaxial layer are adopted to form the sensitive diode, the width of a depletion layer is increased, charge collection can be accelerated, on the other hand, the deep N well is adopted to be fully distributed in the whole pixel unit, the front-end circuit is realized in the deep N well, the charge recombination rate is effectively reduced, and the collection efficiency is improved.
The operating principle of the CMOS technology is shown in figure 1, the CMOS technology is provided with a P-type high-resistance epitaxy layer, an N well, a P well, a deep N well and a deep P isolating layer, and a pixel unit and a reading circuit are manufactured on the low-doped P-type epitaxial layer. The deep N well and the P-type epitaxial layer are used for generating a P-N sensitive diode, and the N well on the deep N well and the N-type active region (N +) form a passage and are connected with other reading circuits through metal wires.
The deep P isolation layer is used for isolating devices in a deep N well, so that charge competition between a PMOS transistor and a sensitive diode is avoided, the PMOS transistor and an NMOS transistor can be simultaneously manufactured in the deep P isolation layer, a complex CMOS circuit can be realized, the complex circuit can be realized in a pixel, and a pixel signal is amplified and subjected to noise reduction, wherein the N well and a P type active region (P +) in the deep P isolation layer are used for manufacturing the PMOS transistor (see the upper right corner part in figure 1), the P well and the N type active region (N +) in the deep P isolation layer are used for manufacturing the NMOS transistor, and two NMOS transistors are manufactured in figure 1.
The deep N well and the P-type high-resistance epitaxial layer form a P-N diode serving as a sensitive area and used for collecting non-equilibrium electrons.
When the particles pass through the sensor chip, a certain number of electron-hole pairs are generated in a depletion region formed by the deep N well and the P-type high-resistance epitaxial layer, and about 80 pairs of non-equilibrium carriers are generated per micron.
The diode depletion region width is related to the bias voltage and the substrate resistivity by the following formula:
wherein, represents the silicon dielectric constant, μ represents the mobility, ρ represents the substrate resistivity, VbiasRepresenting the P-N bias voltage. As can be seen from equation (1.1), increasing the bias voltage and resistivity can effectively increase the width of the depletion region, and besides increasing the epitaxial layer resistivity to be greater than 1K Ω · cm, the width of the depletion region can also be increased by increasing the bias voltage, see the left part of fig. 1, and applying a reverse voltage (-Vb) to the substrate, these electrons are collected by the N + region under the electric field of the depletion region. The collected charges are amplified and shaped by a pixel internal circuit to improve the signal-to-noise ratio, then processed by a discriminator, converted from analog signals into digital signals, and finally transmitted to a subsequent data processing circuit through metal wiring.
In order to further improve the charge collection efficiency, a deep N well is fully paved in the pixel unit, one pixel unit is a sensitive diode, the deep N well and the P-type high-resistance epitaxial layer form a depletion region, the depletion region basically occupies the whole pixel unit, when charged particles pass through the detection chip, electrons in the depletion region are rapidly collected, the electron recombination rate is remarkably reduced due to the small area outside the depletion region, most of charges are collected by the depletion region, and the collection efficiency is remarkably improved.
The structure of the pixel unit is shown in fig. 2, the deep N-well is fully paved on the whole pixel unit, one pixel is a sensitive diode, NMOS and PMOS tubes are manufactured in the pixel unit, namely the deep N-well, a CMOS circuit is realized, and the outputs of the pixel unit are connected together through a column transmission line and are transmitted to a column end processing circuit.
Fig. 3 is a pixel cell internal circuit including calibration test, charge sensitive amplifier, shaper, comparator, and case drive circuit. Calibration test composed ofinjThe capacitor and the external trigger signal are used for simulating external charge injection and calibrating the performance of the internal circuit of the pixel. The diode capacitance is large because the diode sensitive area occupies most of the whole pixel area. From V-Q/C, the voltage signal is small, and in order to eliminate the influence of large capacitance, the method adoptsThe charge sensitive preamplifier amplifies the signal, and the working principle is that the input charge is integrated, and the amplitude of the output signal is in direct proportion to the input charge quantity. In order to reduce noise, noise reduction processing is carried out before signal digitization, and a shaper is added. The pixel information is converted to a digital signal by a comparator and then hit information is sent to the column side by case drive logic. Wherein the reference voltage (Vref) of the comparator may be set by a bias circuit.
The gain of the charge sensitive amplifier is about 1/Cf, so that the feedback capacitance value should be reduced as much as possible to obtain higher gain, the minimum capacitance value of a standard capacitor device provided by a CMOS (complementary Metal-Oxide-Metal) process is limited by the process, and in order to improve the gain to the maximum extent, a customized MOM (Metal-Oxide-Metal) capacitor is adopted as a feedback capacitor, namely, the feedback capacitor is generated by a coupling capacitor between Metal Oxide layers. With MOM capacitors, the capacitance can be less than 1fF, while with capacitive devices the capacitance is about 15 fF. Therefore, the MOM capacitor can effectively reduce the feedback capacitor and improve the gain of the charge sensitive amplifier.
The feedback resistor is used for providing a static working point and discharging signals, the resistance value is large (100M omega-1G omega), similarly, the maximum resistance value of a standard resistor device provided by a CMOS process is limited by the process, the area is large, and the resistance value larger than 100M omega can be realized by adopting a weak current circuit or a weak starting switch. The shaper adopts a CR-RC structure, the comparator adopts a two-stage structure, the first stage finishes a differential amplification function, the second stage finishes a positive feedback comparison function, the case driving circuit finishes a priority judgment function, and if a certain pixel is hit by a particle, the case driving circuit transmits a judgment signal to a column end to finish priority triggering.
Fig. 4 is a MOM capacitor implementation. And the same layer of metal wire inserting finger-shaped structure is adopted, wherein the space between the metal wires is the minimum space allowed by the process, and the length of the metal wires is a multiple of the unit length.
Fig. 5 shows an overall structure diagram of a pixel sensor chip, wherein a plurality of pixel units form a pixel array, and the pixel array is read out in a global shutter (global shutter) manner, so that information is read out only when a pixel is hit, and the reading speed is high. In addition to the pixel array, the pixel sensor chip integrates peripheral circuits such as a pixel configuration circuit, sequential logic, a bias circuit, a clock circuit, priority coding logic, a control interface and the like.
The pixel configuration circuit, the sequential logic, the bias circuit and the clock circuit are all connected with the pixel array; the pixel array, the control interface and the pixel configuration circuit are also connected with a priority coding logic and data processing module, the priority coding logic and data processing module is connected with a reading unit, and the reading unit is connected with a serial output unit.
The pixel configuration circuit is mainly used for calibrating the performance of a pixel internal circuit, the sequential logic is used for a pixel internal logic circuit, the bias circuit is realized by a multi-bit to Analog Converter (DAC) and used for providing reference voltage and current, the clock circuit is realized by a Phase-locked loop (PLL), a high-speed clock is mainly provided for a pixel array and serial output, the priority coding logic and the data processing module are used for processing case information, the case information comprises hit position information, time information and the like, the output data rate of the case information is directly related to the number of cases, and the number of cases can calculate the maximum cumulative value according to Poisson distribution, so that the Digital logic is optimized. The control interface is mainly used for adjusting the bias parameters and the enabling signals so that the chip works in the optimal state. The working principle is that when charged particles pass through a pixel array, electric signals are generated in the pixels, after the electric signals are amplified and shaped, analog signals are converted into digital signals through a comparator, hit information is sent to a column end through an in-pixel case driving circuit, after the hit information of the whole array is processed through priority coding logic and data processing, hit address information and time information are sequentially read out through an output serializer. Due to the reverse bias of the sensitive diodes, the pixel array peripheral circuits must be isolated with deep N-wells and the IO (input and output) pins are custom designed.
The CMOS pixel sensor provided by the invention has the advantages of high integration level, high resolution, low power consumption, low material quality and low cost, adopts the P-type high-resistance epitaxial layer and the reverse bias voltage, increases the width of a depletion region, shortens the charge collection time, improves the charge collection efficiency, adopts the sensitive diode with the size of the pixel unit, and adopts the deep N well paved in the pixel unit as the cathode of the diode, so that the charge recombination rate can be reduced, the charge collection efficiency is effectively improved, and the sensitivity of the pixel sensor is improved. Meanwhile, the process has four wells, so that charge competition between a PMOS transistor and a sensitive diode is avoided, a complex CMOS circuit can be realized in a pixel, and information amplification, noise reduction and digitization are completed.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
- The CMOS pixel sensor is characterized by comprising a P-type substrate, a P-type high-resistance epitaxial layer, an N well, a P well, a deep N well and a deep P isolating layer;the deep N well and the P-type high-resistance epitaxial layer form a P-N diode;the N trap on the deep N trap and the N-type active region form a passage and are connected with other reading circuits through metal wires;the deep P isolation layer is used for isolating devices in the deep N trap, the N trap and the P type active area in the deep P isolation layer are used for manufacturing PMOS transistors, and the P trap and the N type active area in the deep P isolation layer are used for manufacturing NMOS tubes.
- 2. The CMOS pixel sensor of claim 1, wherein the P-type high resistance epitaxial layer has a resistivity greater than 1K Ω -cm.
- 3. The CMOS pixel sensor of claim 1, wherein the P-N diode is connected in the anode region to a reverse bias voltage for faster charge collection.
- 4. The CMOS pixel sensor of claim 1, further comprising a plurality of pixel cells forming a pixel array, each pixel cell having a deep N-well tiled therein such that the entire pixel cell acts as a diode.
- 5. The CMOS pixel sensor of claim 1, wherein each pixel cell includes a calibration test circuit, a charge sensitive amplifier, a shaper, a comparator, and an instance drive circuit connected in series.
- 6. The CMOS pixel sensor of claim 5, wherein said calibration test circuit is comprised of CinjThe capacitor and the external trigger signal are used for simulating external charge injection and calibrating the performance of the internal circuit of the pixel.
- 7. The CMOS pixel sensor of claim 5, wherein the gain of the charge sensitive amplifier is approximately 1/Cf, and the MOM capacitance is customized as a feedback capacitance.
- 8. The CMOS pixel sensor of claim 5, wherein the shaper is of a CR-RC structure; the comparator adopts a two-stage structure, the first stage completes the differential amplification function, and the second stage completes the positive feedback comparison function.
- 9. The CMOS pixel sensor of claim 5, wherein said case driver circuit performs a priority determination function, and if a pixel is hit by a particle, the case driver circuit transmits a determination signal to the column terminal to perform a priority trigger.
- 10. The CMOS pixel sensor of claim 1, wherein the CMOS pixel sensor is further configured with pixel configuration circuitry, timing logic, bias circuitry, clock circuitry, and a control interface; the pixel configuration circuit, the sequential logic, the bias circuit and the clock circuit are all connected with the pixel array; the control interface is mainly used for adjusting the bias parameters and the enabling signals to enable the chip to work in the optimal state; the pixel configuration circuit is used for calibrating the performance of the pixel internal circuit; the sequential logic is used for the pixel internal logic circuit. The bias circuit mainly provides a static working point for the pixel unit circuit; the clock circuit mainly provides a high-speed clock for the data processing module.
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