CN111769118A - Method for improving electrical property of three-dimensional memory and three-dimensional memory - Google Patents
Method for improving electrical property of three-dimensional memory and three-dimensional memory Download PDFInfo
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention relates to a method for improving the electrical property of a three-dimensional memory, which comprises the following steps: the semiconductor device includes a substrate, a stack structure on the substrate, and a vertical channel structure through the stack structure. The method comprises the following steps: depositing a silicon nitride layer on the stacked structure; and heat-treating the three-dimensional memory in a hydrogen atmosphere; wherein, hydrogen ions in the silicon nitride layer are diffused into the vertical channel structure through heat treatment.
Description
Technical Field
The invention relates to a method for improving the electrical property of a three-dimensional memory, which can repair lattice defects in a vertical channel structure and effectively improve the electrical response sensitivity of a device.
Background
Semiconductor integrated circuits have since their birth, undergone a phase of development from small-scale, medium-scale to large-scale and very large-scale integration, and are increasingly becoming one of the most active technical fields in modern scientific technology.
A memory is a widely used semiconductor device. To overcome the limitation of the storage capacity of the conventional two-dimensional memory, modern technologies often adopt a stacked memory chip manner to achieve higher integration. For example, chips or structures with different functions can be processed by micro-machining technology such as stacking or hole interconnection to form a three-dimensional (3D) device with three-dimensional integration and signal communication in the vertical direction. The three-dimensional memory is formed by three-dimensionally arranging memory cells on a substrate by using the technology, so that the aim of improving the performance and the storage density of the memory is fulfilled.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for improving the electrical property of a three-dimensional memory, which can repair lattice defects in a vertical channel structure and effectively improve the electrical response sensitivity of a device.
The present invention adopts a technical solution to solve the above technical problems by providing a method for improving electrical characteristics of a three-dimensional memory, wherein the three-dimensional memory comprises: a substrate, a stack structure on the substrate, and a vertical channel structure through the stack structure, the method comprising the steps of: depositing a silicon nitride layer on the stacked structure; and heat-treating the three-dimensional memory under a hydrogen atmosphere; wherein hydrogen ions in the silicon nitride layer are diffused into the vertical channel structure by the heat treatment.
In an embodiment of the invention, the three-dimensional memory further includes a metal interconnection structure and an inter-metal dielectric layer between the silicon nitride layer and the stacked structure, and hydrogen ions in the silicon nitride layer diffuse into the vertical channel structure through the metal interconnection structure.
In an embodiment of the invention, the hydrogen ion content in the silicon nitride layer is at least 1.98 x 1022/cm 2.
In an embodiment of the invention, the thickness of the silicon nitride layer is:
in one embodiment of the present invention, the stack structure is sunkThe method for depositing the silicon nitride layer comprises
The deposition rate of (a) deposits the silicon nitride layer.
In an embodiment of the invention, the reaction gas for depositing the silicon nitride layer includes monosilane and ammonia, and the ratio of the monosilane to the ammonia is at least 1.5: 1.
In an embodiment of the present invention, the rf power for depositing the silicon nitride layer is: 600-.
In an embodiment of the present invention, the chamber pressure for depositing the silicon nitride layer is: 530 ℃ and 670 Pa.
In an embodiment of the invention, after the performing the heat treatment on the three-dimensional memory under the hydrogen atmosphere, the method further includes: removing the silicon nitride layer; forming a metal interconnection structure and an intermetallic dielectric layer on the stacked structure; and depositing a passivation layer on the intermetallic dielectric layer.
In an embodiment of the invention, after the performing the heat treatment on the three-dimensional memory under the hydrogen atmosphere, the method further includes: removing the silicon nitride layer; and depositing a passivation layer on the intermetallic dielectric layer.
In an embodiment of the present invention, the passivation layer is made of silicon nitride, and has a thickness of:
in an embodiment of the invention, the bottom of the vertical channel structure has an epitaxial layer, and hydrogen ions in the silicon nitride layer are diffused into the epitaxial layer through the thermal treatment.
In an embodiment of the invention, a sidewall of the vertical channel structure has a semiconductor layer, and hydrogen ions in the silicon nitride layer are diffused into the semiconductor layer by the thermal treatment.
Another aspect of the present invention provides a three-dimensional memory fabricated using the above method, including: a substrate; a stack structure on the substrate; and a vertical channel structure passing through the stacked structure.
Another aspect of the present invention provides a three-dimensional memory including: a substrate; a stack structure on the substrate; a vertical channel structure through the stacked structure; the metal interconnection structure and the intermetallic dielectric layer are positioned on the stacking structure; and a passivation layer located on the intermetallic dielectric layer; wherein, the passivation layer is made of silicon nitride and has the following thickness:
due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
according to the method for improving the electrical property of the three-dimensional memory, the silicon nitride layer is deposited on the stacked structure, and the three-dimensional memory is subjected to heat treatment in the hydrogen atmosphere, so that hydrogen ions in the silicon nitride layer are diffused into the vertical channel structure through the heat treatment, the lattice defect in the vertical channel structure is repaired, and the electrical response sensitivity of the device is effectively improved.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a flow chart of a method for improving electrical performance of a three-dimensional memory according to an embodiment of the invention;
fig. 2 to 7 are schematic process steps of a method for improving electrical performance of a three-dimensional memory according to an embodiment of the invention;
FIG. 8 is a diagram illustrating hydrogen ion content of a method for improving electrical performance of a three-dimensional memory according to an embodiment of the present invention;
FIG. 9 is a flowchart of another method for improving electrical performance of a three-dimensional memory according to an embodiment of the present invention;
FIGS. 10 to 11 are schematic process steps of another method for improving electrical characteristics of a three-dimensional memory according to an embodiment of the invention;
FIG. 12 is a flowchart of another method for improving electrical performance of a three-dimensional memory according to an embodiment of the present invention;
fig. 13 to 14 are schematic process steps of another method for improving electrical characteristics of a three-dimensional memory according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
During the fabrication of three-dimensional memory devices, it is often necessary to deposit a passivation layer on the surface of the device to protect it from moisture and ions. One solution is to deposit a passivation film of nitride directly on the surface of the three-dimensional memory (not shown). However, in this case, the hydrogen ion (H +) content in the passivation film of nitride is low (e.g., 1.48 x 10)22/cm2) The lattice defect in the vertical channel structure of the three-dimensional memory can not be repaired by the subsequent thermal annealing process, so that the electrical performance of the device is improvedThe sensitivity should be low. Also, the nitride deposition rate in this scheme is low (e.g.
) The thickness of the passivation film is large, and the cost is high.
In view of the above problems, the following embodiments of the present invention provide a method for improving electrical properties of a three-dimensional memory, which can repair lattice defects in a vertical channel structure and effectively improve electrical response sensitivity of a device.
Fig. 1 is a flowchart illustrating a method for improving electrical performance of a three-dimensional memory according to an embodiment of the invention. Fig. 2 to 7 are schematic process steps of a method for improving electrical characteristics of a three-dimensional memory according to an embodiment of the invention. The method is described below with reference to fig. 1 to 7.
It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
Referring to fig. 2, the three-dimensional memory 100 includes: a substrate 101, a stacked structure 102 located on the substrate 101, and a vertical channel structure 103 passing through the stacked structure 102.
The material of the substrate 101 may be, for example, silicon (Si). In other embodiments of the present invention, the substrate 101 may also be made of other suitable materials including, but not limited to, polysilicon, silicon germanium, and silicon-on-insulator (SOI) and the like.
The material of the stacked structure 102 is, for example, silicon oxide, silicon nitride, or a combination thereof. For example, the stacked structure 102 may include a first material layer and a second material layer (not shown) stacked on each other. The material of the first material layer is, for example, silicon nitride, and the material of the second material layer is, for example, silicon oxide.
For example, silicon oxide and/or silicon nitride may be sequentially deposited on the substrate 101 by using Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) or other suitable deposition methods, thereby forming a first material layer and a second material layer which are alternately stacked, i.e., a stacked structure 102 having a SiOx-SiOxNx-SiOx stack (ONO stack) structure.
In some examples, the stacked structure 102 further includes a stack intermediate layer (not shown). The material of the intermediate layer of the stack may be a material having a very high etch selectivity to silicon nitride, such as silicon oxide, silicon carbide, silicon oxycarbide, aluminum oxide, and the like. In some embodiments, the first material layer may also serve as a dummy gate layer, and the metal (e.g., tungsten) or polysilicon is removed and filled in a subsequent process to form a gate layer. The second material layer may be used as a dielectric layer between the gate layers, but the invention is not limited thereto.
In one example shown in fig. 2, a plurality of vertical channel structures 103 pass through the stacked structure 102 and communicate with the substrate 101.
For example, a mask may be placed on the surface of the stacked structure 102, and then the stacked structure 102 may be etched using a Photolithography process (Photolithography) to form a plurality of vertical channel structures 103 (channel holes). A plurality of vertical channel structures 103 are respectively in communication with the substrate 101.
In some examples, a memory layer and a channel layer (not shown) may be sequentially formed on an inner wall of the vertical channel structure 103.
The structure of the memory layer may be varied. In some embodiments, the memory layer includes, but is not limited to, a blocking oxide layer, a charge trapping layer, and a tunneling oxide layer sequentially formed from inside to outside. The tunnel oxide layer may be made of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof. The material of the charge trapping layer includes, but is not limited to, silicon nitride, silicon oxynitride, silicon, or combinations thereof. The barrier layer material is silicon oxide, silicon nitride, high dielectric constant insulating material or the combination of the above materials.
The material of the channel layer may be selected from amorphous, polycrystalline, single crystal silicon, and the like. The process of forming the channel layer may use a thin film deposition process. The thin film deposition process includes, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), or combinations thereof, among other suitable processes.
It is understood that the three-dimensional memory 100 shown in fig. 2 may also include other layers or structures, which will not be described further herein.
Fig. 5 is a schematic structural diagram of another three-dimensional memory according to an embodiment of the invention. Referring to fig. 5, in an embodiment of the invention, a three-dimensional memory 200 includes a substrate 201, a stack structure 202 on the substrate 201, and a vertical channel structure 203 passing through the stack structure 202. The three-dimensional memory 200 shown in fig. 5 is different from the three-dimensional memory 100 shown in fig. 2 in that it further includes a metal interconnect structure 204 and an inter-metal dielectric layer 205 over the stacked structure 202.
In one example shown in fig. 5, the metal interconnection structure 204 includes metal interconnection layers distributed in a lateral direction (i.e., in a horizontal direction) and metal wires distributed in a longitudinal direction (i.e., in a vertical direction). The intermetal dielectric layer 205 is disposed around the metal interconnect structure 204.
Illustratively, the material of the metal interconnect structure 204 includes, but is not limited to, copper (Cu), TiN (Sn), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and the like, or any combination thereof. The metal interconnect structure 204 may be formed by growing an interconnect seed layer (not shown).
The material of the intermetal dielectric layer 205 may be silicon oxide, silicon nitride, or a combination thereof. The intermetal dielectric layer 205 may be formed by one or more thin film deposition processes, such as Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.
Referring to fig. 1, the method for improving the electrical property of the three-dimensional memory according to the present invention includes the following steps:
at step 110, a silicon nitride layer is deposited over the stacked structure.
Referring to fig. 2 and 3, a silicon nitride layer 104 is deposited on the stacked structure 102 of the three-dimensional memory 100 to form a three-dimensional memory 110.
Referring to fig. 5 and 6, a silicon nitride layer 206 is deposited on the stack structure 202 of the three-dimensional memory 200 to form a three-dimensional memory 210. It should be noted that, since the stacked structure 202 of the three-dimensional memory 200 shown in fig. 5 further has the metal interconnection structure 204 and the inter-metal dielectric layer 205 thereon, the silicon nitride layer 206 formed by the above deposition process is located on the upper surface of the inter-metal dielectric layer 205, but the invention is not limited thereto.
In an embodiment of the present invention, the hydrogen ion content in the silicon nitride layer (e.g., the silicon nitride layer 104 or the silicon nitride layer 206) is at least 1.98 x 1022/cm2. It will be appreciated that a higher hydrogen ion content will facilitate better diffusion of hydrogen ions into underlying layers and/or structures (e.g., vertical channel structures) during subsequent processing (e.g., thermal processing).
In an embodiment of the invention, the thickness of the silicon nitride layer (e.g., the silicon nitride layer 104 or the silicon nitride layer 206) may be:
it will be appreciated that greater thicknesses may increase the hydrogen ion content in the silicon nitride layer.
In an embodiment of the present invention, a method of depositing a silicon nitride layer (e.g., silicon nitride layer 104 or silicon nitride layer 206) on a stacked structure (e.g., stacked structure 102 or stacked structure 202) includes depositing a silicon nitride layer on a substrate
The deposition rate of (a) deposits the silicon nitride layer.
Illustratively, the reaction gas for depositing the silicon nitride layer (e.g., silicon nitride layer 104 or silicon nitride layer 206) may comprise monosilane (SiH)4) And ammonia (NH)3). Preferably, the ratio of monosilane to ammonia is at least 1.5: 1. In some examples, the range of rf power to deposit a silicon nitride layer (e.g., silicon nitride layer 104 or silicon nitride layer 206) may be: 600-. In some examples, the chamber pressure for the deposition process may range from 530 Pa to 670Pa (i.e., 4-5 Torr).
It is understood that by adjusting the ratio of the reactive gases during the deposition process (e.g., increasing the flow rates of the silane and the ammonia gas), the rf power during the deposition, and the chamber pressure, the deposition rate of the silicon nitride layer can be increased, so that the silicon nitride layer (e.g., the silicon nitride layer 104 or the silicon nitride layer 206) formed on the stacked structure (e.g., the stacked structure 102 or the stacked structure 202) has a higher hydrogen ion content.
And step 120, performing heat treatment on the three-dimensional memory in a hydrogen atmosphere.
Referring to FIGS. 3 and 4, in the presence of hydrogen (H)2) The three-dimensional memory 110 is thermally treated under an atmosphere to form a three-dimensional memory 120.
Referring to FIGS. 6 and 7, in the case of hydrogen (H)2) The three-dimensional memory 210 is thermally treated under an atmosphere to form a three-dimensional memory 220.
In some examples, the heat treatment process may be a thermal anneal. After the thermal treatment process of step 120, hydrogen ions in the silicon nitride layer (e.g., silicon nitride layer 104 or silicon nitride layer 206) diffuse into the vertical channel structure (e.g., vertical channel structure 103 or vertical channel structure 203).
It should be noted that in the examples shown in fig. 3 and 4, hydrogen ions in the silicon nitride layer 104 may diffuse directly into the vertical channel structure 103. In the examples shown in fig. 6 and 7, hydrogen ions in the silicon nitride layer 206 diffuse through the metal interconnect structure 204 into the vertical channel structure 203.
The thermal treatment of the three-dimensional memory (e.g., the three-dimensional memory 110 or the three-dimensional memory 210) in the hydrogen atmosphere can improve the hydrogen ion activity in the silicon nitride layer (e.g., the silicon nitride layer 104 or the silicon nitride layer 206) of the three-dimensional memory (e.g., the three-dimensional memory 110 or the three-dimensional memory 210) to facilitate better diffusion into the underlying vertical channel structure (e.g., the vertical channel structure 103 or the vertical channel structure 203).
In some examples of the invention, the bottom of a vertical channel structure (e.g., vertical channel structure 103 or vertical channel structure 203) has an epitaxial layer, such as the lower dark portion of vertical channel structure 103 shown in fig. 4 and the lower dark portion of vertical channel structure 203 shown in fig. 7. The hydrogen ions in the silicon nitride layer (e.g., silicon nitride layer 104 or silicon nitride layer 206) are diffused into the epitaxial layer after the above-mentioned heat treatment.
In other examples of the present invention, the sidewalls of the vertical channel structures (e.g., vertical channel structure 103 or vertical channel structure 203) have a semiconductor layer (not shown to keep the figures concise). The hydrogen ions in the silicon nitride layer (e.g., silicon nitride layer 104 or silicon nitride layer 206) are diffused into the semiconductor layer after the above-mentioned heat treatment.
The semiconductor layer may be a memory layer and/or a channel layer. It will be appreciated that the structure of the memory layer is varied. In some embodiments, the memory layer includes, but is not limited to, a blocking oxide layer, a charge trapping layer, and a tunneling oxide layer (not shown) formed sequentially from inside to outside. Illustratively, the tunneling oxide layer may be an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof. The material of the charge trapping layer includes, but is not limited to, silicon nitride, silicon oxynitride, silicon, or combinations thereof. The barrier layer material may be silicon oxide, silicon nitride, a high dielectric constant insulating material, or a combination thereof.
The material of the channel layer may be selected from amorphous, polycrystalline, single crystal silicon, and the like. The process of forming the channel layer includes various types of thin film deposition processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), or combinations thereof, among other suitable processes.
It should be noted that the present invention is not limited to a specific internal structure of the vertical channel structure (e.g., the vertical channel structure 103 or the vertical channel structure 203).
FIG. 8 is a diagram illustrating hydrogen ion content of a method for improving electrical properties of a three-dimensional memory according to an embodiment of the invention. Referring to fig. 8, the method for improving the electrical property of the three-dimensional memory according to the present invention controls the deposition rate of the silicon nitride layer and the thickness of the deposited silicon nitride layer, so that the silicon nitride layer has a higher hydrogen ion content (e.g. 1.98 x 10 as shown in high H SIN in the figure)22/cm2)。
Then, the three-dimensional memory (e.g., the three-dimensional memory 110 or the three-dimensional memory 210) is thermally treated in a hydrogen atmosphere, so that hydrogen ions in the silicon nitride layer (e.g., the silicon nitride layer 104 or the silicon nitride layer 206) are further diffused into the vertical channel structure (e.g., the vertical channel structure 103 or the vertical channel structure 203), thereby repairing lattice defects in the vertical channel structure and effectively improving the electrical response sensitivity of the device.
FIG. 9 is a flowchart illustrating another method for improving electrical performance of a three-dimensional memory according to an embodiment of the present invention. Fig. 10 to 11 are schematic process steps of another method for improving electrical characteristics of a three-dimensional memory according to an embodiment of the invention.
Referring to fig. 9, in some embodiments of the invention, step 120 (thermal treatment of the three-dimensional memory under a hydrogen atmosphere) may further include, after:
at step 910, the silicon nitride layer is removed.
Referring to fig. 4 and 10, the silicon nitride layer 104 of the three-dimensional memory 120 is removed. Illustratively, a dry etch may be used to remove the silicon nitride layer 104 on the stack structure 102. Preferably, the dry etching may use an etching gas containing fluorine (F), such as fluorides, e.g., carbon tetrafluoride, perfluorobutadiene, nitrogen trifluoride, hexafluoroethane, perfluoropropane, trifluoromethane, etc., but the present invention is not limited thereto.
Referring to fig. 11, a metal interconnection structure 105 and an intermetal dielectric layer 106 are formed on the stacked structure 102. The distribution, material and formation process of the metal interconnection structure 105 and the intermetal dielectric layer 106 may refer to the embodiment described in fig. 5, and will not be further expanded herein.
At step 930, a passivation layer is deposited on the intermetal dielectric layer.
With continued reference to fig. 11, a passivation layer 107 is deposited over the intermetal dielectric layer 106 to form a three-dimensional memory 130.
In an embodiment of the present invention, the passivation layer 107 may be silicon nitride, and has a thickness of:
FIG. 12 is a flowchart illustrating another method for improving electrical performance of a three-dimensional memory according to an embodiment of the present invention. Fig. 13 to 14 are schematic process steps of another method for improving electrical characteristics of a three-dimensional memory according to an embodiment of the invention.
Referring to fig. 12, in another embodiment of the present invention, step 120 (heat-treating the three-dimensional memory under a hydrogen atmosphere) may further include:
Referring to fig. 7 and 13, the silicon nitride layer 206 of the three-dimensional memory 220 is removed. Illustratively, a dry etch may be used to remove the silicon nitride layer 206 on the stacked structure 202, i.e., on the surface of the intermetal dielectric layer 205. Preferably, the dry etching may use an etching gas containing fluorine, such as fluorides of carbon tetrafluoride, perfluorobutadiene, nitrogen trifluoride, hexafluoroethane, perfluoropropane, trifluoromethane, etc., but the present invention is not limited thereto.
Referring to fig. 14, a passivation layer 207 is deposited on the intermetal dielectric layer 205 to form a three-dimensional memory 230.
In an embodiment of the present invention, the passivation layer 207 may be silicon nitride, and has a thickness of:
the method for improving the electrical property of the three-dimensional memory repairs the lattice defects in the vertical channel structure (such as the vertical channel structure 103 or the vertical channel structure 203) through the silicon nitride layer with high hydrogen ion content deposited in the step 110 and the heat treatment process in the step 120, and improves the electrical response sensitivity of the device.
Therefore, when the passivation layer (e.g., the passivation layer 107 or the passivation layer 207) is deposited on the intermetal dielectric layer (e.g., the intermetal dielectric layer 106 or the intermetal dielectric layer 205) in step 930 or step 1120, the content of hydrogen ions therein does not need to be strictly controlled, the effect of isolating moisture and ions can be achieved by using a smaller passivation layer thickness of silicon nitride, and the manufacturing cost is reduced.
The flowcharts shown in fig. 1, fig. 9 and fig. 12 are used to illustrate the steps/operations performed by the method for improving the electrical property of the three-dimensional memory according to the embodiment of the present application. It should be understood that the above or below steps/operations are not necessarily performed exactly in order. Rather, various steps/operations may be processed in reverse order or concurrently. Meanwhile, other steps/operations may be added to or removed from these processes.
The above embodiments of the present invention provide a method for improving the electrical property of a three-dimensional memory, which can repair the lattice defect in the vertical channel structure and effectively improve the electrical response sensitivity of the device.
Another aspect of the present invention is to provide a three-dimensional memory fabricated by the method for improving electrical characteristics of a three-dimensional memory, wherein the three-dimensional memory has fewer lattice defects in a vertical channel structure and has a higher electrical response sensitivity.
Referring to fig. 2, the three-dimensional memory 100 includes: a substrate 101, a stacked structure 102 located on the substrate 101, and a vertical channel structure 103 passing through the stacked structure 102.
Other details of the present embodiment may refer to the embodiments described in fig. 1 to 4, and will not be further described herein.
It should be noted that the method for improving the electrical property of the three-dimensional memory can be implemented in the three-dimensional memory 100 shown in fig. 2 or a variation thereof, but the invention is not limited thereto.
Another aspect of the present invention is to provide a three-dimensional memory having fewer lattice defects in a vertical channel structure, and having a higher electrical response sensitivity.
Referring to fig. 11 or 14, the three-dimensional memory (e.g., the three-dimensional memory 130 or the three-dimensional memory 230) includes: a substrate (e.g., substrate 101 or substrate 201), a stacked structure (e.g., stacked structure 102 or stacked structure 202) located on the substrate (e.g., substrate 101 or substrate 201); a vertical channel structure (e.g., vertical channel structure 103 or vertical channel structure 203) through a stacked structure (e.g., stacked structure 102 or stacked structure 202) in a stacked structure (e.g., stacked structureMetal interconnect structure (e.g., metal interconnect structure 105 or metal interconnect structure 204) and intermetal dielectric layer (e.g., intermetal dielectric layer 106 or intermetal dielectric layer 205) on structure 102 or stacked structure 202), and passivation layer (e.g., passivation layer 107 or passivation layer 207) on the intermetal dielectric layer (e.g., intermetal dielectric layer 106 or intermetal dielectric layer 205). The passivation layer (e.g., passivation layer 107 or passivation layer 207) is made of silicon nitride, and has a thickness of:
the three-dimensional memory can realize the effect of isolating moisture and ions by using the smaller thickness of the passivation layer of the silicon nitride, thereby effectively reducing the manufacturing cost. Meanwhile, the vertical channel structure of the three-dimensional memory has less lattice defects, and the three-dimensional memory has higher electrical response sensitivity.
Other implementation details of the three-dimensional memory of the present embodiment can refer to the embodiments described in fig. 1 to 14, and are not expanded herein. Those skilled in the art can make appropriate adjustments to the specific structure of the three-dimensional memory according to actual needs, and the invention is not limited thereto.
It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (15)
1. A method of improving electrical performance of a three-dimensional memory, the three-dimensional memory comprising: a substrate, a stack structure on the substrate, and a vertical channel structure through the stack structure, the method comprising the steps of:
depositing a silicon nitride layer on the stacked structure; and
performing heat treatment on the three-dimensional memory under a hydrogen atmosphere;
wherein hydrogen ions in the silicon nitride layer are diffused into the vertical channel structure by the heat treatment.
2. The method of claim 1, wherein the three-dimensional memory further comprises a metal interconnection structure and an intermetallic dielectric layer between the silicon nitride layer and the stacked structure, and wherein hydrogen ions in the silicon nitride layer diffuse into the vertical channel structure through the metal interconnection structure.
3. According to claim1 or 2, wherein the hydrogen ion content of the silicon nitride layer is at least 1.98 x 1022/cm2。
4. A method according to claim 1 or 2, wherein the thickness of the silicon nitride layer is:
5. the method of claim 1 or 2, wherein depositing the silicon nitride layer on the stack structure comprises depositing the silicon nitride layer on the stack structure by a chemical vapor deposition process
The deposition rate of (a) deposits the silicon nitride layer.
6. The method of claim 5, wherein the reaction gas for depositing the silicon nitride layer comprises monosilane and ammonia, and the ratio of the monosilane to the ammonia is at least 1.5: 1.
7. The method of claim 5, wherein the RF power to deposit the silicon nitride layer is: 600-.
8. The method of claim 5, wherein the chamber pressure for depositing the silicon nitride layer is: 530 ℃ and 670 Pa.
9. The method of claim 1, further comprising, after the thermally treating the three-dimensional memory under a hydrogen atmosphere:
removing the silicon nitride layer;
forming a metal interconnection structure and an intermetallic dielectric layer on the stacked structure; and
and depositing a passivation layer on the intermetallic dielectric layer.
10. The method of claim 2, further comprising, after the thermally treating the three-dimensional memory under a hydrogen atmosphere:
removing the silicon nitride layer; and
and depositing a passivation layer on the intermetallic dielectric layer.
11. The method according to claim 9 or 10, wherein the passivation layer is made of silicon nitride and has a thickness of:
12. the method of claim 1, wherein the bottom of the vertical channel structure has an epitaxial layer, and hydrogen ions in the silicon nitride layer are diffused into the epitaxial layer by the thermal treatment.
13. The method of claim 1, wherein a sidewall of the vertical channel structure has a semiconductor layer, and hydrogen ions in the silicon nitride layer are diffused into the semiconductor layer by the thermal treatment.
14. A three-dimensional memory fabricated using the method of claim 1, comprising:
a substrate;
a stack structure on the substrate; and
a vertical channel structure passing through the stacked structure.
15. A three-dimensional memory, comprising:
a substrate;
a stack structure on the substrate;
a vertical channel structure through the stacked structure;
the metal interconnection structure and the intermetallic dielectric layer are positioned on the stacking structure; and
the passivation layer is positioned on the intermetallic dielectric layer;
wherein, the passivation layer is made of silicon nitride and has the following thickness:
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| US20040011279A1 (en) * | 2002-07-18 | 2004-01-22 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
| US20180342455A1 (en) * | 2017-05-25 | 2018-11-29 | Sandisk Technologies Llc | Interconnect structure containing a metal silicide hydrogen diffusion barrier and method of making thereof |
| CN111244101A (en) * | 2020-01-16 | 2020-06-05 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040011279A1 (en) * | 2002-07-18 | 2004-01-22 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor device |
| US20180342455A1 (en) * | 2017-05-25 | 2018-11-29 | Sandisk Technologies Llc | Interconnect structure containing a metal silicide hydrogen diffusion barrier and method of making thereof |
| CN111244101A (en) * | 2020-01-16 | 2020-06-05 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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