CN111766746B

CN111766746B - Display panel, driving method thereof and display device

Info

Publication number: CN111766746B
Application number: CN202010588412.7A
Authority: CN
Inventors: 王婷; 华火梅; 周洪波; 伍黄尧; 曾晓岚; 赖国昌
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2022-06-03
Anticipated expiration: 2040-06-24
Also published as: CN111766746A

Abstract

The invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises a first substrate and a second substrate; the second substrate comprises a plurality of peep-proof control electrodes, and the polarity of a voltage signal input by a pixel electrode corresponding to the same sub-pixel unit is the same as that of a voltage signal input by the peep-proof control electrode; the first substrate includes a driving circuit including: a shift register unit; the input end of the enabling circuit is connected to the second output end of the shift register unit; a first control module, wherein a control end of the first control module is connected to an output end of the enabling circuit, and an input end of the first control module is connected to the first voltage signal line; the control end of the second control module is connected to the output end of the enabling circuit, the input end of the second control module is connected to the second voltage signal line, and the output ends of the first control module and the second control module are electrically connected with the peep-proof control electrode; the voltage polarity of the first voltage signal line is opposite to the voltage polarity of the second voltage signal line. The invention improves the problem of flicker of the display panel.

Description

Display panel, driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.

Background

A Liquid Crystal Display (LCD) has advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and is dominant in the field of flat panel displays. At present, liquid crystal display devices are gradually developed toward wide viewing angles, and for example, liquid crystal display devices using an in-plane switching mode (IPS) or a fringe field switching mode (FFS) can realize wide viewing angles. The wide viewing angle design enables the user to see a complete and undistorted picture from all directions. However, people are increasingly paying attention to protecting their privacy. Therefore, the display with single viewing angle mode has not been able to satisfy the user's requirement. In addition to the requirement of a wide viewing angle, there is also a need to be able to switch or adjust the display device to a narrow viewing angle mode where privacy is required.

In order to switch a wide viewing angle and a narrow viewing angle of a liquid crystal display device, a vertical electric field is generally applied to liquid crystal molecules by arranging a peep-proof control electrode on one side of a color film substrate, and the switching between the wide viewing angle and the narrow viewing angle is realized by changing an inclination angle of the liquid crystal molecules, but the problem of panel flicker exists.

Disclosure of Invention

In view of the above, the present invention provides a display panel to solve the problem of panel flicker.

In one aspect, the present invention provides a display panel, including a first substrate and a second substrate that are disposed opposite to each other, and a liquid crystal layer interposed between the first substrate and the second substrate:

the first substrate comprises a substrate base plate, a plurality of sub-pixel units defined by a plurality of scanning lines and a plurality of data lines in a crossed mode are arranged on the substrate base plate, the sub-pixel units are arranged in an array mode, each sub-pixel unit is provided with a pixel electrode, the pixel electrodes are electrically connected with the data lines through switch transistors, and the polarities of voltage signals supplied to adjacent data lines are opposite;

the second substrate comprises a plurality of peep-proof control electrodes extending along the extension direction of the scanning line, and the polarity of a voltage signal input by the pixel electrode corresponding to the same sub-pixel unit is the same as that of a voltage signal input by the peep-proof control electrode;

the first substrate further includes a driving circuit including:

a first output end of the shift register unit is electrically connected with the scanning line;

the control end of the enabling circuit is connected to the trigger signal end, and the input end of the enabling circuit is connected to the second output end of the shift register unit;

the control end of the first control module is connected to the output end of the enabling circuit, the input end of the first control module is connected to the first voltage signal line, and the output end of the first control module is electrically connected with the peep-proof control electrode;

a control end of the second control module is connected to an output end of the enabling circuit, an input end of the second control module is connected to a second voltage signal line, and an output end of the second control module is electrically connected with the peep-proof control electrode;

the voltage polarity of the first voltage signal line is opposite to the voltage polarity of the second voltage signal line.

On the other hand, the invention also provides a driving method of the display panel,

the display panel includes:

the liquid crystal display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is clamped between the first substrate and the second substrate:

the first substrate comprises a substrate base plate, the substrate base plate comprises a plurality of sub-pixel units defined by a plurality of scanning lines and a plurality of data lines in a crossed mode, the sub-pixel units are arranged in an array mode, each sub-pixel unit is provided with a pixel electrode, the pixel electrodes are electrically connected with the data lines through switch transistors, and the polarities of voltage signals supplied to adjacent data lines are opposite;

the second substrate comprises a plurality of peep-proof control electrodes extending along the scanning line direction, and the polarity of a voltage signal input by the pixel electrode corresponding to the same sub-pixel unit is the same as that of a voltage signal input by the peep-proof control electrode;

the first substrate further includes a driving circuit including:

a voltage polarity of the first voltage signal line is opposite to a voltage polarity of the second voltage signal line;

the enabling circuit includes:

a first inverter having a first terminal connected to the second output terminal of the shift register unit, a second terminal connected to a high potential, a third terminal connected to a low potential, and a fourth terminal connected to a first node;

the first module and the first inverter form a first clock inverter, the first end of the first clock inverter is connected to the first node, the second end of the first clock inverter is connected to the control ends of the first control module and the second control module, the third end of the first clock inverter is connected to a high potential, the fourth end of the first clock inverter is connected to a low potential, and the fifth end of the first clock inverter is connected to the first end of the first inverter;

a second module, which forms a second clock inverter with the first inverter, wherein the first terminal of the second clock inverter is connected to the second terminal of the first module, the second terminal of the second clock inverter is connected to the fifth terminal of the first module, the third terminal of the second clock inverter is connected to the first node, the fourth terminal of the second clock inverter is connected to a high potential, and the fifth terminal of the second clock inverter is connected to a low potential;

a control end of the trigger module is electrically connected with the trigger signal end, a first end of the trigger module is connected to a low potential, and a second end of the trigger module is connected to a sixth end of the first module;

a second inverter, a first end of which is connected to the second end of the trigger module, a second end of which is connected to the sixth end of the second module, a third end of which is connected to a high potential, and a fourth end of which is connected to a low potential;

the first end of the storage capacitor is connected to a high potential, and the second end of the storage capacitor is connected to the control ends of the first control module and the second control module;

the driving method includes:

in the first stage, a high potential is input to the trigger signal terminal, the trigger module is turned on, the low potential is transmitted to the sixth terminal of the first module, the second output terminal of the shift register unit outputs a low potential, the first inverter is turned on, the high potential is transmitted to the first node, and the first node transmits the high potential to the first terminal of the first module and the third terminal of the second module;

in the second stage, a low potential is input to the trigger signal end, and the trigger module is turned off; a second output end of the shift register unit outputs a high potential, a low potential is input to the first node, the first node transmits the low potential to a first end of the first module and a third end of the second module, and the high potential is input to control ends of the first control module and the second control module and a first end of the second module; the second control module is conducted, and the voltage of the second voltage signal line is input to the peep-proof control electrode;

in the third stage, a low potential is input to the trigger signal end, and the trigger module is turned off; a second output end of the shift register unit outputs a low potential, a high potential is transmitted to the first node, the first node transmits the high potential to a first end of the first module and a third end of the second module, the low potential is transmitted to a second end of the second inverter through a sixth end of the second module, and the high potential is transmitted to the sixth end of the first module through the first end of the second inverter;

in the fourth stage, a low potential is input to the trigger signal end, and the trigger module is turned off; the second output end of the shift register unit outputs a high potential, a low potential is transmitted to the control ends of the first control module and the second control module through the second end of the first module, the first control module is conducted, and the voltage of the first voltage signal line is input to the peep-proof control electrode.

In another aspect, the invention further provides a display device comprising the display panel.

Compared with the prior art, the display panel, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:

the display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are arranged oppositely, the liquid crystal layer is clamped between the first substrate and the second substrate, the first substrate comprises a substrate, a plurality of scanning lines and a plurality of data lines are arranged on the substrate in a crossed and limited mode, the plurality of sub-pixel units are arranged in an array mode, each sub-pixel unit is provided with a pixel electrode, the pixel electrodes are electrically connected with the data lines through switching transistors, and the polarities of voltage signals supplied to the adjacent data lines are opposite; the second substrate comprises a plurality of peep-proof control electrodes extending along the extension direction of the scanning line, and the polarity of a voltage signal input by a pixel electrode corresponding to the same sub-pixel unit is the same as that of a voltage signal input by the peep-proof control electrode; the first substrate further includes a driving circuit including: a first output end of the shift register unit is electrically connected with the scanning line; the control end of the enabling circuit is connected to the trigger signal end, and the input end of the enabling circuit is connected to the second output end of the shift register unit; the control end of the first control module is connected to the output end of the enabling circuit, the input end of the first control module is connected to the first voltage signal line, and the output end of the first control module is electrically connected with the peep-proof control electrode; the control end of the second control module is connected to the output end of the enabling circuit, the input end of the second control module is connected to the second voltage signal line, and the output end of the second control module is electrically connected with the peep-proof control electrode; the voltage polarity of the first voltage signal line is opposite to the voltage polarity of the second voltage signal line. The pixel driving mode of the display panel adopts column inversion, the voltage of the first voltage signal line and the voltage of the second voltage signal line can be alternately applied to the peep-proof control electrode according to a time sequence through the enabling circuit, the polarity of a voltage signal input by a pixel electrode corresponding to the same sub-pixel unit is the same as that of a voltage signal input by the peep-proof control electrode, and the problem of panel flicker is fundamentally solved.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a display panel in the prior art;

FIG. 2 is a schematic diagram of the electric field generated by the adjacent sub-pixels in FIG. 1 during displaying;

FIG. 3 is a schematic diagram of the same sub-pixel in FIG. 1 generating electric fields in two adjacent frames;

FIG. 4 is a schematic plane structure diagram of a display panel according to the present invention;

FIG. 5 is a cross-sectional view taken along line A-A' of FIG. 4;

FIG. 6 is a schematic diagram of electric fields generated by adjacent frames of the same sub-pixel during display;

FIG. 7 is a schematic plan view of a peep-proof control electrode according to the present invention;

FIG. 8 is a schematic diagram of an enable circuit according to the present invention;

FIG. 9 is a timing diagram of a portion of the ports of FIG. 8;

FIG. 10 is a schematic diagram of another enable circuit configuration provided by the present invention;

FIG. 11 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 12 is a cross-sectional view taken along line B-B' of FIG. 4;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

In order to solve the problem of panel flicker in the liquid crystal display device when switching between a wide viewing angle and a narrow viewing angle, the inventors have conducted the following studies on the display device in the related art:

referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of a display panel in the prior art; FIG. 2 is a schematic diagram of the electric field generated by the adjacent sub-pixels in FIG. 1 during displaying; FIG. 3 is a schematic diagram of the same sub-pixel in FIG. 1 generating electric fields in two adjacent frames; the display panel 000 in fig. 1 includes a first substrate 01 and a second substrate 02 that are disposed opposite to each other, and a liquid crystal layer 03 interposed between the first substrate 01 and the second substrate 02. The first substrate 01 includes a substrate 010, a common electrode 09 and a pixel electrode 08 are disposed on a side of the substrate 010 close to the second substrate 02, of course, a plurality of sub-pixel units defined by crossing a plurality of scanning lines and a plurality of data lines (not shown) are disposed on the substrate 010, a pixel electrode 08 is correspondingly disposed in each sub-pixel unit, and the pixel electrode 08 is electrically connected to the data lines (not connected) through a switching transistor. The second substrate 02 includes a substrate 04, a color resistor 05 disposed on a side of the substrate 04 close to the first substrate 01, a black matrix 06 between the color resistors 05, and a privacy control electrode 07 disposed on a side of the color resistor 05 close to the first substrate 01, wherein the privacy control electrode 07 extends along a first direction X, and the display panel performs row scanning and column inversion during displaying.

As shown in fig. 2, in the prior art, a constant voltage is usually applied to the privacy protection control electrode 07, and as shown in fig. 2, the voltage applied to the privacy protection control electrode 07 is +2V, the voltages applied to the pixel electrodes in the adjacent sub-pixel units are +5V and-5V, respectively, the driving voltages of the pixels in the adjacent columns are kept in opposite polarities, and the voltage applied to the common electrode 09 is-0.1V. Of course, the electric fields E1 and E2 are formed between the pixel electrode 08 and the privacy control electrode 07 of the adjacent sub-pixels P1 and P2, but since the electric field E1 is formed between +5V and +2V in the sub-pixel P1 and the electric field E2 is formed between +2V and-5V in the sub-pixel P2, there is a difference between the electric fields E1 and E2. Of course, the display effect is that the liquid crystal is deflected by the electric field E3 between the pixel electrode 08 and the common electrode 09, because the presence of the electric fields E1 and E2 can interfere with the liquid crystal inversion, as shown in fig. 2, the liquid crystal deflection angle in the sub-pixel P1 is θ 1, and the liquid crystal deflection angle in the sub-pixel P2 is θ 2, and there is a large difference in the liquid crystal deflection angles in the sub-pixel P1 and the sub-pixel P2, resulting in the difference in the brightness of the adjacent sub-pixel P1 and the sub-pixel P2, which causes display flicker.

Referring again to fig. 3, fig. 3 shows schematic diagrams of electric fields of a positive frame and a negative frame of the same sub-pixel, when the sub-pixel P1 is in a positive frame, the voltage applied to the privacy-protection control electrode 07 is +2V, the voltage applied to the pixel electrode 08 is +5V, the voltage applied to the common electrode 09 is-0.1V, and an electric field E1 is formed between the pixel electrode 08 and the privacy-protection control electrode 07, when the sub-pixel P1 is in a negative frame, the voltage applied to the privacy-protection control electrode 07 is +2V, the voltage applied to the pixel electrode 08 is-5V, the voltage applied to the common electrode 09 is-0.1V, and an electric field E1 'is formed between the pixel electrode 08 and the privacy-protection control electrode 07, so there is a difference between the electric fields E1 and E1'. Of course, the display effect is that the electric field E3 between the pixel electrode 08 and the common electrode 09 deflects the liquid crystal, because the existence of the electric fields E1 and E1 'can interfere the liquid crystal inversion, as shown in fig. 3, the liquid crystal deflection angle is θ 1 in the positive frame, and the deflection angle is θ 1' in the negative frame, and there is a large difference between the liquid crystal deflection angles in the positive frame and the negative frame, which results in a large brightness difference between the positive frame and the negative frame of the same sub-pixel, and forms visual flicker.

In short, since the display panel is line-scanned and column-inverted, when the anti-peeping control electrode 07 is disposed, an electric field formed between the anti-peeping control electrode 07 and the pixel electrode 08 when the positive and negative frames of adjacent sub-pixels or the same sub-pixel are inverted affects the display electric field, and causes flicker.

The present invention provides a display panel, a driving method thereof, and a display device, and the following description will be made in detail with respect to specific embodiments of the display panel.

Referring to fig. 4, 5 and 6, fig. 4 is a schematic plane structure diagram of a display panel according to the present invention, fig. 5 is a cross-sectional view taken along a direction a-a' in fig. 4, and fig. 6 is a schematic diagram of electric fields generated by adjacent frames of the same sub-pixel during display.

The display panel 100 in this embodiment includes a first substrate 1 and a second substrate 2 disposed opposite to each other, and a liquid crystal layer 3 interposed between the first substrate 1 and the second substrate 2.

The first substrate 1 includes a substrate 10, a plurality of sub-pixel units P defined by a plurality of scan lines 11 and a plurality of data lines 12 are disposed on the substrate 10, the plurality of sub-pixel units P are arranged in an array, each sub-pixel unit P has a pixel electrode 8, the pixel electrodes 8 are electrically connected to the data lines 12 through switching transistors 13, and the polarities of voltage signals provided to adjacent data lines 12 are opposite.

It will be appreciated that the pixels of the display panel are driven with column inversion, with adjacent columns of pixels being of opposite polarity.

The second substrate 2 includes a plurality of anti-peep control electrodes 7 extending along the extending direction of the scanning line 11, and the polarity of the voltage signal input by the pixel electrode 8 corresponding to the same sub-pixel unit P is the same as the polarity of the voltage signal input by the anti-peep control electrode 7.

Referring to fig. 5, voltages applied to the privacy control electrode 7 corresponding to the adjacent two sub-pixels P1 and P2 are +2V and-2V, respectively, voltages applied to the pixel electrodes in the adjacent sub-pixel units are +5V and-5V, respectively, and the voltage applied to the common electrode 9 remains unchanged at-0.1V. Electric fields E1 and E2 are formed between the pixel electrode 8 and the privacy control electrode 7 of the adjacent sub-pixels P1 and P2, an electric field E1 in the sub-pixel P1 is formed by +5V and +2V, and an electric field E2 in the sub-pixel P2 is formed by-2V and-5V, so that the absolute values of the electric fields E1 and E2 are equal and have no difference. The display effect is that the liquid crystal is deflected by the electric field E3 between the pixel electrode 8 and the common electrode 9, the liquid crystal is disturbed to turn over by the existence of the electric fields E1 and E2, and as shown in FIG. 5, the deflection angles of the liquid crystal in the sub-pixels P1 and P2 are equal and are all theta 1 because the absolute values of E1 and E2 are the same, so that the brightness of the adjacent sub-pixel P1 and the brightness of the sub-pixel P2 are not different, and the problem of adjacent sub-pixel flicker is improved. Similarly, referring to fig. 6, the luminance of adjacent frames of the same subpixel is not different, and when the subpixel P1 is in a positive frame, the voltage applied to the privacy-improving control electrode 07 is +2V, the voltage applied to the pixel electrode 8 is +5V, the voltage applied to the common electrode 9 is-0.1V, an electric field E1 is formed between the pixel electrode 8 and the privacy-improving control electrode 7, when the subpixel P1 is in a negative frame, the voltage applied to the privacy-improving control electrode 07 is-2V, the voltage applied to the pixel electrode 8 is-5V, the voltage applied to the common electrode 09 is-0.1V, an electric field E1 'is formed between the pixel electrode 8 and the privacy-improving control electrode 7, and the absolute values of the electric fields E1 and E1' are equal. The display effect is that the electric field E3 between the pixel electrode 8 and the common electrode 9 deflects the liquid crystal, because the existence of the electric fields E1 and E1' can interfere the liquid crystal to turn over, but because the absolute values of E1 and E2 are the same, the deflection angles of the sub-pixel P1 in the positive frame and the negative frame are equal and are all theta 1, and the problem of flicker of the positive frame and the negative frame of the same sub-pixel is improved.

In some alternative embodiments, with continued reference to fig. 4, the peep-proof control electrode 7 includes first electrode portions 7a and second electrode portions 7b which are staggered, a forward projection of the first electrode portions 7a on the plane of the substrate 10 overlaps a forward projection of the odd-numbered pixel electrodes 8 on the plane of the substrate 10, and a polarity of a voltage signal supplied to the first electrode portions 7a is the same as a polarity of a voltage signal supplied to the odd-numbered pixel electrodes 8, a forward projection of the second electrode portions 7b on the plane of the substrate 10 overlaps a forward projection of the even-numbered pixel electrodes 8 on the plane of the substrate 10, and a polarity of a voltage signal supplied to the second electrode portions 7b is the same as a polarity of a voltage signal supplied to the even-numbered pixel electrodes 8.

Referring to fig. 7 and fig. 7 which are schematic plane structural diagrams of a privacy-protecting control electrode according to the present invention, the privacy-protecting control electrode 7 in fig. 7 extends along the extending direction X of the scan line, and has a first electrode portion 7a and a second electrode portion 7b, the first electrode portion 7a and the second electrode portion 7b are arranged in a staggered manner, it can be understood that the first electrode portion 7a is electrically connected together, the second electrode portion 7b is electrically connected together, and voltage signals can be uniformly provided for the first electrode portion 7a or the second electrode portion 7b, so that when the pixel driving manner is column inversion, it can be ensured that the polarity of the voltage signal input by the pixel electrode corresponding to the same subpixel unit P is the same as the polarity of the voltage signal input by the privacy-protecting control electrode 7, that is the same as the polarity of the voltage signal provided to the first electrode portion 7a as the polarity of the voltage signal provided to the odd-digit pixel electrode 8, the polarity of the voltage signal supplied to the second electrode portion 7b is the same as the polarity of the voltage signal supplied to the pixel electrode 8 of even-numbered bits, thereby improving the problem of flicker of the display panel.

With continued reference to fig. 4, the first substrate further includes a driving circuit 14, the driving circuit 14 including:

a shift register unit 15 having a first output terminal 151 electrically connected to the scan line 11;

it is understood that the shift register unit 15 further has a first input terminal 153 and a second input terminal 154, the first input terminal 153 is electrically connected to the first clock signal line CK1, the second input terminal 154 is electrically connected to the second clock signal line CK2, and provides a high level and a low level for the shift register unit 15, respectively, and the first shift register unit 15 is further connected to a trigger terminal ST.

An enable circuit EN having a control terminal connected to the trigger signal terminal STV and an input terminal connected to the second output terminal 152 of the shift register unit 15;

a first control module 16, a control end of which is connected to the output end of the enable circuit EN, an input end of which is connected to the first voltage signal line comA, and an output end of which is electrically connected to the peep-proof control electrode 7;

a second control module 17, a control end of which is connected to the output end of the enable circuit EN, an input end of which is connected to the second voltage signal line comB b, and an output end of which is electrically connected to the peep-proof control electrode 7;

the voltage polarity of the first voltage signal line comA is opposite to the voltage polarity of the second voltage signal line comB.

It can be understood that the signals output by the first output terminal and the second output terminal of the shift register unit 15 are the same, the display panel is in row-scan column inversion, the first output terminal outputs a signal to the scan line, the data line transmits a data signal to the pixel electrode, and at the same time, the enable circuit EN controls one of the first control module 16 and the second control module 17 to be turned on, so as to transmit the voltage of the first voltage signal line comA or the second voltage signal line comB b to the anti-peep control electrode 7, thereby implementing that the polarity of the voltage signal input by the pixel electrode 8 corresponding to the same sub-pixel unit is the same as the polarity of the voltage signal input by the anti-peep control electrode 7.

Compared with the prior art, the display panel has at least the following beneficial effects:

the display panel is in line scanning column inversion, a first output end outputs signals to scanning lines, data lines transmit data signals to pixel electrodes, meanwhile, an enabling circuit controls one of a first control module or a second control module to be conducted, and therefore the voltages of a first voltage signal line or a second voltage signal line are transmitted to a peep-proof control electrode, the polarity of voltage signals input by the pixel electrodes corresponding to the same sub-pixel unit is the same as the polarity of voltage signals input by the peep-proof control electrode, and the problem that electric fields formed between the peep-proof control electrode and the pixel electrodes when positive and negative frames of adjacent sub-pixels or the same sub-pixel are inverted can influence the display electric fields to cause flicker is solved.

In some alternative embodiments, referring to fig. 8, fig. 8 is a schematic diagram of an enable circuit structure provided in the present invention, and in combination with fig. 4 and fig. 8, the enable circuit EN includes:

a first inverter 20 having a first terminal 201 connected to the second output terminal of the shift register unit, a second terminal 202 connected to the high voltage VGH, a third terminal 203 connected to the low voltage VGL, and a fourth terminal 204 connected to the first node N1;

the first inverter 20 functions to provide two clock signals of opposite polarity to the first block 30 and the second block 40.

The first module 30 and the first inverter 20 form a first clock inverter, a first terminal 301 of which is connected to the first node N1, a second terminal 302 of which is connected to control terminals (shown as out in fig. 8) of the first control module and the second control module, a third terminal 303 of which is connected to the high voltage VGH, a fourth terminal of which is connected to the low voltage VGL, and a fifth terminal 305 of which is connected to the first terminal 201 of the first inverter 20;

the first module 30, the first inverter 20, the trigger module 50, and the second inverter 60 switch the out signal between a high voltage level and a low voltage level.

A second module 40, which forms a second clocked inverter with the first inverter 20, and has a first terminal 401 connected to the second terminal 302 of the first module 30, a second terminal 402 connected to the fifth terminal 305 of the first module 30, a third terminal 403 connected to the first node N1, a fourth terminal 404 connected to the high voltage VGH, and a fifth terminal 405 connected to the low voltage VGL;

in the second block 40, the out signal is used as an input signal of the second block 40, and the output signal is opposite to the out signal, so that the input signal of the second inverter is switched between a high potential and a low potential.

A trigger module 50 having a control terminal electrically connected to the trigger signal terminal STV, a first terminal 501 connected to the low voltage VGL, and a second terminal 502 connected to the sixth terminal 306 of the first module 30;

the trigger block 50 provides an input signal of a low potential to the first block 30.

A second inverter 60 having a first terminal 601 connected to the second terminal 502 of the trigger module 50, a second terminal 602 connected to the sixth terminal 406 of the second module 40, a third terminal 603 connected to the high voltage VGH, and a fourth terminal 604 connected to the low voltage VGL;

the second inverter 60 provides a high input signal to the first module 30.

The storage capacitor Cst has a first terminal connected to the high voltage VGH and a second terminal connected to the control terminals (out in fig. 8) of the first and second control modules. It will be appreciated that the storage capacitor is used to maintain the potential at the control terminals (out in fig. 8) of the first and second control modules.

The enabling circuit EN can realize the switching between high potential and low potential of the out signal along with the Next signal, so that the signal output in one frame is high potential voltage, the signal output in one frame is low potential voltage, and the voltages of the first voltage signal line comA and the second voltage signal line comB are selectively switched.

With reference to fig. 7, 8 and 9, fig. 9 is a timing diagram of a portion of ports in fig. 8, and the present invention further provides a driving method of a display panel, where the driving method includes:

in the first stage t1, a high voltage is input to the trigger signal terminal STV, the trigger module 50 is turned on, the low voltage is transmitted to the sixth terminal 306 of the first module 30, the second output terminal of the shift register unit outputs a low voltage (Next in fig. 8), the first inverter 20 is turned on, the high voltage is transmitted to the first node N1, and the first node N1 transmits the high voltage to the first terminal 301 of the first module 30 and the third terminal 403 of the second module 40.

In the second stage t2, a low potential is input to the trigger signal terminal STV, and the trigger module 50 is turned off; the second output terminal of the shift register unit outputs a high potential, the low potential VGL is input to the first node N1, the first node N1 transmits the low potential to the first terminal 301 of the first module 30 and the third terminal 403 of the second module 40, and the high potential VGH is input to the control terminals of the first control module 16 and the second control module 17, and the first terminal 401 of the second module 40; the first control module 16 is turned on, and the voltage of the first voltage signal line comA is input to the peep-proof control electrode.

At this time, when the first voltage signal line comA is at a high potential, the signal input to the peep-proof control electrode is at a high potential, and the voltage of the corresponding pixel electrode is also at a high potential, so that the polarity of the voltage signal input by the pixel electrode corresponding to the same sub-pixel unit is ensured to be the same as the polarity of the voltage signal input by the peep-proof control electrode. In the third stage t3, a low potential is input to the trigger signal terminal STV, and the trigger module 50 is turned off; the second output terminal of the shift register unit outputs a low potential, the high potential VGH is transmitted to the first node N1, the first node N1 transmits a high potential to the first terminal 301 of the first module 30 and the third terminal 403 of the second module 40, the low potential is transmitted to the second terminal 602 of the second inverter 60 through the sixth terminal 406 of the second module 40, and the high potential is transmitted to the sixth terminal 306 of the first module 30 through the first terminal 601 of the second inverter 60.

A fourth stage t4, in which a low potential is input to the trigger signal terminal STV, and the trigger module 50 is turned off; the second output end of the shift register unit outputs a high potential, the low potential is transmitted to the control ends of the first control module 16 and the second control module 17 through the second end 302 of the first module 30, the second control module 17 is turned on, and the voltage of the second voltage signal line comB b is input to the peep-proof control electrode 7.

At this time, when the second voltage signal line comB is at a low voltage, the signal input to the peep-proof control electrode is at a low voltage, and the voltage of the corresponding pixel electrode is at a low voltage, so that the polarity of the voltage signal input by the pixel electrode corresponding to the same sub-pixel unit is ensured to be the same as the polarity of the voltage signal input by the peep-proof control electrode.

According to the driving method, the enabling circuit EN controls the voltage signals of the first voltage signal line comA and the second voltage signal line comB to be alternately transmitted to the peep-proof control electrode according to the time sequence, so that the polarity of the voltage signal input by the pixel electrode corresponding to the same sub-pixel unit is the same as the polarity of the voltage signal input by the peep-proof control electrode, and the problem of flicker of a display panel is solved.

It can be understood that in the same frame, the polarity of the voltage signal supplied to the first electrode portion 7a through the first voltage signal line comA (the first voltage signal line comA on the left side of the display area AA in fig. 4) is the same as the polarity of the voltage signal of the pixel electrode 8 of the odd-numbered bit, and is high, and the polarity of the voltage signal supplied to the second electrode portion 7b through the second voltage signal line comB (the second voltage signal line comB b on the right side of the display area AA in fig. 4) is the same as the polarity of the voltage signal of the pixel electrode 8 of the even-numbered bit, and is low, so that the polarity of the voltage signal inputted to the pixel electrode corresponding to the same sub-pixel unit is the same as the polarity of the voltage signal inputted to the peep prevention control electrode, thereby improving the problem of the flicker of the display panel.

In some alternative embodiments, referring to fig. 4 and 10, fig. 10 is a schematic diagram of a structure of another enable circuit provided by the present invention, and the first inverter 20 in fig. 10 includes:

a first transistor M1, having a control terminal connected to the second output terminal (Next) of the shift register unit and the fifth terminal 305 of the first block 30, respectively, an input terminal connected to the high voltage VGH, and an output terminal connected to the first node N1;

the second transistor M2 has a control terminal connected to the second output terminal (Next) of the shift register unit and the fifth terminal 305 of the first block 30, respectively, an input terminal connected to the low voltage VGL, and an output terminal connected to the first node N1.

It is understood that the first transistor M1 and the second transistor M2 are double-gate transistors, but may also be single-gate transistors, and this is not specifically limited, where the first transistor M1 is a P-type transistor, the second transistor M2 is an N-type transistor, but may also be an N-type transistor, and the second transistor M2 is a P-type transistor, and this is only schematically illustrated here as long as two clock signals with opposite polarities can be provided for the first module 30 and the second module 40.

In some alternative embodiments, with continued reference to fig. 10, the first module 30 includes:

a third transistor M3, having a control terminal connected to the first node N1 and an input terminal connected to the high voltage VGH;

a fourth transistor M4 having a control terminal connected to the second terminal 502 of the trigger module 50, an input terminal connected to the output terminal of the third transistor M3, and an output terminal connected to the control terminals of the first control module 16 and the second control module 17;

a fifth transistor M5 having a control terminal connected to the second terminal 502 of the trigger module 50 and an output terminal connected to the control terminals of the first control module 16 and the second control module 17;

a sixth transistor M6 has control terminals respectively connected to the first terminal 201 of the first inverter 20 and the second terminal 402 of the second module 40, an input terminal connected to the low potential VGL, and an output terminal connected to an input terminal of the fifth transistor M5.

It is to be understood that the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are double-gate transistors, and may also be single-gate transistors, and this is not limited specifically, where the third transistor M3 and the fourth transistor M4 are P-type transistors, the fifth transistor M5 and the sixth transistor M6 are N-type transistors, and of course, the fifth transistor M5 and the sixth transistor M6 may also be N-type transistors, and the third transistor M3 and the fourth transistor M4 are P-type transistors, and this is only for illustrative purposes.

In some alternative embodiments, the second module 40 comprises:

a seventh transistor M7 having a control terminal connected to the first terminal 201 of the first inverter 20 and the fifth terminal 305 of the first module 30, and an input terminal connected to the high voltage VGH;

an eighth transistor M8 having a control terminal connected to the second terminal 302 of the first module 30, an input terminal connected to the output terminal of the seventh transistor M7, and an output terminal connected to the second terminal of the second inverter 60;

a ninth transistor M9 having a control terminal connected to the second terminal 302 of the first module 30 and an output terminal connected to the second terminal 602 of the second inverter 60 and the output terminal of the eighth transistor M8;

a tenth transistor M10 has a control terminal connected to the first node N1, an input terminal connected to the low potential VGL, and an output terminal connected to an input terminal of the ninth transistor M9.

It is understood that the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are double-gate transistors, and may also be single-gate transistors, and this is not limited specifically, where the seventh transistor M7 and the eighth transistor M8 are P-type transistors, the ninth transistor M9 and the tenth transistor M10 are N-type transistors, and of course, the ninth transistor M9 and the tenth transistor M10 may also be N-type transistors, and the seventh transistor M7 and the eighth transistor M8 are P-type transistors, and this is only for illustrative purposes.

In some alternative embodiments, with continued reference to fig. 10, the triggering module 50 includes:

the eleventh transistor M11 has a control terminal connected to the trigger signal terminal STV, an input terminal connected to the low potential VGL, and an output terminal connected to the sixth terminal 306 of the first block 30 and the first terminal 601 of the second inverter 60.

In some alternative embodiments, with continued reference to fig. 10, the second inverter 60 includes:

a twelfth transistor M12, having a control terminal connected to the sixth terminal 406 of the second module 40 and an input terminal connected to the high voltage VGH;

a thirteenth transistor M13, having a control terminal connected to the sixth terminal 406 of the second module 40, an input terminal connected to the low potential VGL, and an output terminal connected to the second terminal 502 of the trigger module 50 and the output terminal of the twelfth transistor M12.

It is understood that the twelfth transistor M12 and the thirteenth transistor M13 are double-gate transistors, but may also be single-gate transistors, and are not limited herein, where the twelfth transistor M12 is a P-type transistor, the thirteenth transistor M13 is an N-type transistor, and of course, the twelfth transistor M12 is an N-type transistor, and the thirteenth transistor M13 is a P-type transistor, which are only illustrated schematically here.

In some alternative embodiments, referring to fig. 4, 9 and 10, there is also provided a driving method including:

in the first stage t1, a high potential is input to the trigger signal terminal STV, the eleventh transistor M11 is turned on, a low potential VGL is input to the control terminals of the fourth transistor M4 and the fifth transistor M5, and the fourth transistor M4 is turned on; the second output terminal Next of the shift register unit 15 outputs a low voltage, the first transistor is turned on, a high voltage is transmitted to the first node, the first node N1 transmits a high voltage to the third transistor M3, and the third transistor M3 is turned off;

in the first stage t1, the main purpose is to turn on the fourth transistor M4 in advance for the next stage.

In the second stage t2, a low potential is input to the trigger signal terminal STV, and the eleventh transistor M11 is turned off; a second output end Next of the shift register unit 15 outputs a high potential, the second transistor M2 is turned on, a low potential VGL is input to a first node N1, the first node N1 transmits a low potential to the third transistor M3, the third transistor M3 is turned on, the high potential is input to the control ends of the first control module 16 and the second control module 17 and the control end of the ninth transistor M9 through the third transistor M3 and the fourth transistor M4, the first control module 16 is turned on, the voltage of the first voltage signal line comA is input to the peep-proof control electrode 7, and the ninth transistor M9 is turned on;

in the second stage t2, the third transistor M3 and the fourth transistor M4 are both turned on to output a high voltage out, and the transistors in the first control module 16 are N-type transistors, so that the first control module is turned on and the high voltage is input to the peep prevention control electrode 7.

A third stage t3 in which a low potential is input to the trigger signal terminal STV and the eleventh transistor M11 is turned off; the second output terminal Next of the shift register unit 15 outputs a low potential, the first transistor M1 is turned on, the high potential VGH is transmitted to the first node N1, the first node N1 transmits the high potential to the third transistor M3 and the tenth transistor M10 are turned on, the low potential VGL is output to the input terminal of the ninth transistor M9 through the tenth transistor M10 and the ninth transistor M9, the low potential VGL is transmitted to the second terminal 602 of the second inverter 60, the twelfth transistor M12 is turned on, the high potential VGH is transmitted to the output terminal of the twelfth transistor M12, the output terminal of the twelfth transistor M12 inputs the high potential VGH to the control terminal of the fifth transistor M5, and the fifth transistor M5 is turned on;

in the third stage t3, the ninth transistor M9 and the tenth transistor M10 are both turned on, and the twelfth transistor M12 is also turned on, so that the fifth transistor M5 is turned on to prepare for the next frame.

A fourth stage t4 in which a low potential is input to the trigger signal terminal STV and the eleventh transistor M11 is turned off; the second output terminal Next of the shift register unit 15 outputs a high voltage, the sixth transistor M6 is turned on, the low voltage VGL is transmitted to the control terminals of the first control module 16 and the second control module 17 through the sixth transistor M6 and the fifth transistor M5, the second control module 17 is turned on, and the voltage of the first voltage signal line comA is input to the peep-proof control electrode 7.

In the fourth stage t4, the fifth transistor M5 which has been in the on state in the third stage t3 is utilized, so that the low potential VGL is output to out through the sixth transistor M6 and the fifth transistor M5. The transistors in the second control module 17 are P-type transistors, so that the second control module is turned on, and the low potential is input to the peep prevention control electrode 7.

Referring to fig. 11, fig. 11 is a schematic plan view of another display panel provided in the present invention. The first substrate further includes an outer frame 18, along the extending direction of the scan line 11, the outer frame 18 includes a first frame 181 and a second frame 182, which are oppositely disposed, the driving circuit 14 includes a first driving circuit 14a and a second driving circuit 14b, the first driving circuit 14a is located on the first frame 181, the second driving circuit 14b includes the second frame 182, wherein,

the first control module 16 and the second control module 17 of the first drive circuit 14a are electrically connected to the first electrode portion 7a, and the first control module 16 and the second control module 17 of the second drive circuit 14b are electrically connected to the second electrode portion 7 b.

In this embodiment, in the same frame of picture, the polarity of the voltage signal provided to the first electrode portion 7a by the first driving circuit 14a is the same as the polarity of the voltage signal of the odd-numbered pixel electrode 8, and is both high potential, and the polarity of the voltage signal provided to the second electrode portion 7b by the second driving circuit 14b is the same as the polarity of the voltage signal of the even-numbered pixel electrode 8, and is both low potential, so that the polarity of the voltage signal input to the pixel electrode corresponding to the same sub-pixel unit is the same as the polarity of the voltage signal input to the anti-peep control electrode, thereby improving the problem of flicker of the display panel.

Referring to fig. 4 and 12, fig. 12 is a cross-sectional view taken along line B-B' of fig. 4, and the substrate base plate 10 of fig. 12 includes a plurality of connection electrodes 19 on a side thereof adjacent to the second base plate 2, and different connection electrodes 19 are electrically connected to the output terminals of the first control module 16 and the second control module 17, respectively;

the connection electrode 19 is electrically connected to the peep prevention control electrode 7.

In some alternative embodiments, the different connection electrodes 19 are electrically connected to the output terminal of the first control module 16 and the output terminal of the second control module 17 respectively through different metal traces 80, which may also be used in other manners, and is not limited herein. After the connection electrode 19 is electrically connected with the peep-proof control electrode 7, the voltage of the first voltage signal line comA or the second voltage signal line comB can be transmitted to the peep-proof control electrode 7 through the connection electrode 19, so that the polarity of the voltage signal input by the pixel electrode corresponding to the same sub-pixel unit is the same as the polarity of the voltage signal input by the peep-proof control electrode, and the problem of display panel flicker is solved.

In some alternative embodiments, with continued reference to fig. 12, the connection electrode 19 and the privacy control electrode 7 are electrically connected by a conductive gold ball 71.

It should be noted that the frame glue 70 is disposed on the edge of the first substrate 1 and the second substrate 2 when the first substrate 1 and the second substrate 2 are bonded to form a closed space for accommodating the liquid crystal, and at this time, the conductive gold ball 71 is disposed in the frame glue 70 to electrically connect the anti-peeping control electrode 7 and the connection electrode 19.

The electric connection between the peep-proof control electrode 7 and the connecting electrode 19 is realized by arranging the conductive gold ball 71 in the frame glue 70, no wiring is additionally arranged between the first substrate and the second substrate, and the manufacturing process is simple.

In some alternative embodiments, please refer to fig. 13, where fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device 200 provided in this embodiment includes the display panel 100 provided in the above embodiment of the present invention. The embodiment of fig. 13 only takes a mobile phone as an example to describe the display device 200, and it should be understood that the display device 200 provided in the embodiment of the present invention may be other display devices 200 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel 100 in the foregoing embodiments, and the detailed description of the embodiment is not repeated herein.

According to the embodiment, the display panel, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:

the display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are arranged oppositely, the liquid crystal layer is clamped between the first substrate and the second substrate, the first substrate comprises a substrate, a plurality of scanning lines and a plurality of data lines are arranged on the substrate in a crossed and limited mode, the plurality of sub-pixel units are arranged in an array mode, each sub-pixel unit is provided with a pixel electrode, the pixel electrodes are electrically connected with the data lines through switching transistors, and the polarities of voltage signals supplied to the adjacent data lines are opposite; the second substrate comprises a plurality of peep-proof control electrodes extending along the extension direction of the scanning line, and the polarity of a voltage signal input by a pixel electrode corresponding to the same sub-pixel unit is the same as that of a voltage signal input by the peep-proof control electrode; the first substrate further includes a driving circuit including: a shift register unit, wherein a first output end of the shift register unit is electrically connected with the scanning line; the control end of the enabling circuit is connected to the trigger signal end, and the input end of the enabling circuit is connected to the second output end of the shift register unit; the control end of the first control module is connected to the output end of the enabling circuit, the input end of the first control module is connected to the first voltage signal line, and the output end of the first control module is electrically connected with the peep-proof control electrode; the control end of the second control module is connected to the output end of the enabling circuit, the input end of the second control module is connected to the second voltage signal line, and the output end of the second control module is electrically connected with the peep-proof control electrode; the voltage polarity of the first voltage signal line is opposite to the voltage polarity of the second voltage signal line. The pixel driving mode of the display panel adopts column inversion, the voltage of the first voltage signal line and the voltage of the second voltage signal line can be alternately applied to the peep-proof control electrode according to a time sequence through the enabling circuit, the polarity of a voltage signal input by a pixel electrode corresponding to the same sub-pixel unit is the same as that of a voltage signal input by the peep-proof control electrode, and the problem of panel flicker is fundamentally solved.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. The display panel is characterized by comprising a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is clamped between the first substrate and the second substrate;

the first substrate further includes a driving circuit including:

the control end of the second control module is connected to the output end of the enabling circuit, the input end of the second control module is connected to the second voltage signal line, and the output end of the second control module is electrically connected with the peep-proof control electrode;

the peep-proof control electrode comprises first electrode parts and second electrode parts which are arranged in a staggered mode, wherein the orthographic projection of the first electrode parts on the plane of the substrate base plate is overlapped with the orthographic projection of the odd-numbered pixel electrodes on the plane of the substrate base plate, the polarity of a voltage signal provided for the first electrode parts is the same as that of a voltage signal provided for the odd-numbered pixel electrodes, the orthographic projection of the second electrode parts on the plane of the substrate base plate is overlapped with the orthographic projection of the even-numbered pixel electrodes on the plane of the substrate base plate, and the polarity of a voltage signal provided for the second electrode parts is the same as that of a voltage signal provided for the even-numbered pixel electrodes.

2. The display panel of claim 1, wherein the enable circuit comprises:

and a first end of the storage capacitor is connected to a high potential, and a second end of the storage capacitor is connected to the control ends of the first control module and the second control module.

3. The display panel according to claim 2, wherein the first inverter comprises:

a first transistor, a control terminal of which is connected to the second output terminal of the shift register unit and the fifth terminal of the first module, respectively, an input terminal of which is connected to a high potential, and an output terminal of which is connected to the first node;

a second transistor, a control terminal of which is connected to the second output terminal of the shift register unit and the fifth terminal of the first module, respectively, an input terminal of which is connected to a low potential, and an output terminal of which is connected to the first node.

4. The display panel according to claim 2, wherein the first module comprises:

a third transistor having a control terminal connected to the first node and an input terminal connected to a high potential;

a fourth transistor, a control terminal of which is connected to the second terminal of the trigger module, an input terminal of which is connected to the output terminal of the third transistor, and an output terminal of which is connected to the control terminals of the first control module and the second control module;

a fifth transistor, a control end of which is connected to the second end of the trigger module, and an output end of which is connected to the control ends of the first control module and the second control module;

and a control end of the sixth transistor is respectively connected to the first end of the first inverter and the second end of the second module, an input end of the sixth transistor is connected to a low potential, and an output end of the sixth transistor is connected to an input end of the fifth transistor.

5. The display panel according to claim 2, wherein the second module comprises:

a seventh transistor having a control terminal connected to the first terminal of the first inverter and the fifth terminal of the first block, and an input terminal connected to a high potential;

an eighth transistor having a control terminal connected to the second terminal of the first block, an input terminal connected to the output terminal of the seventh transistor, and an output terminal connected to the second terminal of the second inverter;

a ninth transistor having a control terminal connected to the second terminal of the first block and an output terminal connected to the second terminal of the second inverter and the output terminal of the eighth transistor;

a tenth transistor having a control terminal connected to the first node, an input terminal connected to a low potential, and an output terminal connected to an input terminal of the ninth transistor.

6. The display panel according to claim 2, wherein the trigger module comprises:

an eleventh transistor having a control terminal connected to the trigger signal terminal, an input terminal connected to a low potential, and an output terminal connected to the sixth terminal of the first block and the first terminal of the second inverter.

7. The display panel according to claim 2, wherein the second inverter comprises:

a twelfth transistor, a control terminal of which is connected to the sixth terminal of the second module, and an input terminal of which is connected to a high potential;

a thirteenth transistor, a control terminal of which is connected to the sixth terminal of the second module, an input terminal of which is connected to the low potential, and an output terminal of which is connected to the second terminal of the trigger module and the output terminal of the twelfth transistor.

8. The display panel according to claim 1, wherein the first substrate further comprises an outer frame, the outer frame comprises a first frame and a second frame disposed oppositely along an extending direction of the scan line, the driving circuit comprises a first driving circuit and a second driving circuit, the first driving circuit is disposed on the first frame, the second driving circuit comprises a second frame, wherein,

the first drive circuit is electrically connected to the first electrode portion, and the second drive circuit is electrically connected to the second electrode portion.

9. The display panel according to claim 1, wherein a side of the substrate base plate adjacent to the second base plate includes connection electrodes electrically connected to an output terminal of the first control module and an output terminal of the second control module, respectively;

the connecting electrode is electrically connected with the peep-proof control electrode.

10. The display panel according to claim 9, wherein the connection electrode and the peep prevention control electrode are electrically connected by a conductive gold ball.

11. A driving method of a display panel is characterized in that,

the display panel includes:

the first substrate further includes a driving circuit including:

the enabling circuit includes:

the driving method includes:

12. The method for driving a display panel according to claim 11,

the first inverter includes:

a second transistor having a control terminal connected to the second output terminal of the shift register unit and the fifth terminal of the first module, an input terminal connected to a low potential, and an output terminal connected to the first node

The first module comprises:

a sixth transistor having a control terminal connected to the first terminal of the first inverter and the second terminal of the second module, respectively, an input terminal connected to a low potential, and an output terminal connected to an input terminal of the fifth transistor;

the second module includes:

a tenth transistor having a control terminal connected to the first node, an input terminal connected to a low potential, and an output terminal connected to an input terminal of the ninth transistor;

the trigger module includes:

an eleventh transistor having a control terminal connected to the trigger signal terminal, an input terminal connected to a low potential, and an output terminal connected to the sixth terminal of the first block and the first terminal of the second inverter;

the second inverter includes:

a thirteenth transistor, a control terminal of which is connected to the sixth terminal of the second module, an input terminal of which is connected to the low potential, and an output terminal of which is connected to the second terminal of the trigger module and the output terminal of the twelfth transistor;

the driving method includes:

in the first stage, a high potential is input to the trigger signal end, the eleventh transistor is turned on, a low potential is input to the control ends of the fourth transistor and the fifth transistor, and the fourth transistor is turned on; the second output end of the shift register unit outputs a low potential, the first transistor is conducted, the high potential is transmitted to the first node, the first node transmits the high potential to the third transistor, and the third transistor is not conducted;

in the second stage, a low potential is input into the trigger signal end, and the eleventh transistor is turned off; the second output end of the shift register unit outputs high potential, the second transistor is conducted, the low potential is input to a first node, the first node transmits the low potential to the third transistor, the third transistor is conducted, the high potential is input to the control ends of the first control module and the second control module and the control end of the ninth transistor through the third transistor and the fourth transistor, the second control module is conducted, the voltage of the second voltage signal line is input to the peep-proof control electrode, and the ninth transistor is conducted;

in a third stage, a low potential is input to the trigger signal end, and the eleventh transistor is turned off; the second output end of the shift register unit outputs a low potential, the first transistor is conducted, the high potential is transmitted to a first node, the first node transmits the high potential to the third transistor and the tenth transistor to be conducted, the low potential is output to the input end of the ninth transistor through the tenth transistor and the ninth transistor, the low potential is transmitted to the second end of the second inverter, the twelfth transistor is conducted, the high potential is transmitted to the output end of the twelfth transistor, the output end of the twelfth transistor inputs the high potential to the control end of the fifth transistor, and the fifth transistor is conducted;

in the fourth stage, a low potential is input into the trigger signal end, and the eleventh transistor is turned off; the second output end of the shift register unit outputs high potential, the sixth transistor is conducted, the low potential is transmitted to the control ends of the first control module and the second control module through the sixth transistor and the fifth transistor, the first control module is conducted, and the voltage of the first voltage signal line is input to the peep-proof control electrode.

13. A display device comprising the display panel according to any one of claims 1 to 10.