WO2021134753A1

WO2021134753A1 - Display apparatus and driving method therefor

Info

Publication number: WO2021134753A1
Application number: PCT/CN2020/070117
Authority: WO
Inventors: 李蒙; 于洁; 李鹏涛; 王遥遥; 王晓霞; 历伟; 赵铁磊; 秦树林; 黄庭峰; 王春华; 马青
Original assignee: 京东方科技集团股份有限公司; 北京京东方光电科技有限公司
Priority date: 2020-01-02
Filing date: 2020-01-02
Publication date: 2021-07-08
Also published as: CN113439297A; CN113439297B

Abstract

Provided are a display apparatus and a driving method therefor. The display apparatus comprises a polarity control circuit (10), wherein the polarity control circuit (10) is respectively connected to a control signal end (Con1), a first data signal end (D11) for providing a positive-polarity data signal, and a second data signal end (D12) for providing a negative-polarity data signal. Under the control of a control signal, the polarity control circuit (10) can output, to each data line, a data signal with a continuously changing polarity, and at the same moment, the polarity control circuit can output data signals with opposite polarities to data lines connected to two adjacent sub-pixels of the same color in the same row; therefore, when the signal coupling problem is solved, the problem of a polarization phenomenon of liquid crystal molecules is effectively prevented.

Description

Display device and driving method thereof

Technical field

The present disclosure relates to the field of display technology, and in particular to a display device and a driving method thereof.

Background technique

Liquid crystal display (LCD) devices are widely used in the display field due to their advantages such as high resolution and low energy consumption. At present, in order to improve the light transmittance of the backlight source under the premise of ensuring color display, a white (abbreviated: W) sub-pixel can be added to each pixel.

Wherein, each sub-pixel may include a pixel electrode, a common electrode, and liquid crystal molecules. The data voltage can be applied to the pixel electrode and the common voltage can be applied to the common electrode, so that the liquid crystal molecules are deflected under the action of the data voltage and the common voltage, and the light from the backlight source is projected to realize light emission. However, if data voltages of the same polarity are applied to the pixel electrode for a long time, the liquid crystal molecules may be polarized, that is, the deflection speed becomes slower and the amplitude becomes smaller, which affects the display effect.

Summary of the invention

The present disclosure provides a display device and a driving method thereof. The technical solution is as follows:

In one aspect, a display device is provided. The display device includes an array substrate and a polarity control circuit. The array substrate includes a plurality of data lines and a plurality of pixels arranged in an array, and each of the pixels includes a plurality of data lines and a plurality of pixels arranged in an array. Color sub-pixels of different colors and a plurality of white sub-pixels, each of the data lines is connected to a column of sub-pixels for outputting data signals to the column of sub-pixels;

The polarity control circuit is respectively connected to at least one control signal terminal, a plurality of first data signal terminals, a plurality of second data signal terminals and the plurality of data lines, and the first data signal terminal is used to provide a positive polarity The second data signal terminal is used to provide a second data signal of negative polarity;

The polarity control circuit is configured to output the first data signal or the second data signal to each of the data lines in response to the control signal from the control signal terminal, and the polarity control circuit to each The first data signals output by the data lines are from different first data signal terminals, and the second data signals output by the polarity control circuit to each of the data lines are from different second data signal terminals;

Wherein, the polarity of the data signal output by the polarity control circuit to each of the data lines is constantly changing, and at the same moment, the polarity control circuit transfers the same color to two adjacent sub-pixels in the same color. The polarity of the data signal output by the connected data line is reversed.

Optionally, the polarity control circuit is connected to a control signal terminal, the polarity control circuit includes: a plurality of first control sub-circuits and a plurality of second control sub-circuits, the first control sub-circuit and the The total number of the second control sub-circuits is equal to the number of the data lines; the plurality of data lines includes: a plurality of first data lines and a plurality of second data lines, and two adjacent ones of the same color are located in the same line One sub-pixel is connected to one of the first data lines, and the other sub-pixel is connected to one of the second data lines;

Each of the first control sub-circuits is respectively connected to the control signal terminal, one of the first data signal terminal, one of the second data signal terminal and one of the first data line, and each of the first data signal terminals is connected to the first data line. The control sub-circuit is used to output the first data signal to the first data line connected to it when the potential of the control signal is the first potential, and is used to output the first data signal when the potential of the control signal is the second Output the second data signal to the first data line to which it is connected;

Each of the second control sub-circuits is respectively connected to the control signal terminal, one of the first data signal terminal, one of the second data signal terminal, and one of the second data lines, and each of the second The control sub-circuit is used to output the second data signal to the second data line connected to it when the potential of the control signal is the first potential, and is used to output the second data signal to the second data line connected to the control signal when the potential of the control signal is the second Output the first data signal to the second data line connected to it when it is at a potential;

Wherein, among the plurality of first control subcircuits and the plurality of second control subcircuits, any two control subcircuits are connected to different first data lines, the connected second data lines are different, and the connected first data lines are different. The signal terminal is different, and the connected second data signal terminal is different.

Optionally, each of the first control sub-circuits includes: a first positive polarity control unit and a first negative polarity control unit;

The first positive polarity control unit is respectively connected to the control signal terminal, one of the first data signal terminals and one of the first data lines, and the first positive polarity control unit is used for When the electric potential is the first electric potential, output the first data signal to the first data line to which it is connected;

The first negative polarity control unit is connected to the control signal terminal, the second data signal terminal and the first data line respectively, and the first negative polarity control unit is used for When the potential is the second potential, the second data signal is output to the first data line to which it is connected.

Optionally, the first positive polarity control unit includes: a first switching transistor, the first negative polarity control unit includes: a second switching transistor, and the types of the first switching transistor and the second switching transistor are different;

The gate of the first switching transistor and the gate of the second switching transistor are both connected to the control signal terminal;

A first pole of the first switch transistor is connected to one of the first data signal terminals, and a first pole of the second switch transistor is connected to one of the second data signal terminals;

The second pole of the first switch transistor and the second pole of the second switch transistor are both connected to the first data line.

Optionally, each of the second control sub-circuits includes: a second positive polarity control unit and a second negative polarity control unit;

The second positive polarity control unit is connected to the control signal terminal, the first data signal terminal, and the second data line, respectively, and the second positive polarity control unit is used for When the potential is the second potential, output the first data signal to the second data line to which it is connected;

The second negative polarity control unit is respectively connected to the control signal terminal, one of the second data signal terminals and one of the second data lines, and the second negative polarity control unit is used for When the potential is the first potential, the second data signal is output to the second data line connected thereto.

Optionally, the second positive polarity control unit includes: a third switch transistor, the second negative polarity control unit includes: a fourth switch transistor, and the type of the third switch transistor and the fourth switch transistor different;

The gate of the third switch transistor and the gate of the fourth switch transistor are both connected to the control signal terminal;

A first pole of the third switch transistor is connected to one of the first data signal terminals, and a first pole of the fourth switch transistor is connected to one of the second data signal terminals;

The second pole of the third switch transistor and the second pole of the fourth switch transistor are both connected to one second data line.

Optionally, the number of white sub-pixels included in each pixel is the same as the number of color sub-pixels, and the plurality of white sub-pixels and the plurality of color sub-pixels of different colors are alternately arranged along the extending direction of the gate line .

Optionally, each of the pixels includes: three color sub-pixels of different colors and three white sub-pixels, and the three white sub-pixels and the three color sub-pixels of different colors extend along the direction of the gate line Alternate arrangement.

Optionally, the three color sub-pixels of different colors include: a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel;

In every two adjacent rows of pixels, each pixel of a row of pixels includes a plurality of sub-pixels, according to the first color sub-pixel, one white sub-pixel, the second color sub-pixel, one said The white sub-pixel, the third color sub-pixel, and one white sub-pixel are arranged in sequence;

The plurality of sub-pixels included in each of the pixels in another row of pixels, according to one of the white sub-pixel, the third color sub-pixel, one of the white sub-pixels, the first color sub-pixel, and one of the white sub-pixels The sub-pixels and the second color sub-pixels are arranged in order.

Optionally, the 4n+1th data line and the 4n+2th data line in the plurality of data lines are the first data line, and the 4n+3th data line and the 4n+3th data line among the plurality of data lines 4n+4 data lines are the second data lines, and the n is a positive integer greater than or equal to zero.

Optionally, each of the first control sub-circuits includes: a first switch transistor and a second switch transistor, and the first switch transistor and the second switch transistor are of different types; each of the second control sub-circuits The sub-circuit includes: a third switch transistor and a fourth switch transistor, and the third switch transistor and the fourth switch transistor are of different types;

The gate of the first switching transistor, the gate of the second switching transistor, the gate of the third switching transistor, and the gate of the fourth switching transistor are all connected to the control signal terminal;

The second pole of the first switch transistor and the second pole of the second switch transistor are both connected to the first data line;

Optionally, the display device further includes a source drive circuit, the polarity control circuit is integrated in the source drive circuit, and the source drive circuit further includes a source drive chip;

The control signal terminal, the first data signal terminal, and the second data signal terminal of the source drive chip are respectively connected to the polarity control circuit, and the source drive chip is used to control the The signal terminal outputs a control signal to the polarity control circuit, the first data signal is output to the polarity control circuit through the first data signal terminal, and the polarity is output to the polarity through the second data signal terminal. The control circuit outputs the second data signal.

Optionally, the display device further includes: a source drive circuit, and the polarity control circuit is set independently of the source drive circuit;

The control signal terminal, the first data signal terminal, and the second data signal terminal of the source drive circuit are respectively connected to the polarity control circuit, and the source drive circuit is used to control The signal terminal outputs a control signal to the polarity control circuit, the first data signal is output to the polarity control circuit through the first data signal terminal, and the polarity is output to the polarity through the second data signal terminal. The control circuit outputs the second data signal.

Optionally, the display device further includes: a source drive circuit and a timing controller, and the polarity control circuit is set independently of the source drive circuit and the timing controller;

The first data signal terminal and the second data signal terminal of the source drive circuit are respectively connected to the polarity control circuit, and the source drive circuit is used to pass the first data signal terminal to the The polarity control circuit outputs the first data signal, and outputs the second data signal to the polarity control circuit through the second data signal terminal;

The control signal terminal of the timing controller is connected to the polarity control circuit, and the timing controller is configured to output the control signal to the polarity control circuit through the control signal terminal.

Optionally, the polarity control circuit is arranged on the array substrate.

On the other hand, a method for driving a display device is provided for driving the display device as described in the above aspect, and the method includes:

The control signal terminal provides a control signal, the first data signal terminal provides a first data signal of positive polarity, and the second data signal terminal provides a second data signal of negative polarity. The data line outputs the first data signal and the second data signal;

Optionally, the polarity control circuit includes: a plurality of first control sub-circuits and a plurality of second control sub-circuits, the total number of the first control sub-circuits and the second control sub-circuits and the data The number of lines is equal; the plurality of data lines includes: a plurality of first data lines and a plurality of second data lines, two sub-pixels of the same color located in the same row and adjacent to each other, one sub-pixel and one first data line A data line is connected, and another sub-pixel is connected to one of the second data lines;

The control signal terminal provides a control signal, the first data signal terminal provides a positive polarity first data signal, and the second data signal terminal provides a negative polarity second data signal, including:

In the first stage, the control signal terminal provides a control signal of a first potential, one of the first data signal terminals provides a first data signal of positive polarity, and one of the second data signal terminals provides a second data signal of negative polarity. In response to the control signal, one of the first control sub-circuits outputs the first data signal to one of the first data lines connected thereto, and each of the second control sub-circuits responds to the control signal , Outputting the second data signal to one of the second data lines connected thereto;

In the second stage, the control signal terminal provides a control signal of a second potential, one of the first data signal terminals provides a first data signal of positive polarity, and one of the second data signal terminals provides a second data signal of negative polarity. In response to the control signal, one of the first control sub-circuits outputs the second data signal to one of the first data lines connected thereto, and each of the second control sub-circuits responds to the control signal , Outputting the first data signal to one of the second data lines connected thereto.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of an array substrate and a polarity reversal method in the related art;

2 is a schematic diagram of a signal coupling phenomenon provided by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

4 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of a polarity control circuit provided by an embodiment of the present disclosure;

6 is a schematic structural diagram of a first control sub-circuit provided by an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another first control sub-circuit provided by an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a second control sub-circuit provided by an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another second control sub-circuit provided by an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of another polarity control circuit provided by an embodiment of the present disclosure;

FIG. 11 is a schematic structural diagram of yet another polarity control circuit provided by an embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of another display device provided by an embodiment of the present disclosure;

FIG. 13 is a schematic structural diagram of a source driving circuit provided by an embodiment of the present disclosure;

14 is a schematic structural diagram of a source driving circuit, a timing controller, and a polarity control circuit provided by an embodiment of the present disclosure;

FIG. 15 is a flowchart of a driving method of a display device according to an embodiment of the present disclosure;

FIG. 16 is a flowchart of another method for driving a display device according to an embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the following further describes the embodiments of the present disclosure in detail with reference to the accompanying drawings.

The transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. According to the function in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode, or the drain electrode is referred to as the first electrode and the source electrode is referred to as the second electrode. According to the form in the figure, it is stipulated that the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistors used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level. , The N-type switching transistor is turned on when the gate is high, and it is turned off when the gate is low. In addition, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the signal’s potential has two different state quantities, and does not represent the first potential in the full text. The potential or the second potential has a specific value.

In the related art, the polarity of the data signal loaded to each sub-pixel can be controlled to continuously change (also referred to as polarity inversion) to avoid the polarization phenomenon of the liquid crystal molecules. In addition, a source drive circuit (drive integrated circuit, drive IC) can only load data voltages with opposite polarities to two adjacent columns of sub-pixels, that is, it can only cause the data signals loaded to the same row and two adjacent sub-pixels to have opposite polarities. The data signals loaded to the sub-pixels mentioned in the following embodiments of the present disclosure all refer to the data signals (also referred to as data voltages) loaded to the pixel electrodes of the sub-pixels.

When the display device adopts an array substrate with a red, green and blue (abbreviated: RGB) pixel structure, the above-mentioned polarity inversion method can ensure that the polarity of the data signal loaded to two adjacent sub-pixels of the same color in the same row is exactly opposite. However, with the development of display technology, array substrates are no longer limited to the RGB pixel structure. In order to meet the display requirements of various display fields (such as automotive display fields) for low power consumption and high light transmittance of array substrates, array substrates have begun to increase White sub-pixel (W) capable of improving light transmittance. For example, an array substrate with a red, green, blue and white (abbreviated: RGBW) pixel structure is more popular.

However, in conjunction with the RGBW array substrate shown in FIG. 1, when a white sub-pixel W is added to each pixel, if the above-mentioned polarity inversion method is adopted, it will result in the loading of the same color sub-pixels in the same row and adjacent two sub-pixels. The data signal has the same polarity. As shown in Figure 1, the data signals loaded to the two adjacent red sub-pixels R in the same row are all positive (+), and the data signals loaded to the two adjacent green sub-pixels G in the same row are all negative ( -), the data signals of the two adjacent blue sub-pixels B loaded in the same row are all positive (+).

Furthermore, with reference to FIG. 2, when the data signals loaded to the same color sub-pixels in the same row have the same polarity, the common voltage signal loaded to the sub-pixel will fluctuate up and down, which results in loading to the sub-pixel. The common voltage signal produces coupling phenomenon. However, the coupling phenomenon may cause the display screen of the array substrate to have undesirable problems such as flicker and color shift, and the display effect is poor.

For example, when displaying a color picture, if the common voltage signal is coupled to a positive polarity, the data signal loaded to the red sub-pixel and the data signal loaded to the blue sub-pixel are both positive, and the data signal loaded to the green sub-pixel Negative polarity will cause the voltage finally applied to the green sub-pixel to increase, and the screen display may have a greenish color shift.

When displaying a monochrome picture (that is, only a certain color sub-pixel emits light), because the data line still loads data signals to other sub-pixels that do not need to emit light, only the data signals and common voltage signals of other sub-pixels that do not need to emit light are loaded. The voltage difference is exactly 0, so the reason for the color shift phenomenon when displaying a monochrome picture can be directly referred to the reason for displaying a color picture, which will not be repeated here.

It should be noted that, in the embodiments of the present disclosure, two adjacent and same-color sub-pixels in the same row refer to two sub-pixels that are located in the same row and have the same color, and there are no other sub-pixels of the same color between the two sub-pixels. That is, for each sub-pixel, it is located in the same row as the sub-pixel and has the closest distance to the sub-pixel in the pixel row direction, and the sub-pixel with the same color is the sub-pixel of the same color adjacent to the sub-pixel. Since two sub-pixels of the same color that are in the same line and adjacent to each other may also include sub-pixels of other colors, the "in-line and adjacent" in the embodiment of the present disclosure does not mean directly adjacent.

The embodiment of the present disclosure provides a display device, the display device includes a polarity control circuit, and the polarity control circuit can avoid the signal coupling phenomenon on the premise of avoiding the polarization phenomenon of the liquid crystal molecules, thereby preventing the display screen from appearing Undesirable phenomena such as flicker or color cast.

FIG. 3 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 3, the display device may include an array substrate 00 and a polarity control circuit 10, and the polarity control circuit 10 may be used to drive the array substrate 00.

FIG. 4 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. 3 and 4, the array substrate 00 may include: a plurality of data lines S1 (only shown in FIG. 3) and a plurality of pixels P1 arranged in an array, each pixel P1 may include a plurality of color sub-pixels of different colors And multiple white sub-pixels P10.

For example, referring to FIG. 4, it shows that each pixel P1 includes three different color sub-pixels P11, P12, P13 and three white sub-pixels P10. Each data line S1 can be connected to a column of sub-pixels and used to output data signals to the column of sub-pixels. It should be noted that, referring to FIG. 3, in order to drive the pixels to work normally, the array substrate 00 may further include: a plurality of gate lines G1, and each gate line G1 may be connected to a row of pixels and used to output a gate drive to the row of pixels. signal.

In the embodiment of the present disclosure, referring to FIG. 3, the polarity control circuit 10 may be connected to at least one control signal terminal Con1, a plurality of first data signal terminals D11, a plurality of second data signal terminals D12, and a plurality of data lines S1, respectively. connection. The polarity control circuit 10 shown in FIG. 3 is only connected to one control signal terminal Con1.

The first data signal terminal D11 is used to provide a first data signal of positive polarity, and the second data signal terminal D12 is used to provide a second data signal of negative polarity. The polarity control circuit 10 can output the first data signal or the second data signal to each data line S1 in response to the control signal from the control signal terminal Con1.

For example, the polarity control circuit 10 can output the first data signal to each data line S1 when the potential of the control signal is the first potential, and can output the first data signal to each data line S1 when the potential of the control signal is the second potential The second data signal. Optionally, the first potential can be a high potential relative to the second potential. For example, assuming that the potential threshold is K volts, a potential greater than or equal to 90% K can be referred to as the first potential, and a potential less than or equal to 10% K can be referred to as the first potential. It is called the second potential, that is, the first potential is larger than the second potential.

In addition, the polarity of the data signal output by the polarity control circuit 10 to each data line S1 can be continuously changed. And at the same moment, the polarity of the data signal output by the polarity control circuit 10 to the data line S1 connected to two adjacent sub-pixels of the same color can be reversed.

For example, in conjunction with FIG. 4, the polarity control circuit 10 can output a positive polarity to the data line connected to the first sub-pixel and the second sub-pixel in the odd row of pixels when the potential of the control signal is the first potential. The first data signal outputs the second data signal of negative polarity to the data line connected to the third sub-pixel and the fourth sub-pixel in the odd-numbered row of pixels, and to the fifth sub-pixel and the sixth sub-pixel in the odd-numbered row of pixels. The connected data line outputs the first data signal of positive polarity, the second data signal of negative polarity is output to the data lines connected to the seventh sub-pixel and the eighth sub-pixel in the odd-numbered rows of pixels, and so on.

The polarity control circuit 10 can output the second data signal of negative polarity to the data line connected to the first sub-pixel and the second sub-pixel in the even-numbered row of pixels when the potential of the control signal is the second potential. The data line connected to the third sub-pixel and the fourth sub-pixel in a row of pixels outputs the first data signal of positive polarity, and a negative polarity is output to the data line connected to the fifth sub-pixel and the sixth sub-pixel in the even-numbered row of pixels The first data signal of positive polarity is output to the data line connected to the seventh sub-pixel and the eighth sub-pixel in the even-numbered row of pixels, and so on.

It can be seen in conjunction with FIG. 4 that the polarity control circuit 10 can make the polarity of the data signal finally loaded to the color sub-pixel P11 in the same row and adjacent to be opposite, and the polarity of the data signal loaded to the color sub-pixel P12 in the same row and adjacent Conversely, the polarity of the data signal loaded to the adjacent color sub-pixel P13 in the same row is opposite, and the polarity of the data signal loaded to the adjacent white sub-pixel P10 in the same row is also opposite. It effectively and reliably avoids the signal coupling phenomenon, and avoids the polarization phenomenon of the liquid crystal molecules under the premise of ensuring the display effect.

It should be noted that, in order to drive the array substrate 00 to achieve normal color display, the first data signal output by the polarity control circuit 10 to each data line S1 may come from a different first data signal terminal D11 and send to each data line The second data signal output by S1 may come from a different second data signal terminal D12. That is, the number of first data signal terminals D11 may be greater than or equal to the number of data lines S1, and the number of second data signal terminals D12 may be greater than or equal to the number of data lines S1. Of course, in order to save costs and avoid occupying more space in the display device, the number of first data signal terminals D11, the number of second data signal terminals D12, and the number of data lines S1 included in the display device described in the embodiments of the present disclosure may be equal.

In summary, the embodiments of the present disclosure provide a display device, which includes a polarity control circuit. Because the polarity control circuit is under the control of the control signal, it can output a data signal whose polarity changes continuously to each data line, and at the same time, it can send data connected to two adjacent sub-pixels of the same color in the same time. The lines output data signals with opposite polarities. Therefore, under the premise of solving the signal coupling problem, the problem of the polarization phenomenon of the liquid crystal molecules is effectively avoided, and the display effect of the display device is better.

Optionally, FIG. 5 is a schematic structural diagram of a polarity control circuit provided by an embodiment of the present disclosure. As shown in FIG. 5, the polarity control circuit 10 may be connected to a control signal terminal Con1. The polarity control circuit 10 may include: a plurality of first control sub-circuits 101 and a plurality of second control sub-circuits 102. The total number of one control sub-circuit 101 and the second control sub-circuit 102 may be equal to the number of data lines S1. The plurality of data lines S1 may include: a plurality of first data lines S11 and a plurality of second data lines S12. In addition, among two adjacent sub-pixels of the same color in the same row, one sub-pixel is connected to a first data line S11, and the other sub-pixel is connected to a second data line S12.

For example, in conjunction with FIG. 4, taking the first row of pixels as an example, the first color sub-pixel P11 is connected to a first data line S11, and the second color sub-pixel P11 is connected to a second data line S12, not shown The third color sub-pixel P11 is connected to a first data line S11, the unshown fourth color sub-pixel P11 is connected to a second data line S12, and so on.

Referring to FIG. 5, each first control sub-circuit 101 may be respectively connected to a control signal terminal Con1, a first data signal terminal D11, a second data signal terminal D12, and a first data line S11. Each first control sub-circuit 101 can output the first data signal to the first data line S11 connected to it when the potential of the control signal is the first potential, and can output the first data signal to the first data line S11 connected to it when the potential of the control signal is the second potential The connected first data line S11 outputs the second data signal.

Each second control sub-circuit 102 may be respectively connected to the control signal terminal Con1, a first data signal terminal D11, a second data signal terminal D12, and a second data line S12. Each second control sub-circuit 102 can output a second data signal to the second data line S12 connected to it when the potential of the control signal is at the first potential, and can output the second data signal to the second data line S12 connected to it when the potential of the control signal is at the second potential. The connected second data line S12 outputs the first data signal.

Among the multiple first control sub-circuits 101 and the multiple second control sub-circuits 102, any two control sub-circuits connected to the first data line S11 are different, the connected second data line S12 is different, and the connected first data line S11 is different. The signal terminal D11 is different, and the connected second data signal terminal D12 is different. For example, for the first control sub-circuit 101 and the second control sub-circuit 102 shown in FIG. 5, the first data signal terminal D11 connected to the two control sub-circuits is a different data signal terminal, and the second data signal terminal D12 It is also a different data signal terminal.

By making any two control sub-circuits connected to the first data line S11 to be different, the connected second data line S12 to be different, the connected first data signal terminal D11 to be different, and the connected second data signal terminal D12 to be different, it was possible to ensure the output to The data signal of each data line comes from a different data signal terminal, thereby ensuring that the array substrate can realize normal color display.

In addition, through the polarity control circuit and its connection method shown in FIG. 5, since two sub-pixels of the same color are located in the same row and adjacent to each other, one sub-pixel is connected to a first data line S11, and the other sub-pixel is connected to the first data line S11. A second data line S12 is connected, and because when the potential of the control signal is the first potential, the first control sub-circuit 101 can output a positive first data signal to the first data line S11 connected to it, and at the same time, the second The control sub-circuit 102 may output a second data signal of negative polarity to the second data line S12 connected thereto. Therefore, it is realized that at the same time, two adjacent and same color sub-pixels are loaded with data signals of opposite polarities, which avoids the occurrence of signal coupling.

It should be noted that when each control sub-circuit is connected to the same control signal terminal Con1, because the first control sub-circuit 101 and the second control sub-circuit 102 respond to the control signal of the same potential to the data connected to it The line outputs data signals with opposite polarities. Therefore, in order to ensure that data signals with opposite polarities are loaded to two adjacent and in the same color sub-pixels, combining the above connection relationship can be obtained: two data lines connected to two adjacent and in the same color sub-pixels in the same color S1 (including one first data line S11 and one second data line S12), one data line S1 needs to be connected to the first control sub-circuit 101, and the other data line S1 needs to be connected to the second control sub-circuit 102. That is, the two data lines S1 connected to two adjacent sub-pixels of the same color need to be connected to different types of control sub-circuits.

Optionally, multiple first control sub-circuits 101 and multiple second control sub-circuits 102 included in the polarity control circuit 10 may also be connected to multiple control signal terminals Con1. For example, each control sub-circuit is respectively connected to different control signal terminals Con1. When the polarity control circuit 10 is connected to multiple control signal terminals Con1, in order to ensure that the same color sub-pixels in the same row and adjacent to each other have opposite polarities, the potentials of the control signals provided by the multiple control signal terminals Con1 are equal to those of the pixels on the array substrate 00. The arrangement method and the connection relationship between the data line connected to each pixel and each control sub-circuit are related.

Optionally, FIG. 6 is a schematic structural diagram of a first control sub-circuit provided by an embodiment of the present disclosure. As shown in FIG. 6, each first control sub-circuit 101 may include: a first positive polarity control unit 1011 and a first negative polarity control unit 1012.

The first positive polarity control unit 1011 may be connected to the control signal terminal Con1, a data signal terminal D11, and a first data line S11, respectively. The first positive polarity control unit 1011 may output the first data signal of positive polarity to the first data line S11 connected to it when the potential of the control signal is the first potential.

The first negative polarity control unit 1012 can be respectively connected to the control signal terminal Con1, a second data signal terminal D12, and a first data line S11, and the first data line S11 and the first data line S11 connected to the first negative polarity control unit 1012 The first data line S11 connected to a positive polarity control unit 1011 may be the same first data line S11. The first negative polarity control unit 1012 can output a second data signal of negative polarity to the first data line S11 connected to it when the potential of the control signal is the second potential.

Optionally, FIG. 7 is a schematic structural diagram of another first control sub-circuit provided by an embodiment of the present disclosure. As shown in FIG. 7, the first positive polarity control unit 1011 may include: a first switch transistor M1. The first negative polarity control unit 1012 may include: a second switch transistor M2, and the first switch transistor M1 and the second switch transistor M2 have different types.

For example, the first switch transistor M1 can be an N-type transistor, and correspondingly, the second switch transistor M2 can be a P-type transistor. Of course, the first switch transistor M1 can also be a P-type transistor, and correspondingly, the second switch transistor M2 can be an N-type transistor. The N-type switching transistor may be turned on when the potential of the control signal is at a high potential, and the P-type switching transistor may be turned on when the potential of the control signal is at a low potential. Referring to FIG. 7, the embodiment of the present disclosure is described with an example in which the first switch transistor M1 is an N-type transistor and the second switch transistor M2 is a P-type transistor.

Referring to FIG. 7, the gate of the first switching transistor M1 and the gate of the second switching transistor M2 may both be connected to the control signal terminal Con1.

The first pole of the first switch transistor M1 may be connected to a first data signal terminal D11, and the first pole of the second switch transistor M2 may be connected to a second data signal terminal D12.

The second pole of the first switch transistor M1 and the second pole of the second switch transistor M2 may both be connected to one first data line S11. And the first switch transistor M1 and the second switch transistor M2 are connected to the same first data line S11.

Optionally, FIG. 8 is a schematic structural diagram of a second control sub-circuit provided by an embodiment of the present disclosure. As shown in FIG. 8, each second control sub-circuit 102 may include: a second positive polarity control unit 1021 and a second negative polarity control unit 1022.

The second positive polarity control unit 1021 may be respectively connected to the control signal terminal Con1, a first data signal terminal D11, and a second data line S12. The second positive polarity control unit 1012 may output the first data signal of positive polarity to the second data line S12 connected to it when the potential of the control signal is the second potential.

The second negative polarity control unit 1022 can be respectively connected to the control signal terminal Con1, a second data signal terminal D12, and a second data line S12, and the second data line S12 and the first data line S12 connected to the second negative polarity control unit 1022 The second data line S12 connected to the two positive polarity control units 1021 may be the same data line. The second negative polarity control unit 1022 can output a second data signal of negative polarity to the second data line S12 connected to it when the potential of the control signal is the first potential.

Optionally, FIG. 9 is a schematic structural diagram of another second control sub-circuit provided by an embodiment of the present disclosure. As shown in FIG. 9, the second positive polarity control unit 1021 may include: a third switch transistor M3, and the second negative polarity control unit 1022 may include: a fourth switch transistor M4, and the third switch transistor M3 and the fourth switch transistor The type of M4 is different.

In addition, because the second positive polarity control unit 1021 and the first positive polarity control unit 1011 output the first data signal of positive polarity to the data line connected to them in response to control signals of different potentials, the third switching transistor The types of the first switching transistor M1 included in the M3 and the first positive polarity control unit 1011 are also different. In the same way, because the second negative polarity control unit 1022 and the first negative polarity control unit 1012 respond to control signals of different potentials and output the second data signal of negative polarity to the data line connected to them, the fourth switch The transistor M4 and the second switching transistor M2 included in the first negative polarity control unit 1012 are also of different types.

As above, the third switch transistor M3 can be an N-type transistor, and correspondingly, the fourth switch transistor M4 can be a P-type transistor. Of course, the third switch transistor M3 can also be a P-type transistor, and correspondingly, the fourth switch transistor M4 can be an N-type transistor. Referring to FIG. 9, the embodiment of the present disclosure is described by taking as an example the third switch transistor M3 is a P-type transistor and the fourth switch transistor M4 is an N-type transistor.

Referring to FIG. 9, the gate of the third switch transistor M3 and the gate of the fourth switch transistor M4 may both be connected to the control signal terminal Con1.

The first pole of the third switch transistor M3 can be connected to a first data signal terminal D11, and the first pole of the fourth switch transistor M4 can be connected to a second data signal terminal D12.

The second pole of the third switch transistor M3 and the second pole of the fourth switch transistor M4 may both be connected to a second data line S12. And the third switch transistor M3 and the fourth switch transistor M4 are connected to the same second data line S12.

Optionally, in the embodiment of the present disclosure, the number of white sub-pixels and the number of color sub-pixels included in each pixel P1 may be the same, and multiple white sub-pixels and multiple color sub-pixels of different colors may be along the gate line The extending direction of G1 is arranged alternately.

For example, each pixel P1 may include three color sub-pixels of different colors and three white sub-pixels, and the three white sub-pixels and three color sub-pixels of different colors may be alternately arranged along the extending direction of the gate line.

Optionally, referring to FIG. 4, the three color sub-pixels of different colors may include: a first color sub-pixel P11, a second color sub-pixel P12, and a third color sub-pixel P13. And in every two adjacent rows of pixels, each pixel P1 of a row of pixels includes a plurality of sub-pixels according to the first color sub-pixel P11, one white sub-pixel P10, the second color sub-pixel P12, and one white sub-pixel P10. , The third color sub-pixel P13 and one white sub-pixel P10 are arranged in order. Each pixel P1 of another row of pixels includes a plurality of sub-pixels, which may be a white sub-pixel P10, a third-color sub-pixel P13, a white sub-pixel P10, a first-color sub-pixel P11, a white sub-pixel P10, and a second The color sub-pixels P12 are arranged in order.

For example, referring to FIG. 4, it shows that each pixel P1 in an odd row includes a plurality of sub-pixels, according to the first color sub-pixel P11, one white sub-pixel P10, the second color sub-pixel P12, and one white sub-pixel P10, The third color sub-pixel P13 and one white sub-pixel P10 are arranged in order; the multiple sub-pixels included in each pixel P1 in the even-numbered rows shown here are arranged in accordance with a white sub-pixel P10, a third-color sub-pixel P13, and a white sub-pixel. The pixel P10, the first-color sub-pixel P11, one white sub-pixel P10, and the second-color sub-pixel P12 are arranged in order.

By arranging the same number of white sub-pixels as the number of color sub-pixels, and arranging them alternately, it is possible to facilitate the connection of signal lines on the premise of increasing the light transmittance, and to ensure the uniformity of the display. The display of the array substrate of this pixel arrangement is The effect is better.

Optionally, when the pixel arrangement of the array substrate is the arrangement shown in FIG. 4, in order to realize the output of data signals of opposite polarity to the data lines connected to two adjacent sub-pixels of the same color in the same row, The 4n+1th data line S1 (4n+1) and the 4n+2th data line S1 (4n+2) in the plurality of data lines S1 may be the first data line S11, and the first data line S1 among the plurality of data lines S1 The 4n+3 data lines S1 (4n+3) and the 4n+4th data line S1 (4n+4) may be the second data line S12, and n may be a positive integer greater than or equal to zero. That is, multiple first control sub-circuits 101 can be respectively connected to the 4n+1th data line S1(4n+1) and 4n+2th data line S1(4n+2) in the array substrate, and multiple second control sub-circuits 101 The sub-circuit 102 may be respectively connected to the 4n+3th data line S1 (4n+3) and the 4n+4th data line S1 (4n+4) in the array substrate.

For example, suppose a total of m data lines S1 are provided on the array substrate 00, and m is an even number greater than zero. Correspondingly, in order to ensure that the array substrate can display a color image normally, the polarity control circuit 10 may include m/2 first control sub-circuits 101 and m/2 second control sub-circuits 102. In addition, the m/2 first control sub-circuits 101 can be divided into m/4 groups, and each group includes two first control sub-circuits 101, and the m/2 second control sub-circuits 102 can be divided into m/4. Each group includes two second control sub-circuits 102.

Taking the first data line S11 as the 4n+1th data line S1(4n+1) and the 4n+2th data line S1(4n+2), the second data line S12 is the 4n+3th data line S1( 4n+3) and the 4n+4th data line S1 (4n+4) as an example, FIG. 10 shows a schematic structural diagram of another polarity control circuit provided by an embodiment of the present disclosure, and FIG. 11 shows the present disclosure The embodiment provides a schematic structural diagram of still another polarity control circuit. 10 and FIG. 11 both only show a group of first control sub-circuits 101 and a group of second control sub-circuits 102.

It can be seen in combination with FIG. 10 and FIG. 11 that one first control sub-circuit 101 in each group can be connected to a 4n+1th data line S1 (4n+1), and another first control sub-circuit 101 can be connected to a 4n+1th data line S1 (4n+1). The 4n+2th data line S1(4n+2) is connected; one second control sub-circuit 102 in each group can be connected to a 4n+3th data line S1(4n+3), and the other second control sub-circuit The circuit 102 may be connected to a 4n+4th data line S1 (4n+4). Refer to Fig. 10 and Fig. 11 for the connection modes of control sub-circuits of other groups.

For example, suppose that the first switching transistor M1 included in the first positive polarity control unit 1011 of the first control sub-circuit 101 is an N-type transistor, and the second switching transistor M2 included in the first negative polarity control unit 1012 is a P-type transistor. The third switching transistor M3 included in the second positive polarity control unit 1021 of the second control sub-circuit 102 is a P-type transistor, and the fourth switching transistor M4 included in the second negative polarity control unit 1022 is an N-type transistor, and the first potential is relative to The second potential is a high potential.

When the potential of the control signal is the first potential, assuming that n is 0, a first control sub-circuit 101 connected to the first data line can output a positive first data signal to the first data line, and the first data signal is connected to the first data line. The other first control sub-circuit 101 connected to the two data lines can output a positive first data signal to the second data line; at the same time, a second control sub-circuit 102 connected to the third data line can output the first data signal to the second data line. Three data lines output the second data signal of negative polarity, and another second control sub-circuit 102 connected to the fourth data line can output the second data signal of negative polarity to the fourth data line.

Similarly, assuming that n is 1, another first control sub-circuit 101 connected to the fifth data line can output a positive first data signal to the fifth data line. A first control sub-circuit 101 can output a positive first data signal to the sixth data line. Another second control sub-circuit 102 connected to the seventh data line may output a second data signal of negative polarity to the seventh data line, and another second control sub-circuit 102 connected to the eighth data line may be The second data signal of negative polarity is output to the eighth data line. Follow this and so on.

When the potential of the control signal is the second potential, assuming that n is 0, a first control sub-circuit 101 connected to the first data line can output a second data signal of negative polarity to the first data line. The other first control sub-circuit 101 connected to the two data lines can output the second data signal of negative polarity to the second data line; at the same time, the second control sub-circuit 102 connected to the third data line can output the second data signal to the second data line. Three data lines output the first data signal with positive polarity, and another second control sub-circuit 102 connected to the fourth data line can output the first data signal with positive polarity to the fourth data line.

Similarly, assuming that n is 1, another first control sub-circuit 101 connected to the fifth data line can output a second data signal of negative polarity to the fifth data line. A first control sub-circuit 101 can output a second data signal of negative polarity to the sixth data line. Another second control sub-circuit 102 connected to the seventh data line may output a positive first data signal to the seventh data line, and another second control sub-circuit 102 connected to the eighth data line may be The first data signal of positive polarity is output to the eighth data line. Follow this and so on.

In combination with the array substrate shown in FIG. 4 and the above analysis, it can be known that through the polarity control circuit and the connection method shown in FIG. 10 and FIG. 11, on the one hand, 2 dot (dot) polarity reversal can be achieved. That is, for each row of pixels, each pixel is divided into three groups, and each group includes two adjacent sub-pixels, so that the polarity of the data signal loaded to every two adjacent sub-pixels can be the same, and the loading The polarities of the data signals to each adjacent two groups are opposite. That is, starting from the first sub-pixel, the polarity inversion mode can be positive polarity (+), positive polarity (+), negative polarity (-), and negative polarity (-), and so on; alternatively, it can be negative polarity (-), negative polarity (-), positive polarity (+) and positive polarity (+), and so on. On the other hand, if the control signal provided by the control signal terminal Con1 is inverted according to the row clock (that is, when driving every two adjacent rows of pixels, the potential of the control signal provided by the control signal terminal Con1 is different), that is, it can be loaded to the same column and phase The polarities of the data signals of the two adjacent sub-pixels are also exactly opposite, which further ensures that the polarities of the data signals loaded on the same data line can be continuously reversed.

It should be noted that, in the pixel arrangement shown in FIG. 4 and the connection mode of the polarity control circuit shown in FIG. 10 and FIG. 11, it is assumed that the polarity control circuit is connected to a plurality of control signal terminals Con1. The potential of the control signal provided by the signal terminal Con1 at the same time is the same.

Optionally, the pixel arrangement manner provided by the embodiment of the present disclosure is not limited to the solution in FIG. 4. For example, the arrangement of each pixel may be: a color sub-pixel P11, two white sub-pixels P10, a color sub-pixel P12, a color sub-pixel P13, and a white sub-pixel P10.

In this pixel arrangement, in order to ensure that the polarity of the data signals loaded to two adjacent sub-pixels of the same color in the same row is opposite, the 3n+1th data line and the 3n+2th data line of the multiple data lines S1 The data line may be the first data line S11, the 3n+3th data line among the plurality of data lines S1 may be the second data line S12, and n may be a positive integer greater than or equal to 0.

Correspondingly, multiple groups of control sub-circuits may be included, and each group of control sub-circuits may include two first control sub-circuits 101 and one second control sub-circuit 102. For example, if m data lines S1 are provided on the array substrate 00, and m is an odd number greater than 0, the polarity control circuit 10 may include mm/3 first control sub-circuits 101 and m/3 second control sub-circuits. Circuit 102. The mm/3 first control sub-circuits 101 can be divided into m/3 groups, and each group includes two first control sub-circuits 101, and the m/3 second control sub-circuits 102 can be divided into m/3 groups. Each group includes a second control sub-circuit 102.

Moreover, in order to ensure that the display device can display color images normally, in the pixel arrangement and the connection mode of the control sub-circuit, the two groups of control sub-circuits connected to the multiple data lines connected to each pixel need to be different from two different control sub-circuits. The control signal terminal Con1 is connected. At the same moment, the two control signal terminals Con1 need to provide control signals of different potentials. In addition, among the four groups of control sub-circuits connected to multiple data lines connected to every two adjacent pixels, the two adjacent groups of control sub-circuits connected to data lines connected to different pixels are connected to the same control signal terminal Con1 . In addition, two first control sub-circuits 101 and one second control sub-circuit 102 included in each group of control sub-circuits may be connected to the same control signal terminal Con1.

For example, it is also assumed that the first switching transistor M1 included in the first positive polarity control unit 1011 of the first control sub-circuit 101 is an N-type transistor, and the second switching transistor M2 included in the first negative polarity control unit 1012 is a P-type transistor, The third switching transistor M3 included in the second positive polarity control unit 1021 of the second control sub-circuit 102 is a P-type transistor, and the fourth switching transistor M4 included in the second negative polarity control unit 1022 is an N-type transistor, and the first potential is opposite to The second potential is a high potential. In order to drive the first row of pixels, the driving principle under the pixel arrangement mode is described:

When n is 0, it is assumed that the potential of the control signal provided by a control signal terminal Con1 connected to the control sub-circuit connected to the first, second, and third data lines is the first potential. Correspondingly, the potential of the control signal provided by the control sub-circuit connected to the first, second, and third data lines is the first potential. One first control sub-circuit 101 connected to one data line can output a positive first data signal to the first data line, and another first control sub-circuit 101 connected to the second data line can output a positive first data signal to the second data line. The data line outputs the first data signal of positive polarity, and a second control sub-circuit 102 connected to the third data line can output the second data signal of negative polarity to the third data line.

When n is 1, it is assumed that the potential of the control signal provided by the other control signal terminal Con1 connected to the control sub-circuit connected to the 4th, 5th and 6th data lines is the second potential. Correspondingly, and The other first control sub-circuit 101 connected to the fourth data line can output the second data signal of negative polarity to the fourth data line, and the other first control sub-circuit 101 connected to the fifth data line can output the second data signal to the fourth data line. The five data lines output the second data signal of negative polarity, and another second control sub-circuit 102 connected to the sixth data line can output the first data signal of positive polarity to the sixth data line.

When n is 2, it is assumed that the potential of the control signal provided by the other control signal terminal Con1 connected to the control sub-circuit connected to the seventh, eighth, and ninth data lines is the second potential, and correspondingly, and Another first control sub-circuit 101 connected to the seventh data line can output a second data signal of negative polarity to the seventh data line, and another first control sub-circuit 101 connected to the eighth data line can output the second data signal to the seventh data line. The eight data lines output the second data signal of negative polarity, and another second control sub-circuit 102 connected to the ninth data line can output the first data signal of positive polarity to the ninth data line.

When n is 3, it is assumed that the potential of the control signal provided by a control signal terminal Con1 connected to the control sub-circuits connected to the 10th, 11th and 12th data lines is the first potential. Correspondingly, the potential of the control signal provided by the control sub-circuit connected to the 10th, 11th and 12th data lines is the first potential. Another first control sub-circuit 101 connected to the 10 data lines can output a positive first data signal to the 10th data line, and another first control sub-circuit 101 connected to the 11th data line can output the first data signal to the 11th data line. One data line outputs a first data signal with a positive polarity, and another second control sub-circuit 102 connected to the twelfth data line can output a second data signal with a negative polarity to the twelfth data line. Follow this and so on.

According to the above analysis, in the pixel arrangement mode "color sub-pixel P11, two white sub-pixels P10, color sub-pixel P12, color sub-pixel P13, and one white sub-pixel P10", for each row of pixels, it can be Each pixel is divided into two groups, and each group includes three adjacent sub-pixels. Starting from the first sub-pixel, the polarity inversion mode can be positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), negative polarity (-), positive polarity (+) , Negative (-), Negative (-), Positive (+), Positive (+), Positive (+), Negative (-), and so on. In this way, data signals of opposite polarities are loaded to the same color sub-pixels in the same row and adjacent to each other.

It should be noted that the above-mentioned polarity inversion can be realized by the polarity control circuit provided by the embodiments of the present disclosure, and the liquid crystal molecules in any pixel arrangement can be effectively avoided without changing the conventional wiring method and processing algorithm of the array substrate. The polarization phenomenon realizes low-cost mass production of display devices.

Optionally, FIG. 12 is a schematic structural diagram of another display device provided by an embodiment of the present disclosure. As shown in FIG. 12, the display device may further include a source driving circuit 20.

As an optional implementation manner: FIG. 13 is a schematic structural diagram of a source driving circuit provided by an embodiment of the present disclosure. As shown in FIG. 13, the polarity control circuit 10 may be integrated in the source driving circuit 20, and the source driving circuit 20 may also include a source driving chip 201.

Wherein, the control signal terminal Con1, the first data signal terminal D11, and the second data signal terminal D12 of the source driver chip 201 can be connected to the polarity control circuit 10 respectively. The source driver chip 201 can output a control signal to the polarity control circuit 10 through the control signal terminal Con1, can output a positive first data signal to the polarity control circuit 10 through the first data signal terminal D11, and can pass the second data The signal terminal D12 outputs the second data signal of negative polarity to the polarity control circuit 10. By integrating the polarity control circuit 10 in the source driving circuit 20, it is possible to avoid occupying the space of the array substrate 00.

It should be noted that, referring to FIG. 13, the display device may further include a gate driving circuit 40 that may be connected to each gate line G1 and used to provide a gate driving signal to the gate line G1.

As another optional implementation manner, the polarity control circuit 10 can also be set independently of the source drive circuit 20.

Wherein, the control signal terminal Con1, the first data signal terminal D11 and the second data signal terminal D12 of the source driving circuit 20 are respectively connected to the polarity control circuit 10. The source driving circuit 20 may output a control signal to the polarity control circuit 10 through the control signal terminal Con1, output the first data signal to the polarity control circuit 10 through the first data signal terminal D11, and output the first data signal to the polarity control circuit 10 through the second data signal terminal D12. The sexual control circuit 10 outputs the second data signal.

As yet another optional implementation manner, referring to FIG. 14, the display device may further include a timing controller 30. The polarity control circuit 10 can also be set independently of the source drive circuit 20 and the timing controller 30.

The first data signal terminal D11 and the second data signal terminal D12 of the source driving circuit 20 can be connected to the polarity control circuit 10 respectively, and the source driving circuit 20 can be connected to the polarity control circuit 10 through the first data signal terminal D11. The first data signal is output, and the second data signal is output to the polarity control circuit 20 through the second data signal terminal D12.

The control signal terminal Con1 of the timing controller 30 may be connected to the polarity control circuit 10, and the timing controller 30 may output a control signal to the polarity control circuit 10 through the control signal terminal Con1.

Optionally, when the polarity control circuit 10 is arranged independently of the source drive circuit 20 and/or the timing controller 30, the polarity control circuit 10 may be directly arranged on the array substrate 00.

It should be noted that, for the above three optional implementation manners, the first data signal and the second data signal may be provided by a gamma module in the source driver chip 201. And when the polarity control circuit 10 is independently arranged on the array substrate 00, the arrangement of the sub-circuits included in the polarity control circuit 10 can be adjusted according to the change in the polarity of the data signal provided by the source driving circuit 20.

FIG. 15 is a flowchart of a method for driving a display device according to an embodiment of the present disclosure, which may be used to drive the display device shown in FIG. 3. As shown in Figure 15, the method may include:

Step 1501: The control signal terminal provides a control signal, the first data signal terminal provides a first data signal with a positive polarity, and the second data signal terminal provides a second data signal with a negative polarity. The polarity control circuit responds to the control signal to each The data line outputs the first data signal or the second data signal.

Among them, the polarity of the data signal output by the polarity control circuit to each data line is constantly changing, and at the same moment, the polarity control circuit outputs the output signal to the data line connected to the same and adjacent two sub-pixels of the same color. The polarity of the data signal is reversed.

In summary, the embodiments of the present disclosure provide a driving method of a display device. Because the polarity control circuit included in the display device can output a data signal whose polarity is continuously changed to each data line under the control of the control signal, and at the same time, it can transmit data to two adjacent sub-pixels of the same color in the same time. The connected data lines output data signals with opposite polarities. Therefore, under the premise of solving the signal coupling problem, the polarization phenomenon of the liquid crystal molecules is effectively avoided, and the display effect of the display device is better.

Optionally, referring to FIG. 5, the polarity control circuit 10 may include: a plurality of first control sub-circuits 101 and a plurality of second control sub-circuits 102, and the first control sub-circuit 101 and the second control sub-circuit 102 The total number is equal to the number of data lines S1. The plurality of data lines may include: a plurality of first data lines S11 and a plurality of second data lines S12. Among the two adjacent sub-pixels of the same color in the same row, one sub-pixel is connected to a first data line S11, and the other sub-pixel is connected to a second data line S12.

Correspondingly, FIG. 16 is a flowchart of another method for driving a display device according to an embodiment of the present disclosure. As shown in Figure 6, the method may include:

Step 15011. In the first stage, the control signal terminal provides the control signal of the first potential, one first data signal terminal provides the first data signal of positive polarity, and the second data signal terminal provides the second data signal of negative polarity. In response to the control signal, the first control sub-circuit outputs a first data signal to a first data line connected to it, and each second control sub-circuit responds to the control signal to output a first data signal to a second data line connected to it. Two data signals.

Step 15012. In the second stage, the control signal terminal provides the control signal of the second potential, one first data signal terminal provides the first data signal of positive polarity, and the second data signal terminal provides the second data signal of negative polarity. In response to the control signal, the first control sub-circuit outputs a second data signal to a first data line connected to it, and each second control sub-circuit responds to the control signal to output a first data signal to a second data line connected to it. A data signal.

Optionally, the potential of the control signal can be inverted according to the row clock, that is, when driving two adjacent rows of pixels, the potential of the control signal provided by the control signal terminal is different. Correspondingly, the above steps 15011 and 15012, that is, the first stage and the second stage, can be executed alternately according to the line clock. That is, when driving a row of pixels of every two adjacent rows of pixels, the polarity control circuit can output a data signal to each data line connected to it according to the above-mentioned first-stage driving method, and when driving every two adjacent rows of pixels In the case of another row of pixels, the polarity control circuit can output a data signal to each data line connected to it according to the above-mentioned second-stage driving method.

With the pixel arrangement shown in FIG. 4 and the polarity control circuit shown in FIG. 11, the first switch transistor M1 and the fourth switch transistor M4 are N-type transistors, and the second switch transistor M2 and the third switch transistor M3 are P Type transistor, the first potential is higher than the second potential, every two first control sub-circuits 101 are divided into one group, every two second control sub-circuits 102 are divided into one group, and the control signal terminal Con1 is provided According to the line clock, the control signal starts to flip from the first potential, that is, when driving odd rows of pixels, the potential of the control signal provided by the control signal terminal Con1 is the first potential; when driving even rows of pixels, the control signal provided by the control signal terminal Con1 The potential of is the second potential as an example, and the following describes the driving method of the display device provided by the embodiment of the present disclosure:

For example, assuming that the drive starts from the first row, the control signal provided by the control signal terminal Con1 is the first potential. Correspondingly, each group of the first control sub-circuit 101 includes two second switching transistors M2 and each group of the second switching transistors M2. The two third switch transistors M3 included in the second control sub-circuit 102 are turned off. In addition, the two first switching transistors M1 included in each group of the first control sub-circuit 101 and the two fourth switching transistors M4 included in each group of the second control sub-circuit 102 are turned on.

For each group of first control sub-circuits 101, one first switching transistor M1 can output a first data signal of positive polarity to a 4n+1 first data line connected to it, and another first switching transistor M1 can The connected 4n+2th first data line outputs the first data signal of positive polarity. At the same time, for each group of second control sub-circuits 102, a fourth switch transistor M4 can output a negative data signal to a 4n+3 second data line connected to it, and the other fourth switch transistor M4 A data signal of negative polarity can be output to a 4n+4th second data line connected to it.

Then when n is 0, in conjunction with FIG. 4, taking the first row as an example, the data signals loaded to the first sub-pixel P11 and the second sub-pixel P10 are all positive data signals, which are loaded to the third sub-pixel P12 and The data signals of the fourth sub-pixel P10 are all data signals of negative polarity; when n is 1, in conjunction with FIG. 4, the data signals loaded to the fifth sub-pixel P13 and the sixth sub-pixel P10 are all data signals of positive polarity. The data signals loaded to the seventh sub-pixel P11 and the eighth sub-pixel P10 are all negative polarity data signals. And so on. The polarity inversion of the pixels in the other odd rows is the same as that of the first row, and will not be repeated here. This driving stage is the first stage mentioned above.

Similarly, when driving the second row of pixels, the control signal provided by the control signal terminal Con1 is at the second potential. Correspondingly, each group of the first control sub-circuit 101 includes two two second switch transistors M2 and each group of the second switch transistors M2. The two third switch transistors M3 included in the second control sub-circuit 102 are turned on. In addition, the two first switching transistors M1 included in each group of the first control sub-circuit 101 and the two fourth switching transistors M4 included in each group of the second control sub-circuit 102 are turned off.

For each group of first control sub-circuits 101, one second switch transistor M2 can output a second data signal of negative polarity to a 4n+1 first data line connected to it, and another second switch transistor M2 can output a negative polarity second data signal to a 4n+1 first data line connected to it. The connected 4n+2th first data line outputs a second data signal of negative polarity. At the same time, for each group of second control sub-circuits 102, a third switch transistor M3 can output a positive first data signal to a 4n+3 second data line connected to it, and another third switch The transistor M3 can output a first data signal of positive polarity to a 4n+4th second data line connected to it.

Then when n is 0, in conjunction with FIG. 4, taking the second line as an example, the data signals loaded to the first sub-pixel P10 and the second sub-pixel P13 are all negative data signals, and the data signals are loaded to the third sub-pixel P10 and The data signals of the fourth sub-pixel P11 are all positive-polarity data signals; when n is 1, in conjunction with FIG. 4, the data signals loaded to the fifth sub-pixel P10 and the sixth sub-pixel P12 are all negative-polarity data signals, The data signals loaded to the seventh sub-pixel P10 and the eighth sub-pixel P13 are all positive polarity data signals. And so on. The polarity inversion of the pixels in the other even rows is the same as that of the second row, and will not be repeated here. This driving stage is the second stage mentioned above.

In this way, the polarity of the data signal output to each data line is continuously changed, and at the same time, the polarity of the data signal output to the data line connected to two adjacent and adjacent sub-pixels of the same color is realized The opposite scenario. Avoid loading data signals with the same polarity to adjacent color sub-pixels in the same line to cause signal coupling, resulting in display flicker and color shift problems. It should be noted that the control signal provided by the control signal terminal Con1 may also be inverted from the second potential according to the line clock, or inverted once every two lines.

In summary, the embodiments of the present disclosure provide a driving method of a display device. Because the polarity control circuit included in the display device can output a data signal whose polarity is continuously changed to each data line under the control of the control signal, and at the same time, it can transmit to two adjacent sub-pixels of the same color in the same time. The connected data lines output data signals with opposite polarities. Therefore, on the premise of solving the signal coupling problem, the polarization phenomenon of the liquid crystal molecules is effectively avoided, and the display effect of the display device is better.

Optionally, the display device provided by the embodiment of the present disclosure may be any product or component with display function, such as a vehicle-mounted display device, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, etc.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the display device, the circuits included in the display device, and the specific working processes of the sub-circuits included in the circuits described above can be referred to in the foregoing method embodiments. The corresponding process will not be repeated here.

The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection of the present disclosure. Within range.

Claims

A display device, characterized in that, the display device includes: an array substrate and a polarity control circuit, the array substrate includes: a plurality of data lines and a plurality of pixels arranged in an array, each of the pixels includes a plurality of Color sub-pixels of different colors and a plurality of white sub-pixels, each of the data lines is connected to a column of sub-pixels for outputting data signals to the column of sub-pixels;

The polarity control circuit is respectively connected to at least one control signal terminal, a plurality of first data signal terminals, a plurality of second data signal terminals and the plurality of data lines, and the first data signal terminal is used to provide a positive polarity The second data signal terminal is used to provide a second data signal of negative polarity;

The polarity control circuit is configured to output the first data signal or the second data signal to each of the data lines in response to the control signal from the control signal terminal, and the polarity control circuit to each The first data signals output by the data lines are from different first data signal terminals, and the second data signals output by the polarity control circuit to each of the data lines are from different second data signal terminals;

Wherein, the polarity of the data signal output by the polarity control circuit to each of the data lines is constantly changing, and at the same moment, the polarity control circuit transfers the same color to two adjacent sub-pixels in the same color. The polarity of the data signal output by the connected data line is reversed.
The display device according to claim 1, wherein the polarity control circuit is connected to one of the control signal terminals, and the polarity control circuit comprises: a plurality of first control sub-circuits and a plurality of second control circuits. A sub-circuit, the total number of the first control sub-circuit and the second control sub-circuit is equal to the number of the data lines; the plurality of data lines includes: a plurality of first data lines and a plurality of second data Line, two sub-pixels of the same color located in the same row and adjacent to each other, one sub-pixel is connected to one of the first data lines, and the other sub-pixel is connected to one of the second data lines;

Each of the first control sub-circuits is respectively connected to the control signal terminal, one of the first data signal terminal, one of the second data signal terminal and one of the first data line, and each of the first data signal terminals is connected to the first data line. The control sub-circuit is used to output the first data signal to the first data line connected to it when the potential of the control signal is the first potential, and is used to output the first data signal when the potential of the control signal is the second Output the second data signal to the first data line to which it is connected;

Each of the second control sub-circuits is respectively connected to the control signal terminal, one of the first data signal terminal, one of the second data signal terminal, and one of the second data lines, and each of the second The control sub-circuit is used to output the second data signal to the second data line connected to it when the potential of the control signal is the first potential, and is used to output the second data signal to the second data line connected to the control signal when the potential of the control signal is the second Output the first data signal to the second data line connected to it when it is at a potential;

Wherein, among the plurality of first control subcircuits and the plurality of second control subcircuits, any two control subcircuits are connected to different first data lines, the connected second data lines are different, and the connected first data lines are different. The signal terminal is different, and the connected second data signal terminal is different.
3. The display device according to claim 2, wherein each of the first control sub-circuits comprises: a first positive polarity control unit and a first negative polarity control unit;

The first positive polarity control unit is respectively connected to the control signal terminal, one of the first data signal terminals and one of the first data lines, and the first positive polarity control unit is used for When the electric potential is the first electric potential, output the first data signal to the first data line to which it is connected;

The first negative polarity control unit is connected to the control signal terminal, the second data signal terminal and the first data line respectively, and the first negative polarity control unit is used for When the potential is the second potential, the second data signal is output to the first data line to which it is connected.
3. The display device according to claim 3, wherein the first positive polarity control unit comprises: a first switch transistor, the first negative polarity control unit comprises: a second switch transistor, and the first switch The type of the transistor and the second switching transistor are different;

The gate of the first switching transistor and the gate of the second switching transistor are both connected to the control signal terminal;

A first pole of the first switch transistor is connected to one of the first data signal terminals, and a first pole of the second switch transistor is connected to one of the second data signal terminals;

The second pole of the first switch transistor and the second pole of the second switch transistor are both connected to the first data line.
3. The display device according to claim 2, wherein each of the second control sub-circuits comprises: a second positive polarity control unit and a second negative polarity control unit;

The second positive polarity control unit is connected to the control signal terminal, the first data signal terminal, and the second data line, respectively, and the second positive polarity control unit is used for When the potential is the second potential, output the first data signal to the second data line to which it is connected;

The second negative polarity control unit is respectively connected to the control signal terminal, one of the second data signal terminals and one of the second data lines, and the second negative polarity control unit is used for When the potential is the first potential, the second data signal is output to the second data line connected thereto.
7. The display device of claim 5, wherein the second positive polarity control unit comprises: a third switch transistor, the second negative polarity control unit comprises: a fourth switch transistor, and the third switch The type of the transistor and the fourth switch transistor are different;

The gate of the third switch transistor and the gate of the fourth switch transistor are both connected to the control signal terminal;

A first pole of the third switch transistor is connected to one of the first data signal terminals, and a first pole of the fourth switch transistor is connected to one of the second data signal terminals;

The second pole of the third switch transistor and the second pole of the fourth switch transistor are both connected to one second data line.
The display device according to any one of claims 2 to 6, wherein the number of white sub-pixels included in each pixel is the same as the number of color sub-pixels, and the plurality of white sub-pixels and the plurality of white sub-pixels The color sub-pixels of different colors are alternately arranged along the extending direction of the gate line.
The display device according to claim 7, wherein each of the pixels comprises: three color sub-pixels of different colors and three white sub-pixels, and the three white sub-pixels are different from the three different color sub-pixels. Color sub-pixels of colors are alternately arranged along the extending direction of the gate line.
8. The display device of claim 8, wherein the three color sub-pixels of different colors comprise: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;

In every two adjacent rows of pixels, each pixel of a row of pixels includes a plurality of sub-pixels, according to the first color sub-pixel, one white sub-pixel, the second color sub-pixel, one said The white sub-pixel, the third color sub-pixel, and one white sub-pixel are arranged in sequence;

The plurality of sub-pixels included in each of the pixels in another row of pixels, according to one of the white sub-pixel, the third color sub-pixel, one of the white sub-pixels, the first color sub-pixel, and one of the white sub-pixels The sub-pixels and the second color sub-pixels are arranged in order.
9. The display device of claim 9, wherein the 4n+1th data line and the 4n+2th data line in the plurality of data lines are first data lines, and among the plurality of data lines The 4n+3th data line and the 4n+4th data line are the second data lines, and the n is a positive integer greater than or equal to 0.
The display device according to claim 10, wherein each of the first control sub-circuits comprises: a first switch transistor and a second switch transistor, and the first switch transistor and the second switch transistor Different types; each of the second control sub-circuits includes: a third switch transistor and a fourth switch transistor, and the third switch transistor and the fourth switch transistor are of different types;

The gate of the first switching transistor, the gate of the second switching transistor, the gate of the third switching transistor, and the gate of the fourth switching transistor are all connected to the control signal terminal;

A first pole of the first switch transistor is connected to one of the first data signal terminals, and a first pole of the second switch transistor is connected to one of the second data signal terminals;

A first pole of the third switch transistor is connected to one of the first data signal terminals, and a first pole of the fourth switch transistor is connected to one of the second data signal terminals;

The second pole of the first switch transistor and the second pole of the second switch transistor are both connected to the first data line;

The second pole of the third switch transistor and the second pole of the fourth switch transistor are both connected to one second data line.
The display device according to any one of claims 1 to 11, wherein the display device further comprises: a source drive circuit, the polarity control circuit is integrated in the source drive circuit, and the source The driving circuit also includes a source driving chip;

The control signal terminal, the first data signal terminal, and the second data signal terminal of the source drive chip are respectively connected to the polarity control circuit, and the source drive chip is used to control The signal terminal outputs a control signal to the polarity control circuit, the first data signal is output to the polarity control circuit through the first data signal terminal, and the polarity is output to the polarity through the second data signal terminal. The control circuit outputs the second data signal.
The display device according to any one of claims 1 to 12, wherein the display device further comprises: a source drive circuit, and the polarity control circuit is arranged independently of the source drive circuit;

The control signal terminal, the first data signal terminal, and the second data signal terminal of the source drive circuit are respectively connected to the polarity control circuit, and the source drive circuit is used to control The signal terminal outputs a control signal to the polarity control circuit, the first data signal is output to the polarity control circuit through the first data signal terminal, and the polarity is output to the polarity through the second data signal terminal. The control circuit outputs the second data signal.
The display device according to any one of claims 1 to 13, wherein the display device further comprises: a source drive circuit and a timing controller, and the polarity control circuit is independent of the source drive circuit and the timing controller. The timing controller settings;

The first data signal terminal and the second data signal terminal of the source drive circuit are respectively connected to the polarity control circuit, and the source drive circuit is used to pass the first data signal terminal to the The polarity control circuit outputs the first data signal, and outputs the second data signal to the polarity control circuit through the second data signal terminal;

The control signal terminal of the timing controller is connected to the polarity control circuit, and the timing controller is configured to output the control signal to the polarity control circuit through the control signal terminal.
The display device according to claim 13 or 14, wherein the polarity control circuit is disposed on the array substrate.
A driving method of a display device, characterized in that it is used to drive the display device according to any one of claims 1 to 15, and the method comprises:

The control signal terminal provides a control signal, the first data signal terminal provides a positive first data signal, and the second data signal terminal provides a negative second data signal. The polarity control circuit responds to the control signal to each The data line outputs the first data signal or the second data signal;

Wherein, the polarity of the data signal output by the polarity control circuit to each of the data lines is constantly changing, and at the same moment, the polarity control circuit transfers the same color to two adjacent sub-pixels in the same color. The polarity of the data signal output by the connected data line is reversed.
The method according to claim 16, wherein the polarity control circuit comprises: a plurality of first control sub-circuits and a plurality of second control sub-circuits, the first control sub-circuit and the second control sub-circuit The total number of sub-circuits is equal to the number of the data lines; the plurality of data lines includes: a plurality of first data lines and a plurality of second data lines, and two adjacent sub-pixels of the same color are located in the same row, One sub-pixel is connected to one of the first data lines, and the other sub-pixel is connected to one of the second data lines;

The control signal terminal provides a control signal, the first data signal terminal provides a positive polarity first data signal, and the second data signal terminal provides a negative polarity second data signal, including:

In the first stage, the control signal terminal provides a control signal of a first potential, one of the first data signal terminals provides a first data signal of positive polarity, and one of the second data signal terminals provides a second data signal of negative polarity. In response to the control signal, one of the first control sub-circuits outputs the first data signal to one of the first data lines connected thereto, and each of the second control sub-circuits responds to the control signal , Outputting the second data signal to one of the second data lines connected thereto;

In the second stage, the control signal terminal provides a control signal of a second potential, one of the first data signal terminals provides a first data signal of positive polarity, and one of the second data signal terminals provides a second data signal of negative polarity. In response to the control signal, one of the first control sub-circuits outputs the second data signal to one of the first data lines connected thereto, and each of the second control sub-circuits responds to the control signal , Outputting the first data signal to one of the second data lines connected thereto.