CN111766424B - Comprehensive tester with single-port network analysis function and testing method thereof - Google Patents
Comprehensive tester with single-port network analysis function and testing method thereof Download PDFInfo
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Abstract
The invention provides a comprehensive tester with a single-port network analysis function and a test method thereof, wherein the comprehensive tester comprises: the first signal generator is connected to the first combiner, the first signal receiver is connected to the first combiner and the second coupler through a selector switch respectively, the second signal receiver is connected to the second combiner and the first coupler through a selector switch respectively, the second signal generator is connected to the second combiner, the first combiner is connected to the first coupler and the first output port through a selector switch respectively, and the second combiner is connected to the second coupler and the second output port through a selector switch respectively. The invention can simultaneously meet the multi-port test and single-port test functions of the integrated tester.
Description
Technical Field
The invention relates to a comprehensive tester, in particular to a comprehensive tester with a single-port network analysis function, and further relates to a test method using the comprehensive tester with the single-port network analysis function.
Background
Electronic devices of wireless communication type are widely used in consumer, industrial and defense fields, and these wireless devices for transmitting or receiving electromagnetic energy may interfere with each other due to the relationship between frequency and power spectral density, so these devices must comply with various wireless technology standards and specifications. In the design stage of the products, engineers need to ensure that the products meet the existing technical standards and specifications; during the mass production phase, the plant needs to ensure that each product is acceptable and that the proportion of unacceptable product is unacceptable.
The wireless test instrument is called a comprehensive test instrument for short in the application and is used for measuring technical indexes of the equipment, judging whether the tested equipment (called a DUT for short) meets related technical standards and specifications according to a test result and judging whether the tested equipment (called a DUT for short) is a qualified product. Wireless test meters typically include at least one signal generator (VSG) and at least one signal receiver (VSA). Generating a designated signal by the programmable VSG, the signal sequentially passing through the meter port, the cable connected to the meter port, the DUT connected to the cable, and into the receiver of the DUT; the transmitter signal of the DUT is sent to the VSA via the cable to the instrument port and via the instrument port, finally received and analyzed by the VSA, and finally the analysis result is fed back to the test engineer in the form of visualization or data.
The above-mentioned measurement system needs to determine the insertion loss (simply referred to as line loss) of the cable between the DUT and the instrument before performing the measurement, and then compensate the line loss when performing the measurement, so as to ensure that the DUT measurement result is not affected by the cable. The cable used for connection may be a radio frequency cable, or may be a component of a cable connected to a power divider, an attenuator, and the like. The most common method currently used to measure line loss is "return method" by connecting the two ends of the cable to two ports of the instrument, one of which is connected to the VSG and the other to the VSA. A signal of a certain power (e.g., 0 dBm) is generated by the VSG, and the signal enters the VSA through the cable, and the power of the signal read from the VSA to the return signal (e.g., -5 dBm), and the line loss is the difference between the two powers (e.g., -5 dB). One disadvantage of this existing "return method" is that two ports of the cable need to be connected to two ports of the instrument, respectively, while in measuring DUTs, only one port of the cable is connected to the instrument port, which means that additional wiring is required for measuring line loss, increasing test complexity and measuring time, and even in some cases where multiple devices need to be connected to the cable, the movement of the cable is very difficult; another disadvantage of this "return method" is that the mismatch between the instrument and the cable is not taken into account, and the signal is reflected at the connection between the instrument port and the cable due to the mismatch, which affects the measurement accuracy of the line loss.
When the integrated tester is used for measuring the DUT, the connection quality of the DUT is directly related to the production efficiency, and particularly, the device such as a mobile phone, a WLAN router, a module and the like which have very high requirements on throughput and throughput. At present, the industry has no good solution to the problems of calibration error, test error, low through rate and the like caused by poor connection between a DUT and a test fixture, and a technical scheme which can realize both multi-port test and single-port test does not exist.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a comprehensive tester with a single-port network analysis function, which can meet the test function of multiple ports of the comprehensive tester and all the test functions of a single-port VNA, and further provide a test method of the comprehensive tester with the single-port network analysis function.
To this end, the present invention provides a comprehensive tester with a single-port network analysis function, comprising: the first signal generator is connected to the first combiner, the first signal receiver is connected to the first combiner and the second coupler through a selector switch respectively, the second signal receiver is connected to the second combiner and the first coupler through a selector switch respectively, the second signal generator is connected to the second combiner, the first combiner is connected to the first coupler and the first output port through a selector switch respectively, the first coupler is connected to the first output port, the second combiner is connected to the second coupler and the second output port through a selector switch respectively, and the second coupler is connected to the second output port.
A further improvement of the present invention is that the first combiner and the first coupler are connected to the first output port through a changeover switch, and the second combiner and the second coupler are connected to the second output port through a changeover switch.
In a further development of the invention, in FDD mode of operation, the first signal generator and first signal receiver are connected to the first combiner, which is connected to the first output port via a changeover switch; the second signal generator and the second signal receiver are connected to the second combiner, and the second combiner is connected to the second output port through a switch; a first output port is in a VNA operation mode, the first signal generator and the first signal receiver are connected to the first combiner, the first combiner and the second signal receiver are connected to the first coupler, the first coupler is connected to a first output port, and the second signal generator is connected to a second output port through a second combiner; and when the second output port is in a VNA working mode, the first signal generator is connected to the first output port through the first combiner, the second signal receiver and the second signal generator are connected with the second combiner, the first signal receiver and the second combiner are connected with the second coupler, and the second coupler is connected to the second output port.
The invention has the further improvement that in the VNA working mode, calibration is carried out before the reflection coefficient is measured, the calibration process is realized by mathematical modeling, the mathematical modeling process is that ED parameters, ER parameters and ES parameters are obtained by a standard calibration piece, wherein the ED parameters are directional parameters of signals which are sent from a signal generator port and enter a signal receiver port through an isolation arm of a coupler; the ER parameter is a reflection tracking parameter that a signal is sent from a signal generator port and excites a tested device through an instrument port, and the signal is reflected back by the tested device and enters another signal receiver port through a coupling arm of a coupler; the ES parameter is a source matching parameter which is obtained by reflecting the tested equipment to the same port after the signal is sent from the signal generator port to excite the tested equipment and then reaching the output port after being reflected by the internal components of the instrument; and then storing the ED parameters, the ER parameters and the ES parameters on a storage medium of the instrument according to the frequency, and obtaining a test value through calculation.
The invention is further improved by the formula
Calculating a test value Γ m Wherein Γ is the reflection coefficient of the device under test.
The invention has the further improvement that the line loss test process of the comprehensive tester comprises the following steps: connecting cable to the port of the instrument, connecting the other end of the cable to the open-circuit calibration member and the short-circuit calibration member in sequence, measuring the test values at all concerned frequencies, and calculating the test values according to the formula
To calculate the line loss | S 21 L, wherein,
Γ rS and Γ rO Reflection coefficients, S, of cable ends connected to short-circuit and open-circuit calibration members, respectively 11 、S 21 、S 12 And S 22 Respectively the S parameter, gamma, of the cable S And Γ O The reflection coefficients of the short calibration piece and the open calibration piece are respectively.
The invention also provides a testing method of the comprehensive tester with the single-port network analysis function, which adopts the comprehensive tester with the single-port network analysis function and comprises the following steps:
the method comprises the following steps that S1, an open-circuit calibration piece, a short-circuit calibration piece and a load calibration piece are connected to a port of the comprehensive tester in sequence, and calibration operation is completed;
s2, connecting a test cable with a port of the comprehensive tester;
s3, sequentially connecting an open-circuit calibration piece and a short-circuit calibration piece to the other end of the cable to finish line loss measurement;
s4, connecting the tested equipment to the other end of the cable to construct a complete testing environment;
s5, executing connection detection of the tested equipment;
s6, executing the service test of the tested equipment;
and step S7, finishing the test.
A further development of the invention is that the completion of the calibration operation in said step S1 comprises the following sub-steps:
step S101, setting initial parameters;
step S102, connecting the calibration part k to an output port p of the comprehensive tester;
step S103, setting a frequency f i ；
Step S104, generating a frequency f by a signal generator i The single frequency point signal of (2);
step S105, parsing the received signal r (k, i) by the first signal receiver, parsing the received signal m (k, i) by the second signal receiver, where the signal r (k, i) is a reference signal of the kth calibration piece at the ith frequency, the signal m (k, i) is a test signal of the kth calibration piece at the ith frequency, k is a calibration piece index, k =1 represents an open calibration piece, k =2 represents a short calibration piece, k =3 represents a load calibration piece, and i is a frequency index;
step S106, if i = n, executing step S107, otherwise, setting i = i +1, and returning to step S103, wherein n is the number of concerned frequencies;
step S107, if k =3, executing step S108, otherwise, setting k = k +1, and returning to step S102;
step S108, calculating error items of all frequencies of the output port p, and storing the error items on a storage medium;
step S109, if P =2, executing step S110, otherwise, setting P =2, q =1, k =1, i =1 to return to step S102, P is the subscript of the excitation port, P =1 represents the first output port P1, P =2 represents the second output port P2, q is the subscript of the response port, q =1 represents the first output port P1, and q =2 represents the second output port P2;
step S110, the calibration is ended.
A further improvement of the present invention is that the step S3 of completing the line loss measurement comprises the following substeps:
step S301, setting initial parameters;
step S302, connecting a calibration piece k to the other port of the cable p far away from the comprehensive tester;
step S303, setting a frequency f i ；
Step S304, generating a frequency f by a signal generator i The single frequency point signal of (2);
step S305, parsing a received signal r (k, i) by a first signal receiver, parsing a received signal m (k, i) by a second signal receiver, where the signal r (k, i) is a reference signal of a kth calibration piece at an ith frequency, the signal m (k, i) is a test signal of the kth calibration piece at the ith frequency, k is a calibration piece index, k =1 represents an open calibration piece, k =2 represents a short calibration piece, k =3 represents a load calibration piece, and i is a frequency index;
step S306, if i = n, executing step S307, otherwise, setting i = i +1, and returning to step S303, wherein n is the number of concerned frequencies;
step S307, if k =2, executing step S308, otherwise, setting k = k +1, and returning to step S302;
step S308, loading error terms, calculating the line loss of all frequencies of the cable p, and storing line loss values on a storage medium;
step S309, if p =2, executing step S310, otherwise, setting p =2,q =1,k =1,i =1, and returning to step S302;
in step S310, the line loss test is finished.
The invention is further improved in that the connection detection of the device under test is carried out in step S5 at a maximum frequency f n The method comprises the following substeps:
step S501, connecting the tested device to the other port of the cable p far away from the comprehensive tester;
step S502, generating a frequency f by a signal generator n The single frequency point signal of (2);
step S503, analyzing a received signal r through a first signal receiver, and analyzing a received signal m through a second signal receiver, wherein the signal r is a reference signal of a calibration piece, and the signal m is a test signal of the calibration piece;
step S504, loading an error term, and calculating the reflection coefficients of the cable p and the tested equipment;
step S505, judging whether the connection of the tested equipment is abnormal;
and step S506, ending the connection detection of the device to be tested.
Compared with the prior art, the invention has the beneficial effects that: the coupler is added at a proper position in the comprehensive tester for signal separation, and the switch control is realized through the switch, so that one signal generator (VSG) and two signal receivers (VSA) can be combined into a set of single-port Vector Network Analyzer (VNA) through a switch control signal path, and all test functions of the single-port VNA can be met on the basis of meeting the multi-port test function of the comprehensive tester; and the VNA function can be used for accurately measuring the loss, and the DUT connection quality can be quickly and automatically judged and positioned.
Drawings
FIG. 1 is a schematic structural diagram of one embodiment of the present invention;
FIG. 2 is a schematic diagram of an FDD operation mode according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first output port in a VNA operation mode according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second output port in a VNA operation mode according to an embodiment of the present invention;
FIG. 5 is a signal flow diagram of one embodiment of the present invention in a VNA mode of operation;
FIG. 6 is a flow chart of testing of another embodiment of the present invention;
FIG. 7 is a schematic diagram of a calibration sub-process of another embodiment of the present invention;
FIG. 8 is a schematic view of a line loss test sub-flow according to another embodiment of the present invention;
FIG. 9 is a schematic view of a device under test connection test sub-flow according to another embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
In the embodiment, a directional coupler is added at a proper position in the existing comprehensive tester to separate signals, and then one VSG and two VSAs are combined into a set of single-port Vector Network Analyzer (VNA) through a switch control signal path, so that the embodiment meets all testing functions of the comprehensive tester and the single-port VNA; and the VNA function is utilized to accurately measure the loss, and the rapid automatic judgment and problem positioning can be performed on the DUT connection quality.
The general comprehensive tester can meet the requirement that a plurality of ports work simultaneously, namely, a plurality of VSGs and a plurality of VSAs exist. Taking a two-port comprehensive tester as an example, the present embodiment adds two couplers and six switches, so that a signal generated by each port VSG can be coupled to a VSA of another port, and thus the ratio of two paths of signals solved by the two VSAs is the reflection coefficient of the DUT, so that the present invention can test the reflection coefficient as a true single-port VNA. Namely, the measurement error terms caused by the system can be obtained by calibrating the present example through the standard calibration pieces (the standard calibration pieces comprise an open circuit calibration piece, a short circuit calibration piece and a load calibration piece), and the error terms are used for compensating the test result during testing, so that a more accurate DUT reflection coefficient test value is obtained. After the calibration is carried out at the port of the instrument, a connecting cable is connected, and the other end of the cable is respectively connected with two reflection coefficient measurement values of short circuit and open circuit, so that the insertion loss of the cable can be determined. Similarly, in a normal DUT test, the DUT is connected to the other end of the cable, and the measured reflection coefficient includes information on the quality of the DUT connection, and it is possible to detect the quality of the connection between the DUT and the test fixture (jig) by analyzing the test result to determine whether or not the DUT connection is abnormal.
As shown in fig. 1, in this example, a directional coupler (for short, a coupler) is added between two ports and a combiner, and a plurality of switches are added between the combiner and a VSA and between the combiner and the ports, so that the directional coupler can measure a reflection coefficient.
More specifically, as shown in fig. 1, this embodiment provides a comprehensive tester with a single-port network analysis function, including: a first signal generator (VSG 1), a second signal generator (VSG 2), a first signal receiver (VSA 1), a second signal receiver (VSA 2), a first combiner, a second combiner, a first coupler and a second coupler, wherein the first signal generator (VSG 1) is connected to the first combiner, the first signal receiver (VSA 1) is respectively connected to the first combiner and the second coupler through a switch SW3, the second signal receiver (VSA 2) is respectively connected to the second combiner and the first coupler through a switch SW4, the second signal generator (VSG 2) is connected to the second combiner, the first combiner is respectively connected to the first coupler and the first output port P1 through a switch SW1, the first coupler is connected to the first output port P1, the second combiner is respectively connected to the second coupler and the second output port P2 through a switch SW5, and the second coupler is connected to the second output port P2; more specifically, in this example, the first combiner and the first coupler are connected to the first output port P1 through a switch SW2, and the second combiner and the second coupler are connected to the second output port P2 through a switch SW 6.
It should be noted that the present embodiment is described by using a comprehensive tester with two output ports, and in practical applications, the present embodiment is not limited to a comprehensive tester with two output ports, and can be popularized to any comprehensive tester with two or more ports, or a network analysis mode can be formed by two ports, and the method can be implemented by adaptively adding a coupler and a switch.
In the FDD mode of operation, the switch SW1, the switch SW2 and the switch SW3 are on the left, and the switch SW4, the switch SW5 and the switch SW6 are on the right, as shown in fig. 2, that is, the first signal generator (VSG 1) and the first signal receiver (VSA 1) are connected to the first combiner, and the first combiner is connected to the first output port P1 through the switch; the second signal generator (VSG 2) and the second signal receiver (VSA 2) are connected to the second combiner, which is connected to the second output port P2 through a switch. The FDD mode of operation refers to the mode of operation of the integrated tester for the two port network analysis function.
In this example, when the first output port P1 is in the VNA operation mode, the switch SW1, the switch SW2, the switch SW5 and the switch SW6 are turned on to the right, and the switch SW3 and the switch SW4 are turned on to the left, as shown in fig. 3, that is, the first signal generator (VSG 1) and the first signal receiver (VSA 1) are connected to the first combiner, the first combiner and the second signal receiver (VSA 2) are connected to the first coupler, the first coupler is connected to the first output port P1, and the second signal generator (VSG 2) is connected to the second output port P2 through the second combiner. The VNA working mode refers to a comprehensive tester working mode of a single-port network analysis function.
In this example, when the second output port P2 is in the VNA operation mode, the switch SW1, the switch SW2, the switch SW5 and the switch SW6 are turned on to the left, and the switch SW3 and the switch SW4 are turned on to the right, as shown in fig. 4, that is, the first signal generator (VSG 1) is connected to the first output port P1 through the first combiner, the second signal receiver (VSA 2) and the second signal generator (VSG 2) are connected to the second combiner, the first signal receiver (VSA 1) and the second combiner are connected to the second coupler, and the second coupler is connected to the second output port P2.
In the VNA mode, taking port one as an example, a signal generated by the VSG passes through the combiner, a part of the signal directly enters the VSA of port 1 as a reference signal (reference value), another part of the signal passes through the directional coupler, port 1, and the DUT, is reflected by the DUT back to port 1, and then passes through the coupling arm of the directional coupler and enters the VSA of port 2 as a reflected signal (response value), and the ratio of the response value to the reference value is a reflection coefficient.
In this example, in the VNA operating mode, calibration is required before measurement of the reflection coefficient, and the calibration process is implemented by mathematical modeling, as shown in fig. 5, the mathematical modeling process is to obtain an ED parameter, an ER parameter, and an ES parameter through a standard calibration component, where the ED parameter is a directional parameter in which a signal is emitted from a signal generator port and enters a signal receiver port through an isolation arm of a coupler; the ER parameter is a reflection tracking parameter that a signal is sent from a signal generator port and excites a tested device through an instrument port, and the signal is reflected back by the tested device and enters another signal receiver port through a coupling arm of a coupler; the ES parameter is a source matching parameter that after a signal is sent from a signal generator port to excite a tested device, the tested device is reflected to the same port, reflected by internal components of the device and then reaches an output port, in the present example, the system parameters (ED parameter, ER parameter and ES parameter) are obtained by a method of calibrating the present application by using standard calibration components (including an open circuit calibration component, a short circuit calibration component and a load calibration component), then all the parameters are stored on a storage medium (such as a hard disk) of the device according to frequency,
Γ m for test values, represented by real and imaginary parts; m is a response value and is represented by a real part and an imaginary part; r is a reference value, represented by a real and imaginary part, the DUT characteristics (reflection coefficients) and their test values satisfy Γ according to the mathematical model of FIG. 5 in this example m The following relationships:
therefore, this example can calculate the test value by this formula.
This example is given by the formula
Calculating a test value Γ m Wherein Γ is the reflection coefficient of the device under test, and ED, ES and ER are system parameters.
The calibration process of this example is implemented by sequentially measuring a set of standard calibration components of known reflectance (open, short, and load) at a single frequency, and calculating the system parameters (ED, ES, and ER parameters) at that frequency based on the mathematical relationships described above. And repeating the operation to traverse all concerned frequencies, and storing all calculated system parameters in a storage medium for use in line loss test and DUT connection detection.
The line loss test method is that after the calibration process is completed, the cable is connected to the instrument port, the other end of the cable is connected to the open-circuit calibration piece and the short-circuit calibration piece in sequence, the 'test values' under all concerned frequencies are measured, and the line loss can be calculated by using the 'test values' and the system parameters obtained in the calibration process. The calculation method comprises the steps of firstly calculating the reflection coefficient when the cable is connected with an open circuit and a short circuit, and then calculating the insertion loss according to the reflection coefficient.
The reflection coefficients at the time of the open end and the short end of the cable end satisfy the following relation:
and
the line loss test process of the comprehensive tester comprises the following steps: connecting cable to the port of the instrument, connecting the other end of the cable to the open-circuit calibration member and the short-circuit calibration member in sequence, measuring the test values at all concerned frequencies, and calculating the test values according to the formula
To calculate the line loss | S 21 L, wherein,
Γ rS and Γ rO Reflection coefficients, S, of cable ends connected to short-circuit and open-circuit calibration members, respectively 11 、S 21 、S 12 And S 22 Respectively the S parameter, gamma, of the cable S And Γ O Reflection coefficients of the short-circuit calibration element and the open-circuit calibration element, respectively, ideally gamma S ＝-1，Γ O ＝1。
Generally speaking Γ S +Γ O =0, therefore: [ 1-S ] 22 Γ O )(1-S 22 Γ S )|＝|1-(S 22 Γ O ) 2 |≈1。
In the practical process of the embodiment, the calibration process only needs to be carried out once when the instrument leaves a factory, the system parameters are stored in the storage medium, and when a user carries out connector measurement, the user only needs to connect the open-circuit calibration piece and the short-circuit calibration piece at the tail end of the connector respectively to carry out measurement to obtain line loss, so that the problem that another port and a mobile cable are occupied by a 'return method' is avoided. And after the DUT is connected, the reflection coefficient of the cable and DUT combination is measured, and whether the connection of the DUT is normal or not is judged according to the reflection coefficient, so that the influence on the measurement result caused by the DUT connection problem is avoided. In consideration of the influence of temperature drift and the like, the user can also perform calibration once a day or a week to update the system parameters in the storage medium, thereby improving the measurement accuracy.
The DUT connection detection method has two methods, one is that the connection is considered to be good in a certain error range by comparing the DUT reflection coefficient test value (reference reflection coefficient) under the condition of correct connection, and if the difference between the test reflection coefficient and the reference reflection coefficient used for comparison is larger than a certain empirical value, the connection is considered to be in a problem or the quality of the DUT is in a problem. The selection of the reference reflection coefficient and the empirical value of the decision threshold may be statistically determined by a number of test results. Another method is to perform time domain conversion on the measured reflection coefficient (based on the frequency domain), if there is an abnormal large reflection point in the time domain, it indicates that there is a problem in the test, and further, it can be determined whether the problem is a connection problem or a quality problem of the DUT according to the position of the abnormal large reflection on the time domain result.
As shown in fig. 6, this example further provides a testing method for an integrated tester with a single-port network analysis function, which adopts the integrated tester with a single-port network analysis function, and includes the following steps:
step S1, calibrating at an instrument port; sequentially connecting an open-circuit calibration piece, a short-circuit calibration piece and a load calibration piece at the port of the integrated tester, finishing calibration operation according to the prompt of an instrument operation software interface, and automatically calculating and storing error items by software;
s2, connecting a cable; connecting test cables (including near all connections between an instrument and a DUT) to ports of the integrated instrument;
s3, testing line loss; the other end of the cable is sequentially connected with an open-circuit calibration piece and a short-circuit calibration piece, line loss measurement is completed according to the prompt of an instrument software operation interface, and the software can automatically calculate and store the line loss;
step S4, connecting a DUT; connecting the tested device to the other end of the cable to construct a complete testing environment;
s5, DUT connection detection; executing connection detection of the tested equipment according to instrument software, wherein the software can automatically analyze whether the connection is correct, and if the connection detection is successful, executing the step S6; otherwise, disconnecting the DUT and returning to the step S4;
s6, executing the service test of the tested equipment;
and step S7, finishing the test.
As shown in FIG. 7, this example assumes open, short, and load calibration elements numbered calibration 1, calibration element 2, and calibration element 3 in that order, with a frequency of interest f 1 、f 2 、……、f n In this example, the step S1 of completing the calibration operation includes the following sub-steps:
step S101, setting initial parameters, i.e., setting p =1, q =2, k =1, i =1;
step S102, connecting the calibration part k to an output port p of the comprehensive tester;
step S103, setting a frequency f i ；
Step S104, generating a frequency f by a signal generator VSG (p) i The single frequency point signal of (2);
step S105, through the firstThe signal receiver VSA (p) resolves the received signal r (k, i), which is a reference signal of the kth calibration element at the ith frequency, and resolves the received signal m (k, i) by the second signal receiver VSA (q), the signal r (k, i) is a vector signal represented by a complex number and containing amplitude phase information of the reference signal; the signal m (k, i) is a test signal of the kth calibration piece at the ith frequency, and the signal m (k, i) is a vector signal which is represented by a complex number and contains amplitude phase information of the test signal; k is a calibration member subscript, k =1 represents an open calibration member, k =2 represents a short calibration member, and k =3 represents a load calibration member; i is a frequency index, for example, the frequency to be measured is 10 frequency points from 100MHz to 1GHz, then f i =100 i MHz, i =1 for 100mhz, i =2 for 200MHz, \8230; \8230, i =10 for 1GHz;
step S106, if i = n, executing step S107, otherwise, setting i = i +1, and returning to step S103, wherein n is the number of concerned frequencies;
step S107, if k =3, executing step S108, otherwise, setting k = k +1, and returning to step S102;
step S108, calculating error items of all frequencies of the output port p, and storing the error items on a storage medium;
step S109, if P =2, executing step S110, otherwise, setting P =2, q =1, k =1, i =1 to return to step S102, P is the subscript of the excitation port, P =1 represents the first output port P1, P =2 represents the second output port P2, q is the subscript of the response port, q =1 represents the first output port P1, and q =2 represents the second output port P2;
step S110, the calibration is ended.
Assume that a cable connected to port 1 is denoted as cable 1, and a cable connected to port 2 is denoted as cable 2. As shown in fig. 8, the step S3 of completing the line loss measurement in this example includes the following sub-steps:
step S301, setting initial parameters, i.e., setting p =1, q =2, k =1, i =1;
step S302, connecting a calibration piece k to the other port of the cable p far away from the comprehensive tester;
step S303, setting a frequency f i ；
Step S304, generating a frequency f by a signal generator VSG (p) i The single frequency point signal of (a);
step S305, analyzing the received signal r (k, i) by the first signal receiver VSA (p), and analyzing the received signal m (k, i) by the second signal receiver VSA (q), where the signal r (k, i) is a reference signal of the kth calibration element at the ith frequency, and the signal r (k, i) is a vector signal represented by a complex number and contains amplitude phase information of the reference signal; the signal m (k, i) is a test signal of the kth calibration piece at the ith frequency, and the signal m (k, i) is a vector signal which is represented by a complex number and contains the amplitude phase information of the test signal; k is a calibration member subscript, k =1 represents an open calibration member, k =2 represents a short calibration member, and k =3 represents a load calibration member; i is a frequency index, for example, the frequency to be measured is 10 frequency points from 100MHz to 1GHz, then f i =100 i MHz, i =1 for 100mhz, i =2 for 200MHz, \8230; \8230, i =10 for 1GHz;
step S306, if i = n, executing step S307, otherwise, setting i = i +1, and returning to step S303, where n is the number of the concerned frequencies;
step S307, if k =2, executing step S308, otherwise, setting k = k +1, and returning to step S302;
step S308, loading error terms, calculating the line loss of all frequencies of the cable p, and storing line loss values on a storage medium;
step S309, if p =2, executing step S310, otherwise setting p =2, q =1, k =1, i =1, returning to step S302;
in step S310, the line loss test is finished.
As shown in FIG. 9, the connection detection of the device under test is performed at the maximum frequency f in step S5 of the present example n The method comprises the following substeps:
step S501, connecting a tested device DUT to another port of the cable p far away from the comprehensive tester, namely, connecting one end of the cable to the port p of the tester, and connecting the other end of the cable to the DUT, and recording the other port of the tester as q;
step S502, generating a frequency f by a signal generator VSG (p) n The single frequency point signal of (2);
step S503, analyzing a received signal r through a first signal receiver VSA (p), and analyzing a received signal m through a second signal receiver VSA (q), wherein the signal r is a reference signal of a calibration piece, and the signal m is a test signal of the calibration piece;
step S504, loading an error item, and calculating the reflection coefficients of the cable p and the tested equipment;
step S505, judging whether the connection of the tested equipment is abnormal;
step S506, the device under test connection detection ends.
In summary, in this embodiment, a coupler is added at a suitable position in the integrated tester to perform signal separation, and a switch is used to implement switching control, so that one signal generator (VSG) and two signal receivers (VSA) can be combined into a single-port Vector Network Analyzer (VNA) through a switch control signal path, so that the present embodiment can satisfy all test functions of the single-port VNA on the basis of satisfying the multi-port test function of the integrated tester; and the VNA function can be used for accurately measuring the line loss, and the DUT connection quality can be quickly and automatically judged and positioned.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A comprehensive tester with a single-port network analysis function is characterized by comprising: the first signal generator is connected to the first combiner, the first signal receiver is connected to the first combiner and the second coupler through a change-over switch SW3, the second signal receiver is connected to the second combiner and the first coupler through a change-over switch SW4, the second signal generator is connected to the second combiner, the first combiner is connected to the first coupler and the first output port through a change-over switch SW1, the first coupler is connected to the first output port, the second combiner is connected to the second coupler and the second output port through a change-over switch SW5, and the second coupler is connected to the second output port.
2. The integrated meter with single-port network analysis function according to claim 1, wherein the first combiner and the first coupler are connected to the first output port through a switch SW2, and the second combiner and the second coupler are connected to the second output port through a switch SW 6.
3. The integrated meter with single-port network analysis function according to claim 1 or 2, wherein in FDD mode of operation, the first signal generator and first signal receiver are connected to the first combiner, and the first combiner is connected to the first output port through a switch SW 1; the second signal generator and the second signal receiver are connected to the second combiner, and the second combiner is connected to the second output port through a switch SW 5; a first output port is in a VNA operation mode, the first signal generator and the first signal receiver are connected to the first combiner, the first combiner and the second signal receiver are connected to the first coupler, the first coupler is connected to a first output port, and the second signal generator is connected to a second output port through a second combiner; when the second output port is in a VNA operating mode, the first signal generator is connected to the first output port through the first combiner, the second signal receiver and the second signal generator are connected to the second combiner, the first signal receiver and the second combiner are connected to the second coupler, and the second coupler is connected to the second output port.
4. The integrated meter with single-port network analysis function according to claim 3, wherein in the VNA operation mode, calibration is performed before the reflection coefficient is measured, and the calibration process is implemented by mathematical modeling, wherein the mathematical modeling process is to obtain ED parameters, ER parameters and ES parameters by a standard calibration component, wherein the ED parameters are directional parameters of signals transmitted from the signal generator port and entering the signal receiver port through the isolation arm of the coupler; the ER parameter is a reflection tracking parameter that a signal is sent from a signal generator port and excites a tested device through an instrument port, and the signal is reflected back by the tested device and enters another signal receiver port through a coupling arm of a coupler; the ES parameter is a source matching parameter which is obtained by reflecting the tested equipment to the same port after the signal is sent from the signal generator port to excite the tested equipment and then reaching the output port after being reflected by the internal components of the instrument; and then storing the ED parameters, the ER parameters and the ES parameters on a storage medium of the instrument according to the frequency, and obtaining a test value through calculation.
5. The integrated tester with single-port network analysis function of claim 4, wherein the formula is defined by
Calculating a test value gamma m Wherein Γ is the reflection coefficient of the device under test.
6. The integrated tester with single-port network analysis function of claim 4, wherein the line loss test process of the integrated tester is as follows: connecting cable to the port of the instrument, connecting the other end of the cable to the open-circuit calibration member and the short-circuit calibration member in sequence, measuring the test values at all concerned frequencies, and calculating the test values according to the formula
To calculate the line loss | S 21 L, wherein,
Γ rS and Γ rO Reflection coefficients, S, of the cable ends connected to the short-circuit calibration member and the open-circuit calibration member, respectively 11 、S 21 、S 12 And S 22 Respectively the S parameter, gamma, of the cable S And Γ O The reflection coefficients of the short calibration piece and the open calibration piece, respectively.
7. A method for testing a comprehensive tester with a single-port network analysis function, which is characterized by using the comprehensive tester with the single-port network analysis function according to any one of claims 1 to 6, and comprising the following steps:
the method comprises the following steps that S1, an open-circuit calibration piece, a short-circuit calibration piece and a load calibration piece are connected to a port of the comprehensive tester in sequence, and calibration operation is completed;
s2, connecting a test cable with a port of the comprehensive tester;
s3, sequentially connecting an open-circuit calibration piece and a short-circuit calibration piece at the other end of the cable to complete line loss measurement;
s4, connecting the tested equipment to the other end of the cable to construct a complete testing environment;
s5, executing connection detection of the tested equipment;
s6, executing the service test of the tested equipment;
and step S7, finishing the test.
8. The method for testing the comprehensive tester with the single-port network analysis function according to claim 7, wherein the step S1 of completing the calibration operation comprises the following sub-steps:
step S101, setting initial parameters;
step S102, connecting the calibration part k to an output port p of the comprehensive tester;
step S103, setting a frequency f i ；
Step S104, generating a frequency f by a signal generator i The single frequency point signal of (2);
step S105, parsing, by the first signal receiver, a received signal r (k, i), parsing, by the second signal receiver, a received signal m (k, i), where the signal r (k, i) is a reference signal of the kth calibration piece at the ith frequency, the signal m (k, i) is a test signal of the kth calibration piece at the ith frequency, k is a calibration piece index, k =1 represents an open calibration piece, k =2 represents a short calibration piece, k =3 represents a load calibration piece, and i is a frequency index;
step S106, if i = n, executing step S107, otherwise, setting i = i +1, and returning to step S103, wherein n is the number of concerned frequencies;
step S107, if k =3, executing step S108, otherwise, setting k = k +1, and returning to step S102;
step S108, calculating error items of all frequencies of the output port p, and storing the error items on a storage medium;
step S109, if P =2, executing step S110, otherwise, setting P =2, q =1, k =1, i =1 to return to step S102, P is the subscript of the excitation port, P =1 represents the first output port P1, P =2 represents the second output port P2, q is the subscript of the response port, q =1 represents the first output port P1, and q =2 represents the second output port P2;
step S110, the calibration is ended.
9. The method for testing the comprehensive tester with the single-port network analysis function according to claim 7, wherein the step S3 of completing the line loss measurement comprises the following substeps:
step S301, setting initial parameters;
step S302, connecting a calibration piece k to the other port of the cable p far away from the comprehensive tester;
step S303, setting a frequency f i ；
Step S304, generating a frequency f by a signal generator i The single frequency point signal of (a);
step S305, parsing a received signal r (k, i) by a first signal receiver, parsing a received signal m (k, i) by a second signal receiver, where the signal r (k, i) is a reference signal of a kth calibration piece at an ith frequency, the signal m (k, i) is a test signal of the kth calibration piece at the ith frequency, k is a calibration piece index, k =1 represents an open calibration piece, k =2 represents a short calibration piece, k =3 represents a load calibration piece, and i is a frequency index;
step S306, if i = n, executing step S307, otherwise, setting i = i +1, and returning to step S303, where n is the number of the concerned frequencies;
step S307, if k =2, executing step S308, otherwise, setting k = k +1, and returning to step S302;
step S308, loading error terms, calculating the line loss of all frequencies of the cable p, and storing line loss values on a storage medium;
step S309, if p =2, executing step S310, otherwise, setting p =2,q =1,k =1,i =1, and returning to step S302;
in step S310, the line loss test is finished.
10. The method as claimed in claim 7, wherein the step S5 is performed to detect the connection of the device under test at a maximum frequency f n The method comprises the following substeps:
step S501, connecting the tested device to the other port of the cable p far away from the comprehensive tester;
step S502, generating a frequency f by a signal generator n The single frequency point signal of (2);
step S503, analyzing a received signal r through a first signal receiver, and analyzing a received signal m through a second signal receiver, wherein the signal r is a reference signal of a calibration piece, and the signal m is a test signal of the calibration piece;
step S504, loading an error term, and calculating the reflection coefficients of the cable p and the tested equipment;
step S505, judging whether the connection of the tested equipment is abnormal;
and step S506, ending the connection detection of the device to be tested.
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| CN115426283A (en) * | 2022-08-22 | 2022-12-02 | 上海龙旗科技股份有限公司 | Line loss testing method and equipment for comprehensive tester |
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