CN1117662A - Power supply voltage converting circuit of semiconductor integrated circuit - Google Patents
Power supply voltage converting circuit of semiconductor integrated circuit Download PDFInfo
- Publication number
- CN1117662A CN1117662A CN95106891A CN95106891A CN1117662A CN 1117662 A CN1117662 A CN 1117662A CN 95106891 A CN95106891 A CN 95106891A CN 95106891 A CN95106891 A CN 95106891A CN 1117662 A CN1117662 A CN 1117662A
- Authority
- CN
- China
- Prior art keywords
- voltage
- ditch mos
- mos transistor
- transistor
- internal power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Abstract
A power voltage conversion circuit includes a difference amplifying unit, a drive element and a control unit. A first input node and a second input node of the difference amplifying unit are respectively added with a reference voltage and an internal power voltage. The difference amplifying unit amplifies the difference between the reference voltage and the internal power voltage. The difference amplifying unit does not act during a precharging working period but acts during an active working period. The drive element provides a current to the internal power voltage from an external power voltage according to the output of the difference amplifying unit. The control unit simultaneously controls the drive element when the difference amplifying unit enters into active working.
Description
The present invention relates to semiconductor integrated circuit, more particularly, a kind ofly produce the supply voltage translation circuit of optimized internal power source voltage in order to outer power voltage is transformed into internal power source voltage thereby relate to.
In recent years, along with the high-speed increase of semiconductor memory density, the volume of each element such as transistor was more and more littler, thereby the ratio that the is reduced to ground of builtin voltage capacity and each component size is descended.Therefore, in order to make the stable and reliable operation of internal circuit, must reduce the operational voltage level that offers each element.For reaching this purpose, supply voltage normally is contained in the semiconductor memory, and the outer power voltage that memory is outer is transformed into internal power source voltage.
Fig. 1 is general supply voltage translation circuit, and Fig. 2 is the oscillogram of the supply voltage translation circuit characteristic of key diagram 1.
The supply voltage translation circuit of Fig. 1 is normally made the electric current mirror.As everyone knows, sort circuit is as differential amplifier.Reference voltage V REF and internal power source voltage INT.VCC are arranged in the circuit of Fig. 1, and discharge transistor 18 is pressed the situation discharge of node N4, thereby has amplified the difference voltage between reference voltage V REF and the internal power source voltage INT.VCC.
Following circuit element in the structure of Fig. 1, is equipped with: p ditch MOS transistor 4 and 8, its each source electrode is added with outer power voltage EXT.VCC respectively, and its each grid is connected to each other together; N ditch MOS transistor 14, its drain electrode connects the drain electrode of P ditch MOS transistor 4, and its grid is by reference power supply voltage VRET control, n ditch MOS transistor 16, its drain electrode links together with the drain and gate of p ditch MOS transistor 8, and its grid meets internal power source voltage INT.VCC; N ditch MOS transistor 18, its drain electrode links together with n ditch MOS transistor 14 and 16 source electrode separately, its source ground current potential VSS, its grid meets node N4; P ditch M0S driver transistor 12, its source electrode meets outer power voltage EXT.VCC, and its drain electrode meets internal power source voltage INT.VCC, and its grid connects the drain electrode of p ditch MOS transistor 4; P ditch MOS transistor 2, its source electrode meets outer power voltage EXT.VCC, and its drain electrode connects the drain electrode of p ditch MOS transistor 4, and its grid meets control clock A; P ditch MOS transistor 10, the drain electrode of a termination p ditch MOS transistor 4 of its raceway groove, the drain electrode of another termination p ditch MOS transistor 8 of raceway groove, its grid meets control clock A; P ditch MOS transistor 20, its source electrode meets internal power source voltage INT.VCC, and its drain electrode meets node N4, and its grid meets control clock B; N ditch MOS transistor 22, its drain electrode meets node N4, and its source ground current potential VSS, its grid meet control clock B.
The electric current that p ditch MOS driver transistor 12 provides for the input node of internal power source voltage is proportional to the electric current of the n ditch MOS transistor 14 that is added with reference voltage V REF of flowing through, so that make internal power source voltage keep constant level.At this moment each p ditch MOS transistor 2,4,8,10 and 12 has the back door of a presentation surface as the position of its raceway groove, and this back door meets outer power voltage EXT.VCC respectively.The back door of p ditch MOS transistor 20 meets internal power source voltage INT.VCC.
Referring now to Fig. 1 and Fig. 2, the working condition of general supply voltage translation circuit is described.
At first, under the precharge operating state, when control clock A when logic " height " attitude changes logic " low " attitude over to, 2 conductings of p ditch MOS transistor.So node N1 is pre-charged to the level of outer power voltage EXT.VCC.In addition, control clock A also makes 10 conductings of p ditch MOS transistor, thereby node N1 and N2 are pre-charged to outer power voltage EXT.VCC.Meanwhile, when control clock B when logic " low " attitude changes logic " height " attitude over to, the conducting of n ditch MOS transistor.At this moment, node N4 is in the level of earth potential VSS, thereby n ditch MOS transistor 18 ends, thus make by p ditch MOS transistor 4,8 and 10 and n ditch MOS transistor 14,16 and 18 differential amplifiers of forming because discharge process because of n ditch MOS transistor 18 inoperative by stopping.In addition, connect the p ditch MOS driver transistor of the node N1 that is pre-charged to outer power voltage EXT.VCC, its gate source voltage Vgs becomes 0 volt, thereby p ditch MOS driver transistor 12 is ended.So cut off being connected between outer power voltage EXT.VCC and the internal power source voltage INT.VCC fully, thereby do not formed current path.
Secondly, when actual motion, when control clock A when logic " low " attitude changes logic " height " attitude over to, p ditch MOS transistor 2 and 10 is ended.Meanwhile, when control clock B when logic " height " attitude changes logic " low " attitude over to, 20 conductings of p ditch MOS transistor, n ditch MOS transistor 22 is ended, thereby makes 18 conductings of n ditch MOS transistor.So differential amplifier is owing to the discharge process that 18 conductings of n ditch MOS transistor cause works.
Above-mentioned supply voltage translation circuit is in order to amplify the difference voltage between reference voltage V REF and the internal power source voltage INT.VCC.In other words, when the level of internal power source voltage INT.VCC is lower than the level of reference voltage V REF, the magnitude of current that flows through n ditch MOS transistor 14 more and more increases, the voltage of importing simultaneously on p ditch MOS driver transistor 12 grids descends, thereby p ditch MOS driver transistor 12 is ended, and the current potential of internal power source voltage INT.VCC raises.
On the other hand, when the level of internal power source voltage INT.VCC is higher than reference voltage V REF, the magnitude of current that flows through n ditch MOS transistor 16 more and more increases, the voltage of importing simultaneously on p ditch MOS driver transistor 12 grids is more and more higher, thereby make 12 conductings of p ditch MOS driver transistor, suppressed the rising of internal power source voltage INT.VCC.
Supply voltage translation circuit shown in Fig. 1 constitutes the electric current mirror, and the magnitude of current of promptly flow through p ditch MOS transistor 4 and 8 is almost kept constant.As shown in Fig. 1 and Fig. 2, after the precharge phase of supply voltage translation circuit finishes, if the input of control clock A and B is worked differential amplifying stage, the node N1 that then connects p ditch MOS driver transistor 12 grids goes up the voltage that forms and drops to voltage EXT.VCC-VEp (wherein VEp is the threshold voltage of pMOS transistor 4) from outer power voltage EXT.VCC.At this moment, outer power voltage EXT.VCC reaches the needed time of voltage EXT.VCC-VEp has very big influence to the stability of internal power source voltage INT.VCC, this be because the moment of p ditch MOS driver transistor 12 conductings because of due to the delay of the above-mentioned time that reaches postpones.The formation time of so just having incured loss through delay current path between outer power voltage EXT.VCC and the internal power source voltage INT.VCC.
Before externally the current path between supply voltage EXT.VCC and the internal power source voltage INT.VCC forms, because of the interference of its clutter descends, then prolonged the recovery time of internal power source voltage INT.VCC as if internal power source voltage INT.VCC.So just internal power source voltage can not be maintained desired level.
Therefore, after beginning cycle of activity, 12 conductings as early as possible of p ditch MOS driver transistor, and internal power source voltage INT.VCC should be transferred to desired predetermined voltage level.As shown in Figure 2, in general supply voltage translation circuit, after beginning and pass through about 50 nanoseconds cycle of activity, because 12 conductings of p ditch MOS driver transistor will be transferred to internal power source voltage INT.VCC the voltage level of pre-provisioning request and have any problem.
Therefore the purpose of this invention is to provide a kind of when outer power voltage is transformed into internal power source voltage the very fast supply voltage translation circuit of internal power source voltage being transferred to the voltage level of pre-provisioning request.
Another object of the present invention provides and a kind ofly can prevent the supply voltage translation circuit that internal power source voltage descends because of the interference of its clutter by the current path between quick formation outer power voltage and the internal power source voltage.
For reaching above and other objects of the present invention, a kind of outer power voltage is transformed into the supply voltage translation circuit that internal power source voltage produces the semiconductor integrated circuit formula of optimized internal power source voltage thereby the invention provides.Described supply voltage translation circuit comprises: a difference amplifying unit, on its first input node and the second input node, be added with reference voltage and internal power source voltage respectively, it amplifies is difference between reference voltage and the internal power source voltage, this difference amplifying unit is inoperative at the precharge duration of work, works during real work; An exciting unit, the electric current of outer power voltage is offered internal power source voltage according to the output of difference amplifying unit, with a control unit, controlling exciting unit when differential motion amplifying unit enters active operation forward the pumping signal of exciting unit is pre-charged to preset level between precharge phase after simultaneously.
Fig. 1 is the circuit diagram of general supply voltage translation circuit.
Fig. 2 is the waveform of key diagram 1 supply voltage translation circuit characteristic.
Fig. 3 is the circuit diagram of supply voltage translation circuit of the present invention.
Fig. 4 is the waveform of key diagram 3 supply voltage translation circuit characteristics.
Fig. 3 is the circuit diagram of the supply voltage translation circuit made by the present invention.Following elements in the structure of Fig. 3, is equipped with: p ditch MOS transistor 4 and 8, its source electrode is added with outer power voltage EXT.VCC respectively, and its each grid links together; The drain and gate that n ditch MOS transistor 14, its drain electrode connect p ditch MOS transistor 8 links together, and its grid meets internal power source voltage INT.VCC; N ditch MOS transistor 18, its drain electrode links together with n ditch MOS transistor 14 and 16 source electrode separately, its source ground current potential VSS, its grid meets node N4; P ditch MOS driver transistor 12, its source electrode meets outer power voltage EXT.VCC, and its drain electrode meets internal power source voltage IVT.VCC, and its grid connects the drain electrode of p ditch MOS transistor 4; The p ditch MOS transistor 24 that diode connects, its source electrode meets outer power voltage EXT.VCC, and its grid connects its drain electrode; P ditch MOS transistor 2, its source electrode connect the drain electrode of p ditch MOS transistor 24, and its grid meets control clock A; P ditch MOS transistor 10, the drain electrode of a termination p ditch MOS transistor 4 of its raceway groove, the drain electrode of another termination p ditch MOS transistor 8 of raceway groove, its grid meets control clock A; P ditch MOS transistor 20, its source electrode meets internal power source voltage INT.VCC, and its drain electrode meets node N4, and its grid meets control clock B; N ditch MOS transistor 22, its drain electrode meets node N4, and its source ground current potential VSS, its grid meet control clock B.
P ditch MOS transistor 24 that the diode that the frame of broken lines of Fig. 3 is got up connects and p ditch MOS transistor 24 and P ditch MOS transistor 2 are being controlled p ditch MOS transistor 12 as control circuit.The p ditch MOS transistor 24 usefulness outer power voltage EXT.VCC that diode connects are transferred to voltage EXT.VCC-Vtp as supply voltage with the grid voltage of p ditch MOS driver transistor 12 in pre-charge process.P ditch MOS transistor 2 is connected between the drain electrode and P ditch MOS driver transistor 12 of p ditch MOS transistor 24, and p ditch MOS driver transistor 12 ends during active operation in the conducting of precharge duration of work.
At this moment, each p ditch MOS transistor 4,8,10,12 and 24 all has a back door, and presentation surface is as a position of its raceway groove, and this back door meets outer power voltage EXT.VCC.The back door of p ditch MOS transistor meets internal power source voltage INT.VCC.The source electrode and the back door of p ditch MOS transistor are joined to one another.
Referring now to the working condition of Fig. 3 and Fig. 4 explanation by the supply voltage translation circuit of body plan of the present invention.
At first, in the precharge duty cycle, when control clock A when logic " height " attitude changes logic " low " attitude over to, 2 conductings of p ditch MOS transistor.So node N1 just is pre-charged to the current potential of voltage EXT.VCC-Vtp, this voltage obtains by making outer power voltage reduce a threshold voltage Vtp.In addition, control clock A also makes the 10 also conductings of p ditch MOS transistor, so node N1 and N2 are pre-charged to externally fed voltage EXt.VCC.
On the other hand, when control clock B when logic " low " attitude changes logic " height " attitude over to, 22 conductings of n ditch MOS transistor.So node N4 is in earth potential VSS, and n ditch MOS transistor 18 is ended.Like this and since discharge process because of n ditch MOS transistor by stopping, thereby by p ditch MOS transistor 4,8 and 10 and the differential amplifier that constitutes of n ditch MOS transistor 14,16 and 18 fail.
Secondly, during active operation, when control clock A when logic " low " attitude changes logic " height " attitude over to, p ditch MOS transistor 2 and 19 is ended.On the other hand, when control clock B when logic " height " attitude changes logic " low " attitude over to, 20 conductings of p ditch MOS transistor, n ditch MOS transistor 22 is ended, thereby makes 18 conductings of n ditch MOS transistor.Like this, cause because discharge process is conducting because of n ditch MOS transistor 18, thereby differential amplifier works.
Referring to Fig. 3 and Fig. 4.After precharge phase in the supply voltage translation circuit finishes, the node N1 that is connected with the grid of p ditch MOS driver transistor 12, the voltage that forms on it is added on the voltage EXT.VCC-Vtp in advance in advance.Therefore, if the input of control clock A and B is worked differential amplifier, 12 conductings at once of p ditch MOS driver transistor, thereby suppressed the decline of the internal power source voltage during the initialization cycle.In other words, the gate node of p ditch MOS driver transistor 12 is pre-charged to voltage EXT.VCC-Vtp during precharge cycle, and be lower than under the situation of reference voltage V REF at the level of internal power source voltage INT.VCC, p ditch MOS driver transistor 12 is because of detecting the conducting fast of above-mentioned situation.
In traditional supply voltage translation circuit, after the active operation cycle begins, can eliminate internal power source voltage because of the decline problem that its interference that lasts the clutter that produces about 50 nanoseconds causes, make the circuit smooth working.
Among Fig. 3,, then have little leakage current and flow to internal power source voltage INT.VCC from the outer power voltage EXT.VCC p ditch MOS transistor 2 of flowing through if the threshold voltage of p ditch MOS transistor 24 and p ditch MOS driver transistor 12 is equal to each other.If leakage current then may improve the level of internal power source voltage INT.VCC at the precharge duration of work greater than the standby current that consumes in the internal power source voltage node.Address this problem, the threshold voltage of preferably getting p ditch MOS transistor 24 is lower than the relevant voltage of p ditch MOS driver transistor 24.In addition, because the drain-source voltage Vds of P ditch MOS transistor 24 only is its threshold voltage, thereby the threshold voltage of p ditch MOS transistor 24 can be obtained the relevant voltage that is lower than another normal p ditch MOS transistor.The method of control p ditch MOS transistor 24 and p ditch MOS driver transistor 12 is distinguished the injection component of each transistorized channel length or ion.When regulating each transistorized channel length, if the weak point of the ditch channel ratio p ditch MOS driver transistor 12 of p ditch MOS transistor 24, then the threshold voltage of p ditch MOS transistor 24 is lower than the threshold voltage of p channel MOS driver transistor 12.In addition, can adopt mask process to regulate the injection rate of ion.
In sum, supply voltage translation circuit of the present invention can be transferred to internal power source voltage the voltage level of pre-provisioning request apace in the process that outer power voltage is transformed into internal power source voltage.In addition, supply voltage translation circuit of the present invention can externally form current path between supply voltage and the internal power source voltage rapidly, thus prevent internal power source voltage not its clutter of reason interference and descend.
Claims (4)
1. the supply voltage translation circuit of a semiconductor integrated circuit formula can be with outer power voltage, thereby produces optimized internal power source voltage, it is characterized in that it comprises:
Differential amplifying device, be added with reference voltage and described internal power source voltage respectively on its first input node and on the second input node, this device amplifies is difference voltage between described reference voltage and the described internal power source voltage, described differential amplifying device is inoperative at the precharge duration of work, works during active operation;
Exciting bank provides electric current for described internal power source voltage in order to the output according to described differential amplifying device from described outer power voltage; With
Control device, in order in the pumping signal of described exciting bank after the precharge duration of work is pre-charged to predetermined level, when described differential amplifying device enters active operation forward, control described exciting bank simultaneously.
2. supply voltage translation circuit as claimed in claim 1 is characterized in that, described control device comprises:
The first transistor, with described outer power voltage as supply voltage; With
Transistor seconds is connected between described the first transistor and the described exciting bank, and described transistor seconds ends during active operation in the conducting of precharge duration of work.
3. described supply voltage translation circuit as claimed in claim 2 is characterized in that, described the first transistor is the p ditch MOS transistor that diode connects, and described transistor seconds and described exciting bank are respectively p ditch MOS transistor.
4. supply voltage translation circuit as claimed in claim 3 is characterized in that, the threshold voltage of described the first transistor is lower than the threshold voltage of described exciting bank.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR14755/94 | 1994-06-25 | ||
| KR1019940014755A KR0124048B1 (en) | 1994-06-25 | 1994-06-25 | External power transform circuit in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1117662A true CN1117662A (en) | 1996-02-28 |
Family
ID=19386343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95106891A Pending CN1117662A (en) | 1994-06-25 | 1995-06-23 | Power supply voltage converting circuit of semiconductor integrated circuit |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH0863246A (en) |
| KR (1) | KR0124048B1 (en) |
| CN (1) | CN1117662A (en) |
| TW (1) | TW268164B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100389373C (en) * | 2004-12-25 | 2008-05-21 | 鸿富锦精密工业（深圳）有限公司 | Circuit for generating source voltage |
| CN100412754C (en) * | 2004-12-17 | 2008-08-20 | 鸿富锦精密工业（深圳）有限公司 | Power supply voltage generation circuit |
| CN104900263A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Memory and driving circuit thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100734299B1 (en) * | 2005-12-30 | 2007-07-02 | 삼성전자주식회사 | Current sense internal voltage generating circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3286869B2 (en) * | 1993-02-15 | 2002-05-27 | 三菱電機株式会社 | Internal power supply potential generation circuit |
-
1994
- 1994-06-25 KR KR1019940014755A patent/KR0124048B1/en not_active IP Right Cessation
-
1995
- 1995-06-23 CN CN95106891A patent/CN1117662A/en active Pending
- 1995-06-23 TW TW084106477A patent/TW268164B/en not_active IP Right Cessation
- 1995-06-26 JP JP7158834A patent/JPH0863246A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100412754C (en) * | 2004-12-17 | 2008-08-20 | 鸿富锦精密工业（深圳）有限公司 | Power supply voltage generation circuit |
| CN100389373C (en) * | 2004-12-25 | 2008-05-21 | 鸿富锦精密工业（深圳）有限公司 | Circuit for generating source voltage |
| CN104900263A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Memory and driving circuit thereof |
| CN104900263B (en) * | 2014-03-04 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | Memory and its driving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960002755A (en) | 1996-01-26 |
| TW268164B (en) | 1996-01-11 |
| JPH0863246A (en) | 1996-03-08 |
| KR0124048B1 (en) | 1997-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930009148B1 (en) | Source voltage control circuit | |
| CN102394629B (en) | Semiconductor device | |
| KR100210716B1 (en) | Semiconductor integrated circuit | |
| US6157586A (en) | Memory device having potential control for increasing the operating margin at the start of a sensing cycle | |
| US7468624B2 (en) | Step-down power supply | |
| KR100643620B1 (en) | Memory device | |
| JP3661163B2 (en) | Sense amplifier control circuit for semiconductor memory device | |
| EP0066974B1 (en) | Improved substrate bias generator | |
| US5594695A (en) | Sense amplifier control circuit of semiconductor memory device | |
| KR20000041576A (en) | Data sensing amplifier | |
| US4649289A (en) | Circuit for maintaining the potential of a node of a MOS dynamic circuit | |
| US6650153B2 (en) | Generator circuit for voltage ramps and corresponding voltage generation method | |
| CN1117662A (en) | Power supply voltage converting circuit of semiconductor integrated circuit | |
| KR920000962B1 (en) | Circuit controlling out-put voltage level of data in semiconductor | |
| US6885222B2 (en) | High-speed cross-coupled sense amplifier | |
| US6009032A (en) | High-speed cell-sensing unit for a semiconductor memory device | |
| WO2002003391A3 (en) | Method and low-power circuits used to generate accurate boosted wordline voltage for flash memory core cells in read mode | |
| KR0140124B1 (en) | The detecting circuit of power supply voltage for semiconductor memory device | |
| US4972097A (en) | Reference voltage generating circuit in semiconductor device | |
| KR970063248A (en) | Semiconductor memory, device, signal amplification method, method and apparatus for controlling pass transistor | |
| JPH08205526A (en) | Internal booster circuit in semiconductor integrated circuit | |
| JPH0684357A (en) | Semiconductor device | |
| US20020079955A1 (en) | Circuit for generating internal power voltage in a semiconductor device | |
| KR100247219B1 (en) | Sensing circuit of bitline | |
| JPH0656719B2 (en) | Semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| AD01 | Patent right deemed abandoned | ||
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |