CN111757035B

CN111757035B - Receiving circuit and signal processing method for high-resolution multimedia interface

Info

Publication number: CN111757035B
Application number: CN201910251185.6A
Authority: CN
Inventors: 黄冠嘉; 吴宗轩; 郑景升
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-03-29
Filing date: 2019-03-29
Publication date: 2022-08-23
Anticipated expiration: 2039-03-29
Also published as: CN111757035A

Abstract

The invention discloses a receiving circuit and a signal processing method for a high-resolution multimedia interface, wherein the receiving circuit comprises a first channel, a second channel, a third channel and a control circuit, wherein the first channel is used for carrying out decoding operation and descrambling operation on a first data stream to generate data of a first color corresponding to an image frame, the second channel is used for carrying out decoding operation and descrambling operation on a second data stream to generate data of a second color corresponding to the image frame, and the third channel is used for carrying out decoding operation and descrambling operation on the third data stream to generate data of a third color corresponding to the image frame. In operation of the receiving circuit, the control circuit determines to turn on or off at least a portion of the functions in the first channel, the second channel, or the third channel based on whether the image frame is displayed on a display panel.

Description

Receiving circuit and signal processing method for high-resolution multimedia interface

Technical Field

The present invention relates to a High Definition Multimedia Interface (HDMI), and more particularly, to a receiver circuit conforming to the HDMI and HDCP (High-Definition Digital Content Protection) specifications.

Background

Under the current HDMI and HDCP protocols, when the display device is connected to multiple signal sources through HDMI connectors and a user switches between different signal sources, several seconds may be required for switching from the source to the display screen on the screen, which causes inconvenience to the user. Therefore, in order to enable a user to quickly display on a screen when switching between different signal sources, each HDMI connection needs to be continuously connected to a corresponding signal source and maintain HDCP authentication, however, this method of maintaining HDCP authentication will greatly increase power consumption.

Disclosure of Invention

Therefore, an objective of the present invention is to provide a receiving circuit and a related signal processing method for HDMI, which can greatly reduce the power consumption of the display device while maintaining HDCP authentication to avoid display latency, so as to solve the problems in the prior art.

In one embodiment of the present invention, a receiving circuit applied to a high-resolution multimedia interface is disclosed, which includes a first channel for performing a decoding operation and a de-scrambling operation on a first data stream to generate first data corresponding to first color information of an image frame, a second channel for performing a decoding operation and a de-scrambling operation on a second data stream to generate second data corresponding to second color information of the image frame, and a control circuit for performing a decoding operation and a de-scrambling operation on a third data stream to generate third data corresponding to third color information of the image frame. In operation of the receiving circuit, the control circuit is configured to determine whether to turn on or turn off at least a portion of the functions in the first channel, the second channel, or the third channel according to whether the image frame is played on a display panel.

In another embodiment of the present invention, a signal processing method applied to a high-resolution multimedia interface is disclosed, which comprises the following steps: providing a first channel to perform decoding operation and de-scrambling operation on a first data stream to generate first data corresponding to first color information of an image frame; providing a second channel for performing decoding operation and descrambling operation on a second data stream to generate second data corresponding to second color information of the image frame; providing a third channel for performing decoding operation and de-scrambling operation on a third data stream to generate third data corresponding to third color information of the image frame; and determining to turn on or turn off at least a part of functions in the first channel, the second channel or the third channel according to whether the image frame is played on a display panel.

Drawings

Fig. 1 is a schematic diagram of a display device according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a receiving circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of the second channel and/or the third channel operating in a normal mode and a sleep mode.

Fig. 4 is a timing diagram of the clock signal, the vertical synchronization signal, and the encryption status signal.

Fig. 5 is a flowchart illustrating a signal processing method applied to an HDMI according to an embodiment of the present invention.

Description of the symbols

100 display device

102. 104 electronic device

110_1 ~ 110_ N HDMI connector

130 processing circuit

140 display panel

120_1 to 120_ N, 200 receiving circuit

200 receiving circuit

202 channel deviation calculation circuit

204 control circuit

206 timer

210 first channel

212. 222, 232 decoder

214. 224, 234 descrambler

216. 226, 236 key calculation circuit

220 second channel

230 third channel

300 frame of image

500 to 506 steps

CLK clock signal

enc _ en/enc _ dis encryption status signal

H _ sync horizontal synchronization signal

V _ sync vertical synchronization signal

Vc1, Vc2 and Vc3 control signals

V1 first data stream

V2 second data stream

V3 third data stream

V1 ', V2 ', V3 ' decoded data

D1 first data

D2 second data

D3 third data

Detailed Description

Fig. 1 is a schematic diagram of a display device 100 according to an embodiment of the invention. As shown in FIG. 1, the display device 100 includes a plurality of HDMI connectors 110_1 to 110_ N, a plurality of receiving circuits 120_1 to 120_ N, a processing circuit 130 and a display panel 140. In the embodiment, the HDMI connectors 110_1 to 110_ N of the display device 100 can be used to connect a plurality of signal sources, such as the illustrated

electronic devices

102 and 104, for receiving audio/video data from the

electronic devices

102 and 104 for playback. In the embodiment, the video data received by the display device 100 complies with the HDCP protocol, that is, the video data can be played smoothly after passing the key authentication.

In the embodiment shown in fig. 1, the display device 100 can be connected to a plurality of signal sources, such as the two illustrated

electronic devices

102 and 104, simultaneously, and the user can control the display device 100 to select the image data from one of the electronic devices for playing. For example, when the user selects to play the video data from the electronic device 102, the receiving circuit 120_1 receives the video data from the electronic device 102 through the HDMI connector 110_1, and after performing the decoding, descrambling (descrambling) and key authentication processes, transmits the video data to the processing circuit 130 for subsequent processing and then plays the video data on the display panel. In addition, in order to enable the display panel 140 to rapidly play the image data from the electronic device 104 when the user switches to the electronic device 104, even if the image data of the electronic device 104 is not currently played, the receiving circuit 120_2 still continuously receives the image data from the electronic device 104, and performs decoding, descrambling and key authentication.

As described above, since the display device 100 performs decoding, descrambling and key authentication on all received video signals, the receiving circuits 120_1 to 120_ N have large power consumption, and thus, the present embodiment provides a circuit and a method capable of reducing the power consumption of the receiving circuits 120_1 to 120_ N.

FIG. 2 is a schematic diagram of a receiving circuit 200 according to an embodiment of the invention, wherein the receiving circuit 200 may be any one of the receiving circuits 120_1 to 120_ N shown in FIG. 1. In fig. 2, the receiving circuit 200 includes a first channel 210, a second channel 220, a third channel 230, a channel offset calculating circuit 202, a control circuit 204 and a timer 206, wherein the first channel 210 includes a decoder 212, a descrambler 214 and a key calculating circuit 216, the second channel 220 includes a decoder 222, a descrambler 224 and a key calculating circuit 226, and the third channel 230 includes a decoder 232, a descrambler 234 and a key calculating circuit 236.

In the present embodiment, the receiving circuit 200 operates differently according to whether the received image data is played on the display panel 140. Specifically, when the video data received by the receiving circuit 200 is played on the display panel 140, the control circuit 204 generates the control signals Vc1, Vc2, and Vc3 to enable the first channel 210, the second channel 220, and the third channel 230 to be in an enabled state, and at this time, the decoder 212 in the first channel 210 decodes a first data stream V1 to generate decoded data V1 ', and the descrambler 214 descrambles the decoded data V1' to generate first data D1 corresponding to first color information of an image frame, and the key calculating circuit 216 calculates a corresponding frame key and line key according to the first data D1 to perform key authentication; similarly, the decoder 222 in the second channel 220 decodes a second data stream V2 to generate decoded data V2 ', the descrambler 224 descrambles the decoded data V2' to generate second data D2 corresponding to the second color information of the image frame, and the key calculation circuit 226 calculates corresponding frame keys and line keys according to the second data D2 for key authentication; the decoder 232 in the third channel 230 decodes a third data stream V3 to generate decoded data V3 ', the descrambler 234 descrambles the decoded data V3' to generate third data D3 corresponding to third color information of the image frame, and the key calculation circuit 236 calculates corresponding frame keys and line keys according to the third data D3 for key authentication. In this embodiment, the first color information of the image frame corresponding to the first channel 210 may be any one of red, green, blue, etc., the second color information of the image frame corresponding to the second channel 220 may be another one of red, green, blue, and the third color information of the image frame corresponding to the third channel 230 may be yet another one of red, green, blue. It should be noted that, since the frame key and the line key can be calculated and authenticated by referring to the specification of the HDCP protocol, and the frame key and the line key are not essential to the present invention, the details thereof are not repeated. It should be understood that the color information of the image frame corresponding to the above channels is red, green, blue, etc., however, it may also be Y, U, V information in the YUV color model, or Y, Cb, Cr information in the YCbCr color model, and the invention is not limited thereto. In an embodiment of the invention, the first color information of the image frame corresponding to the first channel 210 may be Y, U, V, the second color information of the image frame corresponding to the second channel 220 may be Y, U, V, and the third color information component of the image frame corresponding to the third channel 230 may be Y, U, V. In another embodiment of the present invention, the first color information, the second color information, and the third color information of the image frame corresponding to the first channel 210, the second channel 220, and the third channel 230 may also be color information such as Y, Cb, Cr, etc. in the YCbCr color model.

On the other hand, when the video data received by the receiving circuit 200 is not played on the display panel 140, in order to reduce the power consumption of the receiving circuit 200, the control circuit 204 continuously turns on one of the first channel 210, the second channel 220 and the third channel 230, and the other two channels are selectively turned on or off to achieve the power saving function. For convenience of the following description, the following embodiments use the control circuit 204 to continuously turn on the first channel 210 for illustration. In detail, the control circuit 204 generates the control signal Vc1 to turn on the first channel 210, i.e., the decoder 212 continuously decodes the first data stream V1 to generate the decoded data V1 ', and the descrambler 214 descrambles the decoded data V1' to generate the first data D1 corresponding to the first color information of an image frame. It should be noted that, in the HDMI 2.0 specification, since the first data stream V1 from the transmitting end is operated with adding scrambling, and the first data stream V1 includes a plurality of unperturbed control bits (unperturbed control bits) to calculate a unperturbed alignment information for the unperturber 214 to perform the descrambling offset calculation (i.e., when to start the unperturbing operation using a seed of the unperturber 214), and the occurrence time points of the plurality of unperturbed control bits are not fixed, it is ensured that the first channel 210 can receive the plurality of unperturbed control bits to perform the unperturbing operation by continuously turning on the decoder 212 and the unperturber 214.

On the other hand, regarding the second channel 220 and the third channel 230, the control circuit 204 can determine the time point for turning on/off the second channel 220 and/or the third channel 230 according to the time information provided by the timer 206. Specifically, the control circuit 204 may continuously turn on the second channel 220 and/or the third channel 230 before the vertical synchronization signal V _ sync of the next image frame occurs according to the time information provided by the timer 206 (i.e., in the normal mode), for example, the control circuit 206 may turn on the second channel 220 and/or the third channel 230 when the decoder 212 outputs the last rows of active display data (active display data) of the image frame 300, so that the channel deviation calculating circuit 202 may calculate a channel deviation information among the first channel 210, the second channel 220, and the third channel 230 (e.g., pixels at the same position of each channel differ by several clock cycles). For example, the channel deviation calculating circuit 202 may calculate the channel deviation information among the first channel 210, the second channel 220, and the third channel 230 according to the differences of the start time points of the vertical synchronization signals V _ sync in the decoded signals V1 ', V2 ', and V3 ' respectively output by the

decoders

212, 222, and 232. On the other hand, the control circuit 204 turns off the second channel 220 and/or the third channel 230 for a period of time after the vertical synchronization signal V _ sync occurs, i.e., controls at least a portion of the components of the second channel 220 and/or the third channel 230 to enter a sleep mode. In addition, fig. 3 shows the image frame 300 and the related horizontal synchronization signal H _ sync and vertical synchronization signal V _ sync, and the active display data of the image frame 300 is actually displayed on the display panel 140, and the remaining areas are the vertical blank space and the horizontal blank space, wherein the second channel 220 and/or the third channel 230 will start to enter the normal mode during the last rows of the active display data of the image frame 300, so as to calculate the channel deviation information among the first channel 210, the second channel 220 and the third channel 230, and then control the second channel 220 and/or the third channel 230 to enter the sleep mode (generally before the active display data starts). Since the structure of the image frame 300 is well known to those skilled in the art, the details thereof are not described herein.

After the channel offset information is determined by the channel offset calculation circuit 202, the descrambler 224 in the second channel 220 and/or the descrambler 234 in the second channel 230 may perform descrambling operations according to the descrambling alignment information generated by the first channel 210 and the channel offset information generated by the channel offset calculation circuit 202 to generate the second data D2 and/or the third data D3, respectively.

Next, refer to FIG. 4 showing a timing diagram of the clock signal CLK, the vertical synchronization signal V _ sync, a signal win _ of _ opp, and the encryption status signal enc _ en/enc _ dis. Taking the first channel 210 as an illustration, the key calculation circuit 216 starts to determine the encryption status signal enc _ en/enc _ dis according to the data received in the time range T2 after a period of time T1 after the vertical synchronization signal V _ sync is enabled and within the time range of the signal win _ of _ op. In one example, the encryption status signal enc _ en/enc _ dis can be determined by a plurality of control bits carried in the signal from the electronic device 102/104 within the time range T2. The encryption status signal enc _ en/enc _ dis is used to determine whether to perform a calculation according to the data received in time T1 and the frame key of the previous image frame to obtain the frame key of the image frame 300. In detail, when the encryption status signal enc _ en is determined according to the data received within the time range T2, the key calculating circuit 216 calculates a new frame key; if the encryption status signal enc _ dis is determined according to the data received within the time range T2, the key calculation circuit 216 uses the frame key of the previous image frame as the frame key of the image frame 300. In one example, the time T2 is shown as the time to determine the encryption status signal enc _ en/enc _ dis. In one example, time T1 may be the period of 0 to 511 clock signals CLK after the vertical synchronization signal V _ sync is asserted, time T2 may be the period of 512 to 527 clock signals CLK, and the key calculation circuit 216 may calculate the frame key within a period of time after the encryption status signals enc _ en/enc _ dis are determined, such as (48+56) clock signal CLK periods. Regarding the calculation of the frame key, in the specification of HDCP 1.4, the key calculation circuit 216 calculates the frame key of the image frame 300 according to the data received within the time T1 and the frame key of the previous image frame, whereas in the specification of HDCP 2.2, the key calculation circuit 216 only needs to record the count value of the frame.

Through the above embodiments, the receiving circuit 200 may dynamically shut down at least a portion of the functions of the second channel 220 and/or the third channel 230 when the received audio/video data is not played on the display panel 140, so as to reduce power consumption. The above functions refer to decoding, descrambling, and key calculation, but the invention is not limited thereto. In addition, since the receiving circuit 200 still calculates the frame key of each frame, the connection between the display device 100 and the

electronic devices

102 and 104 can be maintained.

In some HDMI specifications, the encrypted status signal enc _ en/enc _ dis is generated by four control bits CTL 0-CTL 3, wherein the first control bit CTL2 and the second control bit CTL3 are included in the red channel, the third control bit CTL0 and the fourth control bit CTL1 are included in the green channel, and the encrypted status signal enc _ en is indicated when CTL0, CTL1, CTL2 and CTL3 are respectively "1, 0 and 1", and the encrypted status signal enc _ dis is indicated when CTL0, CTL1, CTL2 and CTL3 are respectively "1, 0 and 0". Therefore, since the encryption status signal enc _ en/enc _ dis only needs information of the red channel and the green channel, if the first channel 210 corresponds to the red component of the image frame, the control circuit 204 only needs to dynamically turn on the channel corresponding to the green component of the image frame (e.g., the second channel 220) to successfully obtain the encryption status signal enc/enc _ dis, and at this time, the channel corresponding to the blue component of the image frame (e.g., the third channel 230) can be always turned off (i.e., the internal components are always in the sleep state). In addition, if the first channel 210 corresponds to the green component of the image frame, the control circuit 204 only needs to dynamically turn on the channel corresponding to the red component of the image frame (e.g., the second channel 220) to successfully obtain the encryption status signal enc _ en/enc _ dis, and at this time, the channel corresponding to the blue component of the image frame (e.g., the third channel 230) can be turned off all the time to further save power consumption. In addition, if the first channel 210 corresponds to the blue component of the image frame, the control circuit 204 needs to dynamically turn on the second channel 220 and the third channel 230, so as to obtain the encryption status signal enc _ en/enc _ dis through the second data D2 and the third data D3.

In another embodiment of the present invention, since the first control bit CTL2 and the second control bit CTL3 are included in the red channel, the third control bit CTL0 and the fourth control bit CTL1 are included in the green channel, and the CTL0 to CTL3 are "1, 0 and 1" to represent the encryption status signal enc _ en, and the CTL0 to CTL3 are "1, 0 and 0" to represent the encryption status signal enc _ dis, the related circuit can determine the encryption status signal enc _ en/enc _ dis only by using the first control bit CTL2 and the second control bit CTL3, and does not need to determine the four control bits CTL0 to CTL 3. As described above, if the first channel 210 corresponds to the red component of the image frame, the control circuit 204 may directly turn off the second channel 220 and the third channel 230 (i.e., the internal components are always in the sleep state). In addition, if the first channel 210 corresponds to the green component of the image frame, the control circuit 204 only needs to dynamically turn on the channel corresponding to the red component of the image frame (e.g., the second channel 220) to successfully obtain the encryption status signal enc _ en/enc _ dis, and at this time, the channel corresponding to the blue component of the image frame (e.g., the third channel 230) can be turned off all the time to further save power consumption. In addition, if the first channel 210 corresponds to the blue component of the image frame, the control circuit 204 only needs to dynamically turn on the channel corresponding to the red component of the image frame (e.g., the second channel 220) to successfully obtain the encryption status signal enc _ en/enc _ dis, and at this time, the channel corresponding to the green component of the image frame (e.g., the third channel 230) can be turned off all the time to further save power consumption. It should be noted that the first, second and

third channels

210, 220 and 230 corresponding to the red, green and blue channels are only examples, and the invention is not limited thereto. In other embodiments, the first channel 210, the second channel 220, and the third channel 230 correspond to other kinds of color information, such as YUV channel or YCbCr channel, and the first control bit CTL2 and the second control bit CTL3 may be included in the Y channel or other channels, and the third control bit CTL0 and the fourth control bit CTL1 may be included in another channel.

Fig. 5 is a flowchart of a signal processing method applied to HDMI according to an embodiment of the present invention, and the flowchart refers to the content described in the above embodiment, and is as follows.

Step 500: the process begins.

Step 502: determining whether the image frame is played on the display panel, if so, the process goes to step 504; otherwise, the flow proceeds to step 506.

Step 504: and opening the first channel, the second channel and the third channel to perform decoding, descrambling and frame key calculation operations.

Step 506: opening a first channel to perform decoding, descrambling and frame key calculation operations; dynamically turning on and off the second channel and/or the third channel to perform or stop the operations of decoding, descrambling and frame key calculation.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.

Claims

1. A receiving circuit for a high-resolution multimedia interface, comprising:

a first channel for performing decoding and descrambling operations on a first data stream to generate first data corresponding to first color information of an image frame;

a second channel for decoding and descrambling a second data stream to generate second data corresponding to second color information of the image frame;

a third channel for decoding and descrambling a third data stream to generate third data corresponding to third color information of the image frame;

a control circuit for opening the first channel and determining to open or close at least a part of functions in the second channel or the third channel according to whether the image frame is played on a display panel;

when the image frame cannot be played on the display panel, the control circuit opens the first channel so that the first channel continuously decodes the first data stream to obtain de-scrambling alignment information, and performs de-scrambling operation according to the de-scrambling alignment information to generate the first data; and the control circuit selectively opens and closes the second channel and/or the third channel in the period of the image frame according to the time sequence of the image frame.

2. The receiving circuit of claim 1, further comprising:

a channel deviation calculation circuit for calculating a channel deviation information among the first channel, the second channel and the third channel;

when the control circuit starts the second channel and/or the third channel according to the time sequence of the image frame, the second channel and/or the third channel performs descrambling operation according to the descrambling alignment information and the channel deviation information of the first channel so as to generate the second data and/or the third data respectively.

3. The receiving circuit of claim 1, further comprising:

a timer;

the control circuit starts the second channel and/or the third channel before the time point of the appearance of a vertical synchronization signal according to the time information provided by the timer, and closes the second channel and/or the third channel after a period of time after the appearance of the vertical synchronization signal.

4. The receiver circuit of claim 3, wherein the control circuit turns on the second channel and/or the third channel before the time point of occurrence of the vertical synchronization signal according to the time information provided by the timer, for determining an encryption status signal; and the first channel calculates a frame key according to the first data and the encryption status signal.

5. A receiving circuit for a high-resolution multimedia interface, comprising:

when the image frame cannot be played on the display panel, the control circuit opens the first channel so that the first channel continuously decodes the first data stream to obtain descrambling alignment information, and performs descrambling operation according to the descrambling alignment information to generate the first data; and the control circuit closes the second channel and the third channel.

6. The receiver circuit of claim 5, wherein the first channel obtains an encryption status signal directly from the first data and computes a frame key according to the first data and the encryption status signal.

7. The receiver circuit of claim 5, wherein the receiver circuit complies with HDMI 2.0, and the first channel corresponds to a red component of the image frame.

8. The receiving circuit of claim 5, wherein the first data stream comprises a first control bit and a second control bit for the receiving circuit to obtain an encryption status signal.

9. A signal processing method for a high-resolution multimedia interface, comprising:

providing a first channel to perform decoding operation and de-scrambling operation on a first data stream to generate first data corresponding to first color information of an image frame;

providing a second channel for performing decoding operation and descrambling operation on a second data stream to generate second data corresponding to second color information of the image frame;

providing a third channel for performing decoding operation and descrambling operation on a third data stream to generate third data corresponding to third color information of the image frame; and

opening the first channel, and determining to open or close at least one part of functions in the second channel or the third channel according to whether the image frame is played on a display panel;

wherein the step of determining whether to turn on or off at least a portion of the functions in the second channel or the third channel according to whether the image frame is displayed on a display panel comprises:

when the image frame cannot be played on the display panel, opening the first channel to enable the first channel to continuously decode the first data stream to obtain descrambling alignment information, and performing descrambling operation according to the descrambling alignment information to generate the first data; and selectively opening and closing the second channel and/or the third channel in the period of the image frame according to the time sequence of the image frame.