CN111755555B - Mesa diode, manufacturing method thereof and manufacturing method of array chip - Google Patents
Mesa diode, manufacturing method thereof and manufacturing method of array chip Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
- H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1864—Annealing
Abstract
The application relates to a mesa diode and a manufacturing method thereof and a manufacturing method of an array chip, wherein the mesa diode sequentially comprises a multiplication layer, an impurity control layer and a high-doping P-type layer from bottom to top, the multiplication layer comprises a diffusion area and a multiplication area, and the diffusion area and the impurity control layer are formed by downward diffusion of impurities in the high-doping P-type layer in a heating process. The mesa type diode provided by the application can avoid adopting diffusion furnace, organic metal vapor deposition and other magazine diffusion equipment, directly adjusts the thickness of multiplication region through the mode of heating diffusion, adjusts the difference between the piece that exists between each epitaxial wafer and the difference between each unit in same epitaxial wafer, improves the uniformity between each unit of array chip, and then improves array chip's performance and yield.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a mesa diode and a method for manufacturing the mesa diode, and a method for manufacturing an array chip.
Background
Avalanche Photodiodes (APDs) can be classified into two types, planar and mesa, according to their structure and corresponding technical route. In the manufacturing process of the planar APD, a P-type contact area and a multiplication area are controlled by adopting a diffusion process, and a diffusion window determines the size of a photosensitive surface. The planar APD process has the advantages that side wall protection measures are not needed, the reliability of a chip is good, but the control difficulty of a window diffusion process is high, the diffusion depth is difficult to measure accurately, the diffusion depth directly influences the thickness of a multiplication region, and further influences the avalanche breakdown voltage, so that the consistency control difficulty of each pixel is high when the array chip is manufactured. The thickness and doping concentration of each layer of material of the mesa APD are usually completely determined by epitaxial growth, the size of the photosensitive surface is determined by a subsequent etching process, and the breakdown voltage is not influenced by the etching process, so that compared with a planar APD process, the pixel consistency in the manufacturing of an array chip can be controlled more accurately, and the mesa APD is more widely applied in the manufacturing of the array chip.
However, in the conventional mesa APD manufacturing process, after the epitaxial growth is completed, the structure of each layer is determined, and the inter-wafer difference of each epitaxial wafer is difficult to be compensated by the post-processing technology, so that the inter-batch difference is large, and the performance of the APD is affected.
Disclosure of Invention
The embodiment of the application provides a mesa diode and a manufacturing method thereof, and a manufacturing method of an array chip, so as to solve the technical problem that inter-wafer differences existing between epitaxial wafers in the related art cannot be compensated through a post-processing technology.
In a first aspect, the mesa diode comprises a multiplication layer, an impurity control layer and a high-doping P-type layer from bottom to top in sequence, wherein the multiplication layer comprises a diffusion area and a multiplication area, and the diffusion area and the impurity control layer are formed by downward diffusion of impurities in the high-doping P-type layer in a heating process.
In some embodiments, the multiplication layer is unintentionally doped InP, and the impurity control layer is unintentionally doped InGaAs or compositionally graded In1-xGaxAsyP1-yThe high-doped P type layer is P type saturation concentration InGaAs.
In some embodiments, the mesa diode further includes a substrate, a buffer layer, an absorption layer, a transition layer, and a charge layer in sequence from bottom to top, and the multiplication layer is located above the charge layer.
In some embodiments, the substrate is N-type or semi-insulating InP, the buffer layer is N-type InP, and the absorption layer is unintentionally doped N-type InGaAs or In1-xGaxAsyP1-yThe transition layer is In with gradually changed components1-xGaxAsyP1-yWherein x is more than or equal to 1, y is less than or equal to 1, and the charge layer is N-type InP.
In a second aspect, the present application further provides a method for manufacturing a mesa diode, including the steps of:
growing a multiplication layer, an impurity control layer and a highly doped P type layer from bottom to top in sequence to form an epitaxial structure;
and heating the epitaxial structure to enable the impurities in the highly doped P-type layer to diffuse downwards until the multiplication layer is locally doped to form a diffusion region, and forming a multiplication region in the undoped region of the multiplication layer.
In some embodiments, the step of forming the epitaxial structure comprises:
a buffer layer, an absorption layer, a transition layer, a charge layer, a multiplication layer, an impurity control layer and a high-doped P type layer are sequentially grown on a substrate.
In some embodiments, before heating the epitaxial structure, further comprising the step of:
and carrying out mesa etching on the epitaxial structure to form a mesa epitaxial structure.
In some embodiments, the heating temperature range to heat the epitaxial structure is between 450 ° and 600 °.
In a third aspect, the present application further provides a method for manufacturing an array chip, including the steps of:
manufacturing a plurality of the mesa diodes, and combining the mesa diodes into an array chip on a wafer;
respectively carrying out characteristic voltage test on all mesa diodes in the array chip to obtain the actual thickness of the multiplication region of each mesa diode;
and comparing the actual thickness of the multiplication region of each mesa diode with a preset target thickness, and correspondingly adjusting the thickness of the multiplication region of each mesa diode in a heating diffusion mode according to the comparison result so as to enable the adjusted actual thickness of the multiplication region of each mesa diode to approach to the preset target thickness.
In some embodiments, the specific step of performing a characteristic voltage test on all mesa diodes in the array chip to obtain the actual thickness of the multiplication region of each mesa diode includes:
respectively carrying out characteristic voltage test on all mesa diodes in the array chip to obtain characteristic voltage curves of the mesa diodes, wherein the characteristic voltage curves comprise the thickness of a multiplication region and a starting voltage curve;
and obtaining the actual thickness of the multiplication region according to the starting voltage of the mesa type diode obtained by testing.
In some embodiments, before comparing the actual thickness of the multiplication region of each mesa-type diode with the preset target thickness, the method further comprises the steps of:
and calculating the average value of the actual thicknesses of the multiplication regions of all the mesa-type diodes, and taking the average value of the actual thicknesses of the multiplication regions of all the mesa-type diodes as a preset target thickness.
In some embodiments, the step of correspondingly adjusting the thickness of the multiplication region of the mesa-type diode by means of thermal diffusion includes:
and according to the distribution condition of the actual thickness of the multiplication regions of all the mesa diodes, locally heating or wholly heating the array chip to adjust the thickness of the multiplication regions of the mesa diodes.
In some embodiments, the specific step of locally heating or entirely heating the array chip according to the distribution of the actual thickness of the multiplication region of all the mesa-type diodes includes:
dividing all the mesa diodes into diodes to be heated and non-heated diodes according to the distribution condition of the actual thickness of the multiplication regions of all the mesa diodes and by combining the preset target thickness, wherein the diodes to be heated are the mesa diodes of which the actual thickness exceeds the preset target thickness, and the non-heated diodes are the mesa diodes of which the actual thickness does not exceed the preset target thickness;
dividing all diodes to be heated between two adjacent non-heating diodes into a region to be heated, and dividing all the non-heating diodes between two adjacent diodes to be heated into a non-heating region;
and heating each zone to be heated respectively.
In some embodiments, the specific steps of comparing the actual thickness of the multiplication region of each mesa-type diode with a preset target thickness, and correspondingly adjusting the thickness of the multiplication region of the mesa-type diode by heating and diffusing according to the comparison result include:
comparing the actual thickness of the multiplication region of each mesa diode with a preset target thickness to obtain a difference value between the actual thickness and the target thickness, and taking the mesa diode with the difference value larger than a set threshold value as a diode to be heated;
and respectively heating each diode to be heated, and controlling the heating time of each diode to be heated according to the difference value between the actual thickness and the target thickness of the diode to be heated so as to enable the adjusted actual thickness of the multiplication region of each diode to be heated to approach the preset target thickness.
The beneficial effect that technical scheme that this application provided brought includes: the thickness of the multiplication area can be directly adjusted by heating diffusion through impurity diffusion equipment such as a diffusion furnace and organic metal vapor deposition, the inter-wafer difference between the epitaxial wafers can be adjusted, the consistency between the epitaxial wafers of the array chip and the consistency between units in the same epitaxial wafer can be improved, and the performance and the yield of the array chip can be further improved.
The embodiment of the application provides a mesa type diode, it includes multiplication layer, impurity control layer and high doping P type layer, the multiplication layer includes diffusion zone and multiplication district, just the diffusion zone with the impurity control layer by impurity in the high doping P type layer heats the diffusion downwards and forms, because this mesa type diode forms through heating diffusion, also can carry out the adjustment of the thickness in multiplication district through the mode of heating diffusion in follow-up technology to make when using, can adjust the difference between the piece that exists between each epitaxial wafer and the difference between each unit in the same epitaxial wafer through the mode of heating diffusion, improve the uniformity between each unit of array chip, and then improve array chip's performance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a mesa diode provided in an embodiment of the present application;
fig. 2 is a flowchart of a method for manufacturing a mesa diode according to an embodiment of the present disclosure;
fig. 3 is a flowchart illustrating specific steps of a method for manufacturing a mesa-type diode according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of an epitaxial structure in step S101 according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a mesa-type epitaxial structure in step S102 according to an embodiment of the present disclosure;
fig. 6 is a flowchart of a method for manufacturing an array chip according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a characteristic voltage curve provided in the embodiment of the present application.
In the figure: 1. a substrate; 2. a buffer layer; 3. an absorbing layer; 4. a transition layer; 5. a charge layer; 6. a multiplication layer; 61. a diffusion region; 62. a multiplication region; 7. an impurity control layer; 8. a highly doped P-type layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, an embodiment of the present application provides a mesa diode, which includes a multiplication layer 6, an impurity control layer 7, and a highly doped P-type layer 8 from bottom to top in sequence, where the multiplication layer 6 includes a diffusion region 61 and a multiplication region 62, and the diffusion region 61 and the impurity control layer 7 are formed by downward diffusion of impurities in the highly doped P-type layer 8 during a heating process.
In the embodiment of the application, since the mesa-type diode is formed by heating diffusion, the thickness of the multiplication region 62 can be adjusted in a subsequent process in a heating diffusion manner, so that during application, inter-wafer differences between epitaxial wafers and differences between units in the same epitaxial wafer can be adjusted in a heating diffusion manner, the consistency between the units of the array chip is improved, and the performance and yield of the array chip are improved.
Specifically, In the embodiment of the present application, the multiplication layer 6 is unintentionally doped InP, and the impurity control layer 7 is unintentionally doped InGaAs or compositionally graded In1-xGaxAsyP1-yAnd the high-doping P type layer 8 is P type saturation concentration InGaAs.
With reference to fig. 1, the mesa diode in the embodiment of the present application further includes, from bottom to top, a substrate 1, a buffer layer 2, an absorption layer 3, a transition layer 4, and a charge layer 5, and the multiplication layer 6 is located above the charge layer 5.
Specifically, In the embodiment of the present application, the substrate 1 is N-type or semi-insulating InP, the buffer layer 2 is N-type InP, and the absorption layer 3 is unintentionally doped N-type InGaAs or In1-xGaxAsyP1-yThe transition layer 4 is In with gradually changed components1-xGaxAsyP1-yWherein x is more than or equal to 1, y is less than or equal to 1, and the charge layer 5 is N-type InP.
Referring to fig. 2, an embodiment of the present application provides a method for manufacturing a mesa diode, including the steps of:
s1: growing a multiplication layer 6, an impurity control layer 7 and a highly doped P type layer 8 from bottom to top in sequence to form an epitaxial structure;
s2: and heating the epitaxial structure to diffuse the impurities in the highly doped P-type layer 8 downwards until the multiplication layer 6 is locally doped to form a diffusion region 61, and an undoped region of the multiplication layer 6 forms a multiplication region 62. Wherein a heating temperature range for heating the epitaxial structure is between 450 ° and 600 °.
In the method for manufacturing a mesa diode according to the embodiment of the present application, the diffusion region 61 is formed by heating diffusion, and the thickness of the multiplication region 62 can be adjusted by heating diffusion in a subsequent processing process, so that during application, inter-wafer differences between the epitaxial wafers and differences between units in the same epitaxial wafer can be adjusted by heating diffusion, the consistency between the units of the array chip is improved, and the performance and yield of the array chip are improved.
In step S1, the specific step of forming the epitaxial structure includes:
a buffer layer 2, an absorption layer 3, a transition layer 4, a charge layer 5, a multiplication layer 6, an impurity control layer 7 and a high-doping P type layer 8 are sequentially grown on a substrate 1.
Further, in the embodiment of the present application, before heating the epitaxial structure, the method further includes the steps of:
and carrying out mesa etching on the epitaxial structure to form a mesa structure.
Preferably, in the embodiment of the present application, after performing mesa etching, the heating temperature range for heating the mesa-type structure is between 450 ° and 600 °, so that the effect is better.
Referring to fig. 3, a method for manufacturing a mesa diode according to an embodiment of the present application includes the specific steps of:
s101: sequentially growing a buffer layer 2, an absorption layer 3, a transition layer 4, a charge layer 5, a multiplication layer 6, an impurity control layer 7 and a highly doped P-type layer 8 on a substrate 1 to form an epitaxial structure, as shown in fig. 4;
s102: performing mesa etching on the epitaxial structure to form a mesa structure, as shown in fig. 5;
s103: heating the mesa structure to diffuse the impurities in the highly doped P-type layer 8 downward in sequence until the multiplication layer 6 is partially doped to form a diffusion region 61, and the undoped region of the multiplication layer 6 forms a multiplication region 62, as shown in fig. 1, wherein the thickness of the multiplication region 62 is dMAnd (4) showing.
Referring to fig. 6, an embodiment of the present application further provides a method for manufacturing an array chip, including the steps of:
a1: manufacturing a plurality of mesa diodes, and combining the mesa diodes into an array chip on a wafer; each mesa diode is a unit of the array chip;
a2: respectively performing characteristic voltage tests on all mesa diodes in the array chip to obtain the actual thickness of the multiplication region 62 of each mesa diode;
a3: comparing the actual thickness of the multiplication region 62 of each mesa-shaped diode with a preset target thickness, and correspondingly adjusting the thickness of the multiplication region 62 of each mesa-shaped diode in a heating diffusion mode according to the comparison result so that the actual thickness of the multiplication region 62 of each mesa-shaped diode after adjustment approaches to the preset target thickness. In the method for manufacturing the array chip of the embodiment of the application, the characteristic voltage test is performed on all mesa diodes in the array chip to obtain a characteristic voltage distribution diagram, the condition that all mesa diode units have differences can be seen, the actual thickness of the mesa diodes is compared with the preset target thickness, the thickness of the multiplication region 62 of the mesa diodes is correspondingly adjusted in a heating diffusion mode, and the actual thickness of the multiplication region 62 of each mesa diode after adjustment approaches to the preset target thickness, so that the differences among the units can be reduced, the consistency of the array chip is improved, the adjustment is performed according to the preset target thickness, and the performance of the array chip is better.
In the step a2, the specific step of performing the characteristic voltage test on all the mesa diodes in the array chip to obtain the actual thickness of the multiplication region 62 of each mesa diode includes:
respectively performing characteristic voltage tests on all mesa diodes in the array chip to obtain characteristic voltage curves of the mesa diodes, wherein the characteristic voltage curves comprise a curve of the thickness and the starting voltage of the multiplication region 62 and a curve of the thickness and the breakdown voltage of the multiplication region 62, and are shown in fig. 7;
the actual thickness of the multiplication region 62 is obtained from the turn-on voltage of the mesa type diode obtained by the test.
Referring to the characteristic voltage curve diagram shown in fig. 7, the breakdown voltage and the thickness of the multiplication region 62 are in a V-shaped curve relationship, and the turn-on voltage and the thickness of the multiplication region 62 are in a linear relationship, so that, during manufacturing, the actual thickness of the multiplication region 62 can be obtained according to the tested turn-on voltage, and the corresponding thickness of the multiplication region 62 is the optimal thickness of the mesa-shaped diode when the breakdown voltage is minimum.
In practical applications, since the corresponding parameters are already designed when designing the epitaxial structure for fabricating the mesa-type diode, the thickness of the multiplication region 62 needs to be adjusted only due to the possible differences in the actual manufacturing process, that is, the process of actually adjusting the multiplication region 62 is: the thickness of the multiplication region 62 is reduced by means of thermal diffusion.
It should be noted that, in the embodiment of the present application, the preset target thickness may be a theoretical value or an empirical value for optimizing the performance of the array chip, or may be an average value of actual thicknesses of the multiplication regions 62 of all mesa-type diodes.
In some embodiments, the step a3 further includes, before comparing the actual thickness of the multiplication region 62 of each mesa-type diode with the preset target thickness, the steps of:
the average value of the actual thicknesses of the multiplication regions 62 of all the mesa-type diodes is calculated, and the average value of the actual thicknesses of the multiplication regions 62 of all the mesa-type diodes is taken as a preset target thickness.
In the embodiment of the application, the average value of the actual thicknesses of the multiplication regions 62 of all mesa-type diodes is used as the preset target thickness, and then adjustment is performed, so that inter-wafer differences existing among epitaxial wafers and differences among units in the same epitaxial wafer can be solved, and the consistency and yield of the array chip are improved.
In the embodiment of the present invention, the thickness of the multiplication region 62 of the mesa-shaped diode is adjusted by the heating diffusion, and the mesa-shaped diode may be heated by regions or individually heated.
In some embodiments, in the step a3, the step of correspondingly adjusting the thickness of the multiplication region 62 of the mesa-type diode by means of thermal diffusion includes:
according to the distribution of the actual thickness of the multiplication region 62 of all the mesa-type diodes, the array chip is locally heated or wholly heated to adjust the thickness of the multiplication region 62 of the mesa-type diodes.
In the embodiment of the present application, the specific steps of locally heating or entirely heating the array chip according to the distribution of the actual thickness of the multiplication region 62 of all the mesa-type diodes include:
dividing all the mesa diodes into diodes to be heated and non-heated diodes according to the distribution condition of the actual thickness of the multiplication regions 62 of all the mesa diodes and by combining the preset target thickness, wherein the diodes to be heated are mesa diodes of which the actual thickness exceeds the preset target thickness, and the non-heated diodes are mesa diodes of which the actual thickness does not exceed the preset target thickness;
dividing all diodes to be heated between two adjacent non-heating diodes into a region to be heated, and dividing all the non-heating diodes between two adjacent diodes to be heated into a non-heating region;
and heating each zone to be heated respectively.
In the embodiment of the application, the array chip is heated in a regional mode, the difference between mode adjustment sheets can be rapidly adjusted through heating diffusion, the process is simple, and the efficiency is higher.
In another embodiment, the specific steps of comparing the actual thickness of the multiplication region 62 of each mesa-type diode with a preset target thickness, and correspondingly adjusting the thickness of the multiplication region 62 of the mesa-type diode by means of thermal diffusion according to the comparison result include:
comparing the actual thickness of the multiplication region 62 of each mesa-shaped diode with a preset target thickness to obtain a difference value between the actual thickness and the target thickness, and taking the mesa-shaped diode with the difference value larger than a set threshold value as a diode to be heated;
and respectively heating each diode to be heated, and controlling the heating time of each diode to be heated according to the difference value between the actual thickness and the target thickness of each diode to be heated so as to enable the adjusted actual thickness of the multiplication region 62 of each diode to be heated to approach the preset target thickness.
In the embodiment of the application, each diode to be heated is respectively heated and adjusted, independent control is carried out, the adjustment precision can be improved, the actual thickness of each diode to be heated is closer to the preset target thickness, and the effect is better.
In this embodiment of the application, the heating mode may be laser heating, or may be other heating processes, and the heating device may be a rapid annealing furnace RTP, or may be other heating devices capable of accurately controlling the temperature, so as to achieve the purpose of heating and diffusing, which is not limited herein.
In the description of the present application, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. A method for manufacturing an array chip is characterized in that,
manufacturing a plurality of mesa diodes, and combining the mesa diodes into an array chip on a wafer;
respectively performing characteristic voltage test on all mesa diodes in the array chip to obtain the actual thickness of the multiplication region (62) of each mesa diode;
comparing the actual thickness of the multiplication region (62) of each mesa diode with a preset target thickness, and correspondingly adjusting the thickness of the multiplication region (62) of each mesa diode in a heating diffusion mode according to the comparison result so that the actual thickness of the multiplication region (62) of each mesa diode after adjustment approaches to the preset target thickness;
mesa type diode includes multiplication layer (6), impurity control layer (7) and high doping P type layer (8) from bottom to top in proper order, multiplication layer (6) are including diffusion zone (61) and multiplication zone (62), just diffusion zone (61) with impurity control layer (7) by impurity in the high doping P type layer (8) diffuses downwards in the heating process and forms.
2. The method for manufacturing an array chip according to claim 1, wherein: the multiplication layer (6) is unintentionally doped InP, and the impurity control layer (7) is unintentionally doped InGaAs or In of gradually varying composition1-xGaxAsyP1-yAnd the high-doped P type layer (8) is P type saturation concentration InGaAs.
3. The method for manufacturing an array chip according to claim 1, wherein: the composite material is characterized by further comprising a substrate (1), a buffer layer (2), an absorption layer (3), a transition layer (4) and a charge layer (5) from bottom to top, wherein the multiplication layer (6) is located above the charge layer (5).
4. The method of manufacturing an array chip according to claim 3, wherein: the substrate (1) is N-type or semi-insulating InP, the buffer layer (2) is N-type InP, and the absorption layer (3) is unintentionally doped N-type InGaAs or In1-xGaxAsyP1-yThe transition layer (4) is In with gradually changed components1-xGaxAsyP1-yWherein x is more than or equal to 1, y is less than or equal to 1, and the charge layer (5) is N-type InP.
5. The method for manufacturing an array chip according to claim 1, wherein the method for manufacturing the mesa type diode comprises the steps of:
growing a multiplication layer (6), an impurity control layer (7) and a highly doped P-type layer (8) from bottom to top in sequence to form an epitaxial structure;
and heating the epitaxial structure to diffuse down the impurities in the highly doped P type layer (8) until the multiplication layer (6) is locally doped to form a diffusion region (61), and forming a multiplication region (62) in the undoped region of the multiplication layer (6).
6. The method for manufacturing the array chip of claim 5, wherein the step of forming the epitaxial structure comprises:
a buffer layer (2), an absorption layer (3), a transition layer (4), a charge layer (5), a multiplication layer (6), an impurity control layer (7) and a high-doping P-type layer (8) are sequentially grown on a substrate (1).
7. The method of fabricating an array chip according to claim 5, further comprising, before heating the epitaxial structure, the steps of:
and carrying out mesa etching on the epitaxial structure to form a mesa epitaxial structure.
8. The method of claim 5, wherein the epitaxial structure is heated at a temperature in a range of 450 ° to 600 °.
9. The method for manufacturing an array chip according to claim 1, wherein the step of performing a characteristic voltage test on all mesa-type diodes in the array chip to obtain the actual thickness of the multiplication region (62) of each mesa-type diode comprises:
respectively carrying out characteristic voltage test on all mesa diodes in the array chip to obtain characteristic voltage curves of the mesa diodes, wherein the characteristic voltage curves comprise the thickness of a multiplication region (62) and a starting voltage curve;
and obtaining the actual thickness of the multiplication region (62) according to the turn-on voltage of the mesa type diode obtained by the test.
10. The method for fabricating an array chip according to claim 1, further comprising the step of, before comparing the actual thickness of the multiplication region (62) of each mesa type diode with a preset target thickness:
and calculating the average value of the actual thicknesses of the multiplication regions (62) of all the mesa-type diodes, and taking the average value of the actual thicknesses of the multiplication regions (62) of all the mesa-type diodes as a preset target thickness.
11. The method for manufacturing an array chip according to claim 1, wherein the step of correspondingly adjusting the thickness of the multiplication region (62) of the mesa-type diode by means of thermal diffusion comprises:
and according to the distribution condition of the actual thickness of the multiplication region (62) of all the mesa diodes, locally heating or wholly heating the array chip to adjust the thickness of the multiplication region (62) of the mesa diode.
12. The method for fabricating an array chip according to claim 11, wherein the step of locally heating or entirely heating the array chip according to the distribution of the actual thickness of the multiplication region (62) of all the mesa-type diodes comprises:
dividing all the mesa diodes into diodes to be heated and non-heated diodes according to the distribution condition of the actual thickness of the multiplication regions (62) of all the mesa diodes and by combining the preset target thickness, wherein the diodes to be heated are mesa diodes of which the actual thickness exceeds the preset target thickness, and the non-heated diodes are mesa diodes of which the actual thickness does not exceed the preset target thickness;
dividing all diodes to be heated between two adjacent non-heating diodes into a region to be heated, and dividing all the non-heating diodes between two adjacent diodes to be heated into a non-heating region;
and heating each zone to be heated respectively.
13. The method for manufacturing an array chip according to claim 1, wherein the specific steps of comparing the actual thickness of the multiplication region (62) of each mesa-type diode with a preset target thickness and correspondingly adjusting the thickness of the multiplication region (62) of the mesa-type diode by means of thermal diffusion according to the comparison result comprise:
comparing the actual thickness of the multiplication region (62) of each mesa diode with a preset target thickness to obtain a difference value between the actual thickness and the target thickness, and taking the mesa diode with the difference value larger than a set threshold value as a diode to be heated;
and respectively heating each diode to be heated, and controlling the heating time of each diode to be heated according to the difference value between the actual thickness and the target thickness of the diode to be heated so as to enable the adjusted actual thickness of the multiplication region (62) of each diode to be heated to approach to the preset target thickness.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020001988A (en) * | 2000-06-29 | 2002-01-09 | 윤종용 | Method of manufacturing avalanche phoetodiode |
| CN1933187A (en) * | 2005-09-12 | 2007-03-21 | 三菱电机株式会社 | Avalanche photodiode |
| KR20140045137A (en) * | 2012-10-08 | 2014-04-16 | 한국과학기술원 | Method of producting planar avalanche photodiode |
| CN110112249A (en) * | 2019-04-18 | 2019-08-09 | 中国科学技术大学 | Avalanche photodide and preparation method |
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| US5866936A (en) * | 1997-04-01 | 1999-02-02 | Hewlett-Packard Company | Mesa-structure avalanche photodiode having a buried epitaxial junction |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020001988A (en) * | 2000-06-29 | 2002-01-09 | 윤종용 | Method of manufacturing avalanche phoetodiode |
| CN1933187A (en) * | 2005-09-12 | 2007-03-21 | 三菱电机株式会社 | Avalanche photodiode |
| KR20140045137A (en) * | 2012-10-08 | 2014-04-16 | 한국과학기술원 | Method of producting planar avalanche photodiode |
| CN110112249A (en) * | 2019-04-18 | 2019-08-09 | 中国科学技术大学 | Avalanche photodide and preparation method |
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