CN111755511A - VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor), preparation method thereof and semiconductor device - Google Patents

VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor), preparation method thereof and semiconductor device Download PDF

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CN111755511A
CN111755511A CN201910232600.3A CN201910232600A CN111755511A CN 111755511 A CN111755511 A CN 111755511A CN 201910232600 A CN201910232600 A CN 201910232600A CN 111755511 A CN111755511 A CN 111755511A
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conductive type
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doped
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lightly doped
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CN111755511B (en
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李俊俏
李永辉
周维
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BYD Co Ltd
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Abstract

The VDMOSFET comprises a first conduction type heavily doped substrate, a first conduction type lightly doped drift layer, a second conduction type lightly doped well region, a second conduction type heavily doped contact region, a first conduction type heavily doped source region, a second conduction type lightly doped region, a first conduction type lightly doped region, a gate oxide layer, a gate, a source and a drain. The VDMOSFET is characterized in that a second conductive type lightly doped region and a first conductive type lightly doped region are introduced to form a PN column (super junction structure) which alternately appears, so that the on-resistance is greatly reduced, the breakdown voltage is not reduced, a gate oxide layer can be effectively protected from being broken down, and the reliability of a device is improved.

Description

VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor), preparation method thereof and semiconductor device
Technical Field
The application relates to the technical field of semiconductors, in particular to a VDMOSFET, a preparation method thereof and a semiconductor device.
Background
The SIC MOSFET has the advantages of high input impedance, high switching speed stability, low on-resistance and the like, and is the SIC switching device which is most concerned at present. Among the sic mosfets, vdmosfet (vertical connection double scaling Metal Oxide semiconductor) is a faster-developing power device at present; the circuit has the characteristics of unique high input impedance, low driving power, high switching speed, excellent frequency characteristic, low noise, good thermal stability, radiation resistance, simple manufacturing process and the like; the device is widely applied to various fields such as alternating current transmission, variable frequency power supplies, switching voltage-stabilized power supplies and the like, and achieves good effects.
In the related art, the VDMOSFET structure is shown in fig. 1: the transistor comprises an N + substrate layer 10, an N type drift region 20, a P-well region (pwell)30, a P + contact region 40, an N + source region 50, a source electrode 60, a grid electrode 70, a drain electrode 80, a JFET region 90 and a grid oxide layer 100. The following disadvantages exist in the lateral channel device structure: firstly, the on-resistance of a device (namely on-state loss in application) can be increased due to the existence of a JFET (junction field effect transistor) region, and the method for reducing the resistance of the JFET region in the related art is to increase the distance between pwells or perform N-injection in the JFET region, but a short channel effect (the device is started in advance) is easily caused, the carrier concentration below a gate oxide layer is higher, the gate oxide layer bears higher voltage, gate oxygen is broken down in advance, and the withstand voltage of the device is reduced; secondly, the on-resistance of the device is inversely proportional to the voltage withstanding value, if the on-resistance is reduced by increasing the concentration of the N-drift layer 20, part of the voltage withstanding of the device is lost, and the voltage withstanding of the device cannot be ensured while the on-resistance is reduced; thirdly, due to the existence of C element, SiC/SiO2The interface state density of the material is about three times that of Si, and the high interface state density causes low channel mobility; fourthly, the higher SiC/SiO2The interface state density of the material and the gate oxide layer are easy to break down in advance compared with a silicon device, so that the actual voltage withstanding value of the device is much lower than the calculated value.
Thus, the related art of the current VDMOSFET still needs to be improved.
Disclosure of Invention
The present application is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a VDMOSFET capable of effectively reducing the on-resistance of the device, improving the voltage endurance of the device, effectively improving the electron mobility in the channel, or effectively protecting the gate oxide layer from breakdown.
In one aspect of the present application, a VDMOSFET is provided. According to an embodiment of the present application, the VDMOSFET includes: a first conductive type heavily doped substrate; a first-conductivity-type lightly-doped drift layer disposed on an upper surface of the first-conductivity-type heavily-doped substrate; a functional doping layer disposed on an upper surface of the first conductive type lightly doped drift layer and including a first doping region and a second doping region located outside the first doping region, wherein the second doping region includes a second conductive type lightly doped well region, a second conductive type heavily doped contact region and a first conductive type heavily doped source region, the second conductive type heavily doped contact region and the first conductive type heavily doped source region are disposed on a portion of an upper surface of the second conductive type lightly doped well region located outside, the second conductive type heavily doped contact region is located outside the first conductive type heavily doped source region, and the upper surface of the second conductive type contact region, the upper surface of the first conductive type heavily doped source region and the heavily doped well region of the second conductive type lightly doped well region are not covered by the second conductive type contact region and the first conductive type source region The upper surface is flush; the first doping area comprises a second conductive type lightly doped area and a first conductive type lightly doped area, and the first conductive type lightly doped area is arranged on the outer side of the second conductive type lightly doped area; the gate oxide layer is arranged on the upper surface of the functional doping layer, covers the upper surface of the first doping region, the upper surface of the second conduction type lightly doped well region which is not covered by the second conduction type heavily doped contact region and the first conduction type heavily doped source region and the upper surface gate of part of the first conduction type heavily doped source region, and is arranged on the upper surface of the gate oxide layer; the source electrode is arranged on the upper surface of the functional doping layer and covers the upper surface of the second conductive type heavily doped contact region and the upper surface of part of the second conductive type heavily doped source region; a drain disposed on a lower surface of the substrate. The VDMOSFET is introduced with a second conductive type light doped region and a first conductive type light doped region to form alternately appeared PN columns (super junction structure), when the device is in reverse bias, the PN columns in the super junction have reverse bias phenomenon, charges of the two columns are mutually compensated, and a depletion layer is formed between the charges, redundant current carriers are transversely depleted at the time, partial reverse bias voltage is born by the depletion region (equivalent to resistance), the voltage resistance of the device can be greatly improved, and the doping concentration of a drift layer of the device can be greatly improved because the redundant current carriers can be transversely depleted at the time, so that the on-resistance is greatly reduced without reducing the breakdown voltage, meanwhile, the depletion layer (resistance region) below a gate oxide layer can bear the reverse voltage, the gate oxide layer is effectively protected from being broken down, and the voltage resistance of the device can be improved while the on-resistance of the device is effectively reduced, and the reliability of the device can be improved. Furthermore, the width and the doping concentration of the PN column can be adjusted, so that the super junction can reach an optimal state, namely the charges are just completely exhausted before the super junction is broken down, the device has better voltage resistance, breakdown resistance and on-resistance, and the use performance and the reliability are greatly improved.
In another aspect of the present application, the present application provides a method of fabricating the VDMOSFET described above. According to an embodiment of the application, the method comprises: forming a first conductive type lightly doped layer on an upper surface of the first conductive type heavily doped substrate; performing ion implantation on the first conductive type lightly doped layer to form a functional doped layer and a first conductive type lightly doped drift layer, wherein the functional doped layer is arranged on the upper surface of the first conductive type lightly doped drift layer; forming a gate oxide layer on a part of the upper surface of the functional doping layer; forming a grid on the upper surface of the gate oxide layer; forming a source electrode on a part of the upper surface of the functional doping layer; forming a drain electrode on a lower surface of the substrate; wherein the step of forming the functional doping layer comprises: performing first ion implantation on the first conductive type lightly doped layer to form a second conductive type lightly doped well region; performing second ion implantation on the first conductive type lightly doped layer to form a second conductive type lightly doped region; performing third ion implantation on the first conductive type lightly doped layer to form a first conductive type lightly doped region; performing fourth ion implantation on the first conductive type lightly doped layer to form a first conductive type heavily doped source region; performing fifth ion implantation on the first conductive type lightly doped layer to form a second conductive type heavily doped contact region; and annealing the product obtained after the fifth ion implantation. The method can be used for quickly and effectively preparing the VDMOSFET, has simple steps and convenient operation, and is easy to realize industrial production.
In yet another aspect of the present application, a semiconductor device is provided. According to an embodiment of the present application, the semiconductor device includes the VDMOSFET described above. The semiconductor device includes all the features and advantages of the VDMOSFET described above and will not be described in detail herein.
Drawings
Fig. 1 is a schematic cross-sectional view of a VDMOSFET in the related art.
Fig. 2 is a schematic cross-sectional view of a VDMOSFET according to an embodiment of the present application.
Fig. 3 is a schematic cross-sectional view of a VDMOSFET according to another embodiment of the present application.
Fig. 4 is a schematic flow chart of a method of fabricating a VDMOSFET according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a partial cross-sectional structure of a VDMOSFET according to another embodiment of the present application.
Fig. 6 is a schematic diagram of a partial cross-sectional structure of a VDMOSFET according to another embodiment of the present application.
Fig. 7 is a schematic diagram of a partial cross-sectional structure of a VDMOSFET according to another embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below. The following description of the embodiments is merely exemplary in nature and is in no way intended to limit the present disclosure. The examples, where specific techniques or conditions are not indicated, are to be construed according to the techniques or conditions described in the literature in the art or according to the product specifications. The reagents or instruments used are not indicated by manufacturers, and are all conventional products available on the market.
In one aspect of the present application, a VDMOSFET is provided. According to an embodiment of the present application, referring to fig. 2, the VDMOSFET includes: a first conductivity type heavily doped substrate 1; a first conductive type lightly doped drift layer 2, the first conductive type lightly doped drift layer 2 being disposed on an upper surface of the first conductive type heavily doped substrate 1; a functional doping layer 3 disposed on an upper surface of the first conductive-type lightly doped drift layer 2 and including a first doping region 32 and a second doping region 34 located outside the first doping region, wherein the second doping region 34 includes a second conductive-type lightly doped well region 342, a second conductive-type heavily doped contact region 344 and a first conductive-type heavily doped source region 346, the second conductive-type heavily doped contact region 344 and the first conductive-type heavily doped source region 346 are disposed on a portion of an upper surface of the second conductive-type lightly doped well region 342 located outside, the second conductive-type heavily doped contact region 344 is located outside the first conductive-type heavily doped source region 346, and the upper surface of the second conductive-type heavily doped contact region 344, the upper surface of the first conductive-type heavily doped source region 346 and the second conductive-type lightly doped well region 342 are not covered by the second conductive-type heavily doped contact region 344 Flush with the upper surface covered by the first-conductivity-type heavily doped source region 346; the first doping region 32 includes a second conductive type lightly doped region 322 and a first conductive type lightly doped region 324, and the first conductive type lightly doped region 324 is disposed outside the second conductive type lightly doped region 322; a gate oxide layer 4, wherein the gate oxide layer 4 is disposed on the upper surface of the functional doping layer 3, and covers the upper surface of the first doping region 32, the upper surface of the second-conductivity-type lightly doped well region 342 not covered by the second-conductivity-type heavily doped contact region 344 and the first-conductivity-type heavily doped source region 346, and the upper surface gate 5 of a part of the first-conductivity-type heavily doped source region 346, and the gate 5 is disposed on the upper surface of the gate oxide layer 4; a source electrode 6, wherein the source electrode 6 is disposed on the upper surface of the function doping layer 3 and covers the upper surface of the second conductive type heavily doped contact region 344 and a portion of the upper surface of the second conductive type heavily doped source region 346; a drain electrode 7, the drain electrode 7 being disposed on a lower surface of the substrate 1. The VDMOSFET is introduced with a second conductive type lightly doped region 322 and a first conductive type lightly doped region 324 to form alternately-appearing PN columns (super junction structure), when the device is in reverse bias, the PN columns in the super junction have reverse bias phenomenon, charges of the two columns are mutually compensated and form a depletion layer between the charges, redundant carriers are transversely depleted at the time, partial reverse bias voltage is born by the depletion region (equivalent to resistance), the withstand voltage of the device can be greatly improved, and because the redundant carriers can be transversely depleted at the time, the doping concentration of a drift layer of the device can be greatly improved, the on resistance is greatly reduced and the breakdown voltage is not reduced, meanwhile, the depletion layer (resistance region) can be formed below a gate oxide layer to bear the reverse voltage, the gate oxide layer is effectively protected from being broken down, the withstand voltage capability of the device can be improved while the on resistance of the device is effectively reduced, and the reliability of the device can be improved. Furthermore, the width and the doping concentration of the PN column can be adjusted, so that the super junction can reach an optimal state, namely the charges are just completely exhausted before the super junction is broken down, the device has better voltage resistance, breakdown resistance and on-resistance, and the use performance and the reliability are greatly improved.
It is to be noted that, as used herein, one of the description "first conductivity type" and "second conductivity type" is n-type conductivity, i.e., electron conductivity, and the other of the description "first conductivity type" and "second conductivity type" is p-type conductivity, i.e., hole conductivity. In some embodiments, the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity.
According to the embodiments of the present application, the material of the first conductive type heavily doped substrate 1 is doped silicon carbide (SiC), and the specific doping concentration can be flexibly selected according to actual needs, in some embodiments, the first conductive type heavily doped substrate can be an N-type heavily doped SiC substrate, the doping impurity can be nitrogen (N) or phosphorus (P), and the specific doping concentration is 1 × 1018cm-3-1×1019cm-3(specifically, it may be 1 × 1018cm-3、2×1018cm-3、3×1018cm-3、4×1018cm-3、5×1018cm-3、6×1018cm-3、7×1018cm-3、8×1018cm-3、9×1018cm-3、1.0×1019cm-3Etc.). Thus, the heavily doped concentration is beneficial for reducing the substrate resistance and thus the device resistance, and compared with the above concentration range, if the concentration is too low, the device resistance is relatively large, and if the concentration is too high, the carrier mobility is relatively reduced.
In some embodiments, the first conductive lightly doped drift layer is N-type doped silicon carbide, the doping impurity can be nitrogen (N) or phosphorus (P), the thickness can be 10 to 12 micrometers (specifically, 10 micrometers, 10.5 micrometers, 11 micrometers, 11.5 micrometers, 12 micrometers, etc.), and the specific doping concentration can be 1.0 × 1015cm-3～1.0×1016cm-3(specifically 1.0 × 10)15cm-3、2×1015cm-3、3×1015cm-3、4×1015cm-3、5×1015cm-3、6×1015cm-3、7×1015cm-3、8×1015cm-3、9×1015cm-3、1.0×1016cm-3Etc.). Therefore, in the doping concentration range, the device has better resistance and voltage resistance, and better meets the use function requirement; if the doping concentration is too high, the withstand voltage performance is relatively deteriorated.
According to an embodiment of the present application, the lightly doped well region 342 of the second conductivity type may be p-type doped, and the doping impurity may be aluminum (Al) or boron (B), and the specific doping concentrationMay be 2.0 × 1013cm-3～3.0×1013cm-3(specifically, 2.0 × 1013cm-3、2.1×1013cm-3、2.2×1013cm-3、2.3×1013cm-3、2.4×1013cm-3、2.5×1013cm-3、2.6×1013cm-3、2.7×1013cm-3、2.8×1013cm-3、2.9×1013cm-3、3.0×1013cm-3Etc.). Therefore, in the doping concentration range, the device can have a proper starting voltage, and compared with the doping concentration range, if the doping concentration is too high, an inversion layer cannot be formed, and the device is difficult to start; if the doping concentration is too low, the turn-on voltage is relatively low, which may cause the device to turn on without applying a voltage to the gate, thereby causing the device to fail.
According to an embodiment of the present application, the second conductive type heavily doped contact region 344 may be p-type doped, the doping impurity may be aluminum (Al) or boron (B), and the specific doping concentration may be 1.0 × 1016cm-3～2.0×1016cm-3(1.0×1016cm-3、1.1×1016cm-3、1.2×1016cm-3、1.3×1016cm-3、1.4×1016cm-3、1.5×1016cm-3、1.6×1016cm-3、1.7×1016cm-3、1.8×1016cm-3、1.9×1016cm-3、2.0×1016cm-3Etc.). Therefore, the second conductive type heavily doped contact region can form good ohmic contact with the source electrode without increasing the on-resistance of the device; compared with the doping concentration range, if the concentration is too high, the on-resistance of the device is relatively increased, and if the concentration is too low, ohmic contact cannot be formed, so that the use performance of the device is affected.
According to an embodiment of the present application, the first conductive type heavily doped source region may be N-type doped with nitrogen (N) or phosphorus (P) as a dopant impurityThe doping concentration of the body may be 2.0 × 1015cm-3～4.0×1015cm-3(specifically, 2.0 × 1015cm-3、2.1×1015cm-3、2.2×1015cm-3、2.3×1015cm-3、2.4×1015cm-3、2.5×1015cm-3、2.6×1015cm-3、2.7×1015cm-3、2.8×1015cm-3、2.9×1015cm-3、3.0×1015cm-3、3.1×1015cm-3、3.2×1015cm-3、3.3×1015cm-3、3.4×1015cm-3、3.5×1015cm-3、3.6×1015cm-3、3.7×1015cm-3、3.8×1015cm-3、3.9×1015cm-3、4.0×1015cm-3Etc.). Therefore, the first conduction type heavily doped source region which is an important region for current circulation can be made to have sufficiently low resistance and a good circulation channel, and compared with the above doping concentration range, if the doping concentration is too low, the current circulation is not facilitated; if the doping concentration is too high, the performance of the device is not improved obviously, but the cost is increased relatively.
According to an embodiment of the present application, the second conductive type lightly doped region may be p-type doped, the specific doping impurity may be aluminum (Al) or boron (B), and the specific doping concentration may be 2 × 1013cm-3～3×1013cm-3(specifically 2 × 1013cm-3、2.1×1013cm-3、2.2×1013cm-3、2.3×1013cm-3、2.4×1013cm-3、2.5×1013cm-3、2.6×1013cm-3、2.7×1013cm-3、2.8×1013cm-3、2.9×1013cm-3、3.0×1013cm-3Etc.); the first conductive type lightly doped region may be N-type doped with nitrogen (N) or phosphorus (P), and the specific doping concentration may beIs 1.5 × 1013cm-3～2.5×1013cm-3(specifically 1.5 × 1013cm-3、1.6×1013cm-3、1.7×1013cm-3、1.8×1013cm-3、1.9×1013cm-3、2.0×1013cm-3、2.1×1013cm-3、2.2×1013cm-3、2.3×1013cm-3、2.4×1013cm-3、2.5×1013cm-3Etc.). Therefore, the second conductive type light doped regions and the first conductive type light doped regions which are alternately arranged can form a PN column (super junction structure), the doping concentration range can enable the super junction structure to reach an optimal state, namely, just completely depleting charges just before the super junction enters breakdown, so that redundant current carriers are completely depleted transversely, a part of reverse bias voltage is borne by the depletion region, the voltage resistance of the device can be greatly improved, and the doping concentration of the drift layer can be greatly improved because the redundant current carriers can be transversely depleted at the moment, so that the on-resistance is greatly reduced and the breakdown voltage is not reduced.
According to an embodiment of the present application, referring to fig. 3, the functionally doped layer 3 further includes: an overlap region 36, the overlap region 36 being disposed between the first doped region 32 and the second doped region 34, formed by the first doped region 32 overlapping the second doped region 34. Therefore, the first doped region 32 and the second doped region 34 are partially overlapped, and carrier injection in the channel region can effectively improve carrier concentration, so that channel mobility is improved, and the use performance of the device can be improved.
According to an embodiment of the present application, the width W1 of the overlapping region 36 may be 0.5 to 0.8 micrometers (specifically, 0.5 micrometers, 0.55 micrometers, 0.6 micrometers, 0.65 micrometers, 0.7 micrometers, 0.75 micrometers, 0.8 micrometers, etc.). Therefore, in the width range, the device can have proper starting voltage and loss at the same time, and if the width is too small compared with the width range, the device can be started in advance to influence the basic switching action of the device; if the width is too large, the turn-on voltage is relatively high and the loss is relatively large.
According to an embodiment of the present application, the portion between the first conductivity type heavily doped source region 346 and the first doped region 32 constitutes the channel of the VDMOSFET when the device structure does not include the overlap region, and the overlap region 36 constitutes the channel of the VDMOSFET when the device structure includes the overlap region 36. According to some embodiments of the present application, the channel length L may be 0.5 to 0.8 micrometers (e.g., 0.5 micrometers, 0.55 micrometers, 0.6 micrometers, 0.65 micrometers, 0.7 micrometers, 0.75 micrometers, 0.8 micrometers, etc.). Therefore, the length of a channel in the device is proper, short channel effect (the device is started in advance) cannot be caused, and the carrier concentration below the gate oxide layer cannot be too large to enable the gate oxide layer to bear larger voltage, so that the gate oxide layer is broken down in advance, and the withstand voltage of the device is reduced.
It will be understood by those skilled in the art that for a VDMOSFET, a JFET effect is generated when the VDMOSFET is turned on, i.e., a parasitic JFET (junction field effect transistor) in the VDMOSFET generates a partial on-resistance, thereby increasing the on-resistance of the VDMOSFET. While the first doped region 32 forms a JFET region according to the embodiments of the present disclosure using the device structure described above, in some embodiments, the width W2 of the first doped region 32 (i.e., the JFET region) may be 2 to 5 micrometers (specifically, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, etc.). Therefore, the breakdown resistance of the gate oxide layer can be ensured, meanwhile, the on-resistance is lower, and compared with the width range, if the JFET is too large in width, the voltage can be concentrated in the gate oxide layer area, so that the gate oxide layer is broken down in advance; if the JFET width is too small, the on-resistance of the device will increase relatively.
According to the embodiment of the application, the specific material of the gate oxide layer can be silicon oxide, silicon nitride and the like, and the thickness of the gate oxide layer can be 0.05 microns. Therefore, the dielectric ceramic has high voltage resistance and high breakdown resistance, and is beneficial to improving the service performance and reliability of devices.
In another aspect of the present application, the present application provides a method of fabricating the VDMOSFET described above. According to an embodiment of the present application, referring to fig. 4, the method comprises the steps of:
s1: a first-conductivity-type lightly doped layer 8 is formed on the upper surface of the first-conductivity-type heavily doped substrate 1, and the structural schematic diagram refers to fig. 5.
According to an embodiment of the present application, the first conductive-type lightly doped layer may be formed by an epitaxial method. Specifically, the epitaxial method may be formed by a deposition method, for example, including but not limited to chemical vapor deposition (cvd), and the like, such as Metal Organic Chemical Vapor Deposition (MOCVD), and the like. Therefore, the process is mature, the operation is simple and convenient, the doping concentration distribution in the formed first conductive type light doping layer is more uniform, and the service performance of the device is better.
S2: and performing ion implantation on the first conductive type lightly doped layer 8 to form a functional doped layer 3 and a first conductive type lightly doped drift layer 2, wherein the functional doped layer 3 is arranged on the upper surface of the first conductive type lightly doped drift layer 2, and the structural schematic diagram refers to fig. 6.
According to an embodiment of the present application, the specific step of forming the functional doping layer 3 may include:
s21: first ion implantation is performed on the first conductive-type lightly doped layer 8 to form a second conductive-type lightly doped well region 342.
According to an embodiment of the present application, the first ion implantation may specifically include forming a mask on the upper surface of the first conductive type lightly doped layer 8, specifically, forming a whole photoresist layer in advance, exposing and developing the photoresist to obtain a patterned photoresist (i.e., the mask), and then performing ion implantation on the upper surface of the first conductive type lightly doped layer 8, where specific implantation dose, implantation energy, and the like may be selected according to the doping concentration, the depth of the second conductive type lightly doped well region, and the like.
S22: second ion implantation is performed on the first conductive-type lightly doped layer 8 to form a second conductive-type lightly doped region 322.
According to an embodiment of the present application, the specific steps of the second ion implantation may be the same as those of the first ion implantation, and are not described in detail herein.
According to an embodiment of the present application, the first ion implantation and the second ion implantation are both first conductive type impurity implantation, and the doping concentrations of the second conductive type lightly doped region and the second conductive type lightly doped well region may be the same, at this time, the first ion implantation and the second ion implantation may be completed by one ion implantation, that is, the second conductive type lightly doped region and the second conductive type lightly doped well region are formed in one step by one ion implantation. Therefore, the preparation process can be saved, and the production cost can be reduced.
S23: a third ion implantation is performed on the first conductive lightly doped layer 8 to form a first conductive lightly doped region 324.
S24: fourth ion implantation is performed on the first conductive-type lightly doped layer 8 to form a first conductive-type heavily doped source region 346.
S25: fifth ion implantation is performed on the first conductive-type lightly doped layer 8 to form a second conductive-type heavily doped contact region 344.
According to an embodiment of the present application, the specific steps of the third ion implantation, the fourth ion implantation, and the fifth ion implantation may be the same as the first ion implantation, and are not described in detail herein.
According to an embodiment of the present application, when performing the third ion implantation, the ion implantation region may partially overlap with the second conductive lightly doped well region, so as to form an overlap region 36, and the structural schematic diagram refers to fig. 7.
S26: and annealing the product obtained after the fifth ion implantation.
According to embodiments of the present application, the annealing temperature may be in a range of 1600 degrees celsius to 1700 degrees celsius, such as 1600 degrees celsius, 1610 degrees celsius, 1620 degrees celsius, 1630 degrees celsius, 1640 degrees celsius, 1650 degrees celsius, 1660 degrees celsius, 1670 degrees celsius, 1680 degrees celsius, 1690 degrees celsius, 1700 degrees celsius, and the like. Therefore, the doped ions are distributed more uniformly, and the use performance of the device is improved.
S3: and forming a gate oxide layer 4 on part of the upper surface of the functional doping layer 3, wherein the structural schematic diagram refers to fig. 2 or fig. 3.
According to the embodiment of the application, the gate oxide layer may be formed by thermal oxidation growth (such as dry oxidation or wet oxidation), PECVD, and other methods in this step, and specific oxidation conditions, parameters, and the like may be flexibly selected by those skilled in the art according to actual needs, and are not described in detail herein.
S4: and forming a gate 5 on the upper surface of the gate oxide layer 4, wherein the structural schematic diagram refers to fig. 2 or fig. 3.
According to an embodiment of the present application, in this step, the gate may be formed by a first deposition method, such as chemical vapor deposition (e.g., evaporation, sputtering, etc.), physical vapor deposition, etc., and specific parameter conditions may be flexibly selected by those skilled in the art as needed, which is not described herein in detail.
S5: and forming a source electrode 6 on a part of the upper surface of the functional doping layer 3, and referring to fig. 2 or fig. 3 for a structural schematic diagram.
According to an embodiment of the present application, in this step, the source electrode may be formed by a second deposition method, such as chemical vapor deposition (e.g., evaporation, sputtering, etc.), physical vapor deposition, etc., and specific parameter conditions may be flexibly selected by those skilled in the art as needed, which is not described herein in detail.
S6: and forming a drain electrode 7 on the lower surface of the substrate 1, wherein the structural schematic diagram refers to fig. 2 or fig. 3.
According to an embodiment of the present application, the drain electrode may also be formed by a second deposition method in this step, such as chemical vapor deposition (e.g., evaporation, sputtering, etc.), physical vapor deposition, etc., and specific parameters and conditions may be flexibly selected by those skilled in the art as needed, which is not described herein in detail.
The method can be used for quickly and effectively preparing the VDMOSFET, has simple steps and convenient operation, and is easy to realize industrial production.
In yet another aspect of the present application, a semiconductor device is provided. According to an embodiment of the present application, the semiconductor device includes the VDMOSFET described above. The semiconductor device includes all the features and advantages of the VDMOSFET described above and will not be described in detail herein.
According to the embodiments of the present application, the specific types of the semiconductor device may be a MOSFET (metal-oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), and those skilled in the art will understand that the structure and components necessary for the conventional device are not described in detail herein, except for the VDMOSFET described above.
Embodiments of the present application are described in detail below.
Example 1:
step 1: epitaxially forming an N-type SIC doping layer 8 with the concentration of 1x10 on the heavily doped N + type SIC substrate 115cm-3The thickness is 10 microns, and the doping impurity is nitrogen (N);
step 2: ion implantation is carried out on the N-type SIC doping layer 8 to form a P-well region and a P-doping region with a super junction structure, and the implantation concentration is 2x1013cm-3The doping impurity is aluminum (Al);
and step 3: ion implantation is carried out on the N-type SIC doping layer 8 to form an N-doping area with a super junction structure, and the implantation concentration is 1.5x1013cm-3；
And 4, step 4: photoetching and injecting on the N-type SIC doping layer 8 to form a source region and a contact region; the doping concentration of the source region is 2x1015cm-3The doping concentration of the contact region is 1x1016cm-3(ii) a Carrying out high-temperature annealing after injection, wherein the annealing temperature is 1600 ℃;
and 5: forming a gate oxide layer by PECVD or thermal oxidation;
step 6: depositing to form a polysilicon gate;
and 7: and depositing metal Ni/Au to form a source electrode and a drain electrode, and obtaining a structural schematic diagram of the VDMOSFET shown in figure 2.
Example 2:
step 1: epitaxially forming an N-type SIC doping layer 8 with the concentration of 1x10 on a heavily doped N + type SIC substrate 115cm-3The thickness is 10 microns, and the doping impurity is nitrogen (N);
step 2: ion implantation is carried out on the N-type SIC doped layer 8 to form a P-well region and a super junctionA P-doped region formed by implanting 2 × 1013cm-3The doping impurity is aluminum (Al);
and step 3: ion implantation is carried out on the N-type SIC doping layer 8 to form an N-doping area with a super junction structure, and the implantation concentration is 1.5x1013cm-3(ii) a The overlapping widths with the P-well region are respectively 0.5 micron;
and 4, step 4: photoetching and injecting on the N-type SIC doping layer 8 to form a source region and a contact region; the doping concentration of the source region is 2x1015cm-3The doping concentration of the contact region is 1x1016cm-3(ii) a Carrying out high-temperature annealing after injection, wherein the annealing temperature is 1600 ℃;
and 5: forming a gate oxide layer by PECVD or thermal oxidation;
step 6: depositing to form a polysilicon gate;
and 7: and depositing metal Ni/Au to form a source electrode and a drain electrode, and obtaining a structural schematic diagram of the VDMOSFET shown in figure 3.
Example 3:
step 1: an N-type SIC doping layer 8 is formed on the heavily doped N + type SIC substrate 1 in an epitaxial mode; doping concentration of 1x1016cm-3The thickness is 12 microns, and the doping impurity is nitrogen (N);
step 2: ion implantation is carried out on the N-type SIC doping layer 8 to form a P-well region and a P-doping region with a super junction structure, and the implantation concentration is 3x1013cm-3The doping impurity is aluminum (Al);
and step 3: ion implantation is carried out on the N-type SIC doping layer 8 to form an N-doping area with a super junction structure, and the implantation concentration is 2.5x1013cm-3(ii) a The overlapping widths with the P-well region are respectively 0.5 micron;
and 4, step 4: forming source region and contact region by photolithography and implantation on the N-type SIC doping layer 8, wherein the doping concentration of the source region is 4x1015cm-3The doping concentration of the contact region is 2x1016cm-3(ii) a And carrying out high-temperature annealing after injection, wherein the annealing temperature is 1700 ℃;
and 5: forming a gate oxide layer by PECVD or thermal oxidation;
step 6: depositing to form a polysilicon gate;
and 7: and depositing metal Ni/Au to form a source electrode and a drain electrode, and obtaining a structural schematic diagram of the VDMOSFET shown in figure 3.
Comparative example 1
Step 1: an N-type SIC doping layer 20 is formed on the heavily doped N + type SIC substrate 10 in an epitaxial mode; doping concentration of 1x1016cm-3The thickness is 12 microns, and the doping impurity is nitrogen (N);
step 2: ion implantation is carried out on the N-type SIC doping layer 20 to form a P-well region 30 with the implantation concentration of 3x1013cm-3The doping impurity is aluminum (Al);
and step 3: forming source region and contact region by photolithography and implantation on the N-type SIC doping layer 20, wherein the doping concentration of the source region is 4x1015cm-3The doping concentration of the contact region is 2x1016cm-3(ii) a And carrying out high-temperature annealing after injection, wherein the annealing temperature is 1700 ℃;
and 4, step 4: forming a gate oxide layer by PECVD or thermal oxidation;
and 5: depositing to form a polysilicon gate;
step 6: and depositing metal Ni/Au to form a source electrode and a drain electrode, and obtaining the VDMOSFET with the structural schematic diagram shown in figure 1.
Performance testing
The silicon carbide VDMOSFETs obtained in the above examples and comparative examples were tested for VGS, Rdson and BVdss under the following test conditions:
vgs (th) (i.e. Vth): the turn-on voltage (threshold voltage) has a negative temperature characteristic. And (3) testing conditions are as follows: VGS ═ VDS, ID ═ 10 mA;
rds (on) (i.e., Rdson): under the condition of specific VGS and drain current (generally 1/2Rated ID), the impedance between the drain and the source when the MOSFET is conducted has positive temperature characteristic. And (3) testing conditions are as follows: VGS 20V, ID 40A;
v (BR) DSS (i.e., BVdss): and the drain-source (D-S) breakdown voltage has positive temperature characteristics. And (3) testing conditions are as follows: VGS ═ 0, ID ═ 100 μ a;
the test results are shown in Table 1.
TABLE 1
Parameter(s) Comparative example 1 Example 1 Example 2 Example 3
Vth 2.75 2.53 2.38 2.47
Rdson(mR) 85 60 42 38
BVdss(V) 1380 1532 1690 1547
From the above test results, compared with comparative example 1, the turn-on voltages Vth of the devices obtained in examples 1 to 3 are substantially equivalent, but the resistance Rdson between the drain and the source is significantly reduced (i.e., the on-resistance is reduced) when the devices are turned on, and the breakdown voltage BVdss is significantly increased (i.e., the withstand voltage is better), so that the devices of the present application can improve the withstand voltage of the devices and reduce the on-resistance at the same time under the same process conditions.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (13)

1. A VDMOSFET, comprising:
a first conductive type heavily doped substrate;
a first-conductivity-type lightly-doped drift layer disposed on an upper surface of the first-conductivity-type heavily-doped substrate;
a functional doping layer disposed on an upper surface of the first conductive type lightly doped drift layer and including a first doping region and a second doping region located outside the first doping region, wherein the second doping region includes a second conductive type lightly doped well region, a second conductive type heavily doped contact region and a first conductive type heavily doped source region, the second conductive type heavily doped contact region and the first conductive type heavily doped source region are disposed on a portion of an upper surface of the second conductive type lightly doped well region located outside, the second conductive type heavily doped contact region is located outside the first conductive type heavily doped source region, and the upper surface of the second conductive type contact region, the upper surface of the first conductive type heavily doped source region and the heavily doped well region of the second conductive type lightly doped well region are not covered by the second conductive type contact region and the first conductive type source region The upper surface is flush; the first doping area comprises a second conductive type lightly doped area and a first conductive type lightly doped area, and the first conductive type lightly doped area is arranged on the outer side of the second conductive type lightly doped area;
the gate oxide layer is arranged on the upper surface of the functional doping layer and covers the upper surface of the first doping region, the upper surface of the second conduction type lightly doped well region which is not covered by the second conduction type heavily doped contact region and the first conduction type heavily doped source region and the upper surface of part of the first conduction type heavily doped source region;
the grid electrode is arranged on the upper surface of the gate oxide layer;
the source electrode is arranged on the upper surface of the functional doping layer and covers the upper surface of the second conductive type heavily doped contact region and the upper surface of part of the second conductive type heavily doped source region;
a drain disposed on a lower surface of the substrate.
2. The VDMOSFET of claim 1, wherein the functionally doped layer further comprises:
an overlap region disposed between the first doped region and the second doped region and formed by the first doped region and the second doped region overlapping.
3. The VDMOSFET of claim 2, wherein the overlap region has a width of 0.5-0.8 μm.
4. The VDMOSFET of claim 1, wherein the lightly doped region of the second conductivity type has a doping concentration of 2 × 1013cm-3～3×1013cm-3。
5. The VDMOSFET of claim 1, wherein the lightly doped region of the first conductivity type has a doping concentration of 1.5 × 1013cm-3～2.5×1013cm-3。
6. The VDMOSFET of claim 1, wherein the channel length is between 0.5 and 0.8 microns.
7. The VDMOSFET of claim 1, wherein the first doped region has a width of 2-5 μm.
8. The VDMOSFET of claim 1, wherein at least one of the following conditions is satisfied:
the doping concentration of the first conductive type heavily doped substrate is 1.0 × 1018cm-3～1.0×1019cm-3；
The doping concentration of the first conduction type lightly doped drift layer is 1.0 × 1015cm-3～1.0×1016cm-3；
The thickness of the first conductive type lightly doped drift layer is 10-12 microns;
the doping concentration of the second conductive type lightly doped well region is 2.0 × 1013cm-3～3.0×1013cm-3；
The doping concentration of the second conductive type heavily doped contact region is 1.0 × 1016cm-3～2.0×1016cm-3；
The doping concentration of the first conductive type heavily doped source region is 2.0 × 1015cm-3～4.0×1015cm-3；
The thickness of the gate oxide layer is 0.045-0.08 micrometer.
9. A method of making the VDMOSFET of any one of claims 1-8, comprising:
forming a first conductive type lightly doped layer on an upper surface of the first conductive type heavily doped substrate;
performing ion implantation on the first conductive type lightly doped layer to form a functional doped layer and a first conductive type lightly doped drift layer, wherein the functional doped layer is arranged on the upper surface of the first conductive type lightly doped drift layer;
forming a gate oxide layer on a part of the upper surface of the functional doping layer;
forming a grid on the upper surface of the gate oxide layer;
forming a source electrode on a part of the upper surface of the functional doping layer;
forming a drain electrode on a lower surface of the substrate;
wherein the step of forming the functional doping layer comprises:
performing first ion implantation on the first conductive type lightly doped layer to form a second conductive type lightly doped well region;
performing second ion implantation on the first conductive type lightly doped layer to form a second conductive type lightly doped region;
performing third ion implantation on the first conductive type lightly doped layer to form a first conductive type lightly doped region;
performing fourth ion implantation on the first conductive type lightly doped layer to form a first conductive type heavily doped source region;
performing fifth ion implantation on the first conductive type lightly doped layer to form a second conductive type heavily doped contact region;
and annealing the product obtained after the fifth ion implantation.
10. The method of claim 9, wherein the first ion implantation and the second ion implantation are performed by a one-step ion implantation.
11. The method of claim 9, wherein the annealing temperature is 1600-1700 ℃.
12. The method of claim 9, wherein at least one of the following conditions is satisfied:
the gate oxide layer is formed by a PECVD or thermal oxidation method;
the gate electrode is formed by a first deposition method;
the source electrode and the drain electrode are formed by a second deposition method.
13. A semiconductor device characterized by comprising the VDMOSFET of any one of claims 1-8.
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CN114023809A (en) * 2021-11-10 2022-02-08 飞锃半导体（上海）有限公司 Semiconductor structure and forming method thereof
WO2024125297A1 (en) * 2022-12-13 2024-06-20 厦门芯达茂微电子有限公司 New sic mosfet device
CN118507529A (en) * 2024-07-19 2024-08-16 北京中科新微特科技开发股份有限公司 Power semiconductor device and method for manufacturing the same

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