CN111755464B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN111755464B CN111755464B CN202010601723.2A CN202010601723A CN111755464B CN 111755464 B CN111755464 B CN 111755464B CN 202010601723 A CN202010601723 A CN 202010601723A CN 111755464 B CN111755464 B CN 111755464B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
The invention discloses an array substrate and a display panel, wherein the array substrate comprises: a substrate base plate; at least one first thin film transistor and at least one second thin film transistor are located on one side of the substrate base plate; the active layer of the first thin film transistor is low-temperature polycrystalline silicon, the active layer of the second thin film transistor is an oxide semiconductor, the grid electrode of the second thin film transistor comprises a top grid electrode and a bottom grid electrode, and the top grid electrode and the bottom grid electrode are connected through a through hole; the grid electrode of the first thin film transistor and the grid electrode of the second thin film transistor are located on different layers, and the source electrode and the drain electrode of the first thin film transistor, the source electrode and the drain electrode of the second thin film transistor and the top grid electrode are located on the same layer. According to the technical scheme provided by the embodiment of the invention, the stability of the electrical performance of the driving circuit on the array substrate is improved through the second thin film transistor with the double-gate structure.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to an array substrate and a display panel.
Background
With the rapid development of the information technology era, the display panel is more and more widely applied to display devices such as smart phones, tablet computers and notebook computers.
The driving circuit of the display unit on the array substrate in the prior art display panel includes a low temperature polysilicon thin film transistor and a metal oxide thin film transistor. The metal oxide thin film transistor takes the metal oxide semiconductor layer as an active layer material of the thin film transistor, and has the optical characteristics of high carrier mobility, low deposition temperature, high transparency and the like. The low-temperature polycrystalline silicon thin film transistor has the advantages of high switching speed, thinner and smaller thin film circuit, lower power consumption and the like. However, in the existing array substrate, the metal oxide thin film transistor is of a single-gate structure, which causes unstable electrical performance of a driving circuit on the array substrate.
Disclosure of Invention
In view of this, embodiments of the present invention provide an array substrate and a display panel, which improve the stability of the electrical performance of a driving circuit on the array substrate.
An embodiment of the present invention provides an array substrate, including:
a substrate base plate;
at least one first thin film transistor and at least one second thin film transistor are located on one side of the substrate base plate; the active layer of the first thin film transistor is low-temperature polycrystalline silicon, the active layer of the second thin film transistor is an oxide semiconductor, the grid electrode of the second thin film transistor comprises a top grid electrode and a bottom grid electrode, and the top grid electrode and the bottom grid electrode are connected through a through hole;
the grid electrode of the first thin film transistor and the grid electrode of the second thin film transistor are located on different layers, and the source electrode and the drain electrode of the first thin film transistor, the source electrode and the drain electrode of the second thin film transistor and the top grid electrode are located on the same layer.
In this technical solution, the second thin film transistor includes a top gate and a bottom gate located at different layers, that is, the second thin film transistor is a thin film transistor with a dual gate structure. The top grid and the bottom grid simultaneously drive the active layer of the second thin film transistor, so that the carrier mobility of the thin film transistor can be greatly improved, the threshold voltage drift problem of the thin film transistor is solved, and the effect of improving the electrical property stability of the thin film transistor is achieved.
Optionally, the method further comprises: and the first electrode of the capacitor structure and the grid electrode of the first thin film transistor are positioned on the same layer, and the second electrode of the capacitor structure and the bottom grid electrode are positioned on the same layer.
According to the technical scheme, the capacitor structure is manufactured while the thin film transistor is manufactured, so that the effects of simplifying the process flow and reducing the cost are achieved.
Optionally, the device further includes a first signal trace and a second signal trace;
the first signal routing is used for providing an electric signal for the grid electrode of the second thin film transistor;
the second signal routing is used for providing electrical signals for the source electrode and the drain electrode of the second thin film transistor;
the overlapped part of the projection of the first signal wire on the substrate base plate and the projection of the second signal wire on the substrate base plate is positioned at different layers.
In the technical scheme, the first signal routing is used for providing an electric signal for the grid electrode of the second thin film transistor and controlling the second thin film transistor to be turned on or turned off. The second signal routing is used for providing power supply signals for the source electrode and the drain electrode of the second thin film transistor. According to the technical scheme, the overlapped parts of the projection of the first signal wiring on the substrate base plate 10 and the projection of the second signal wiring on the substrate base plate are positioned on different layers, so that mutual interference between electric signals of the first signal wiring and the second signal wiring can be avoided, and further the normal operation of the second thin film transistor is ensured, and the electrical stability of the driving circuit on the array base plate is ensured.
Optionally, a projection of the first signal trace on the substrate base plate and a projection of the second signal trace on the substrate base plate are perpendicular to each other.
According to the technical scheme, one second thin film transistor can be determined quickly and accurately, and electric signals are provided for the top grid electrode, the bottom grid electrode, the source electrode and the drain electrode of the second thin film transistor, so that the electric stability of the driving circuit on the array substrate is ensured.
Optionally, the first signal trace includes a first part of signal trace and a second part of signal trace;
the first part of signal routing and the top grid are positioned on the same layer and are connected with the top grid;
the second part of signal routing and the grid electrode of the first thin film transistor are positioned on the same layer or the same layer as the bottom grid electrode, the second part of signal routing is connected with the first part of signal routing through a via hole, and the projection of the second part of signal routing on the substrate base plate are overlapped;
the second signal routing is located on the same layer as the source electrode and the drain electrode of the second thin film transistor and connected with the source electrode and the drain electrode of the second thin film transistor.
According to the technical scheme, the projection of the second signal wiring on the substrate base plate is overlapped with the projection of the second signal wiring on the substrate base plate, but the second signal wiring and the grid electrode of the first thin film transistor are positioned on the same layer or on the same layer with the bottom grid electrode, the second signal wiring is connected with the first signal wiring through the via hole, the second signal wiring and the source electrode and the drain electrode of the second thin film transistor are positioned on the same layer, so that the overlapped part of the projection of the first signal wiring on the substrate base plate and the projection of the second signal wiring on the substrate base plate is positioned on different layers, mutual interference between electric signals of the first signal wiring and the second signal wiring can be avoided, the normal operation of the second thin film transistor is further ensured, and the electrical stability of the driving circuit on the array base plate is ensured.
Optionally, the second signal trace includes a third part of signal trace and a fourth part of signal trace;
the third part of signal routing and the source electrode and the drain electrode of the second thin film transistor are positioned on the same layer and are connected with the source electrode and the drain electrode of the second thin film transistor;
the fourth part of signal routing and the gate of the first thin film transistor are located on the same layer or the same layer as the bottom gate, the fourth part of signal routing is connected with the third part of signal routing through a via hole, and the projection of the fourth part of signal routing on the substrate base plate is overlapped with the projection of the first part of signal routing on the substrate base plate;
the first signal routing and the top grid are located on the same layer and are connected with the top grid.
According to the technical scheme, the projection of the fourth partial signal wiring on the substrate base plate is overlapped with the projection of the first partial signal wiring on the substrate base plate, the fourth partial signal wiring and the grid electrode of the first thin film transistor are located on the same layer or on the same layer with the bottom grid electrode, the fourth partial signal wiring is connected with the third partial signal wiring through the via hole, the first signal wiring and the top grid electrode are located on the same layer, the projection of the first signal wiring on the substrate base plate and the projection of the second signal wiring on the substrate base plate are overlapped, the mutual interference between the electric signals of the first signal wiring and the second signal wiring can be avoided, the normal operation of the second thin film transistor is further guaranteed, and the electrical stability of the driving circuit on the array base plate is guaranteed.
Optionally, the first signal trace and the bottom gate are located on the same layer or on the same layer as the gate of the first thin film transistor, the first signal trace is connected to the top gate through a via hole, and the second signal trace and the source and the drain of the second thin film transistor are located on the same layer and connected to the source and the drain of the second thin film transistor.
According to the technical scheme, the first signal wiring and the second signal wiring are located on different layers, mutual interference between electric signals of the first signal wiring and the second signal wiring can be avoided, and normal operation of the second thin film transistor is further ensured so as to ensure the electrical stability of the driving circuit on the array substrate
Optionally, the first thin film transistor includes a top gate structure or a bottom gate structure.
According to the technical scheme, the flexibility of the design scheme of the driving circuit on the array substrate is improved.
Optionally, a buffer layer, an active layer of the first thin film transistor, a first insulating layer, a gate of the first thin film transistor, a second insulating layer, the bottom gate, a third insulating layer, an active layer of the second thin film transistor, a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor, and the top gate are sequentially disposed on the substrate; the third insulating layer is provided with the via hole, and the bottom gate is connected with the top gate through the via hole.
According to the technical scheme, the bottom grid electrode is connected with the top grid electrode through the through hole, so that the active layer of the second thin film transistor is driven by the top grid electrode and the bottom grid electrode at the same time, the carrier mobility of the thin film transistor can be greatly improved, the problem of threshold voltage drift of the thin film transistor is solved, and the effect of improving the electrical property stability of the thin film transistor is achieved.
The embodiment of the invention also provides a display panel which comprises the array substrate in any of the technical schemes.
The second thin film transistor adopted by the display panel in the technical scheme comprises a top grid electrode and a bottom grid electrode which are positioned at different layers, namely the second thin film transistor is a thin film transistor with a double-grid structure. The active layer of the second thin film transistor is driven by the top grid and the bottom grid simultaneously, so that the carrier mobility of the thin film transistor can be greatly improved, the problem of threshold voltage drift of the thin film transistor is solved, the effect of improving the electrical property stability of the thin film transistor is achieved, and the electrical stability of a driving circuit on the array substrate and the stability of a display picture of the display panel are ensured. In the technical solution provided in this embodiment, the second thin film transistor includes a top gate and a bottom gate located at different layers, that is, the second thin film transistor is a thin film transistor with a dual gate structure. The active layer of the second thin film transistor is driven by the top grid and the bottom grid simultaneously, so that the carrier mobility of the thin film transistor can be greatly improved, the problem of threshold voltage drift of the thin film transistor is solved, and the effect of improving the electrical property stability of the thin film transistor is achieved. In addition, in the conventional array substrate, the gate electrode of the second thin film transistor and the source and drain electrodes of the second thin film transistor are respectively located at different layers, so that two mask plates are required to be used in the process of preparing the gate electrode of the second thin film transistor and the source and drain electrodes of the second thin film transistor. In the technical scheme provided by the embodiment, the source electrode and the drain electrode of the first thin film transistor, the source electrode and the drain electrode of the second thin film transistor and the top gate electrode are located on the same layer, and only one mask is needed in the process of preparing the source electrode and the drain electrode of the first thin film transistor, the source electrode and the drain electrode of the second thin film transistor and the top gate electrode, so that the number of masks used in the preparation process of the array substrate is reduced, the preparation process is simplified, and the production cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate in the prior art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 4 is a top view of a first signal trace and a second signal trace according to an embodiment of the present invention;
fig. 5 is a top view of another first signal trace and a second signal trace according to an embodiment of the present invention;
fig. 6 is a top view of a first signal trace and a second signal trace according to another embodiment of the present invention;
fig. 7 is a top view of a first signal trace and a second signal trace according to another embodiment of the present invention;
fig. 8 is a top view of a first signal trace and a second signal trace according to another embodiment of the present invention;
fig. 9 is a top view of a first signal trace and a second signal trace according to another embodiment of the present invention;
fig. 10 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the driving circuit on the conventional array substrate has unstable electrical performance. Fig. 1 is a schematic structural diagram of an array substrate in the prior art. Referring to fig. 1, for this reason, the conventional array substrate includes a substrate 10; a first thin film transistor 20 and a second thin film transistor 30 on one side of the substrate base plate 10; the active layer 21 of the first thin film transistor 20 is low temperature polysilicon, and the active layer 31 of the second thin film transistor 30 is an oxide semiconductor. In addition, the first thin film transistor 20 further includes a gate electrode 22, a source electrode 23A, and a drain electrode 23B. The second thin film transistor 30 further includes a gate electrode 32, a source electrode 33A, and a drain electrode 33B. Since the active layer 31 of the second thin film transistor 30 is an oxide semiconductor, which is sensitive to hydrogen and oxygen, the second thin film transistor 30 having a single gate structure has a weak carrier control capability with respect to the active layer 31, which causes a problem of low carrier mobility and a problem of drift in threshold voltage, thereby causing an unstable electrical property.
In view of the above technical problems, an embodiment of the present invention provides the following technical solutions:
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. Referring to fig. 2, the array substrate includes: a base substrate 10; at least one first thin film transistor 20 and at least one second thin film transistor 30 are located at one side of the substrate base plate 10; wherein the active layer 21 of the first thin film transistor 20 is low temperature polysilicon, the active layer 31 of the second thin film transistor 30 is oxide semiconductor, the gate of the second thin film transistor 30 includes a top gate 32A and a bottom gate 32B, and the top gate 32A and the bottom gate 32B are connected by a via hole (not shown); the gate 22 of the first thin film transistor 20 and the gate of the second thin film transistor 30 are located at different layers, and the source 23A and the drain 23B of the first thin film transistor 20, the source 33A and the drain 33B of the second thin film transistor 30, and the top gate 32A are located at the same layer.
Specifically, the gate 22 of the first thin film transistor 20 and the gate of the second thin film transistor 30 are located in different layers, so that the thicknesses of the respective film layers of the first thin film transistor 20 and the second thin film transistor 30 can be ensured to be in respective optimal ranges, and the problem that the thicknesses of the optimal film layers of the first thin film transistor 20 and the second thin film transistor 30 in the array substrate are not compatible is avoided, so as to fully exert the optimal effect of the first thin film transistor 20 and the second thin film transistor 30 in the array substrate.
It can be known that the active layer 21 of the first tft 20 is low-temperature polysilicon, which has high electron mobility and high switching speed. The conventional array substrate includes a substrate 10; a first thin film transistor 20 and a second thin film transistor 30 on one side of the substrate base plate 10; the active layer 21 of the first thin film transistor 20 is low-temperature polysilicon, and since the active layer 31 of the second thin film transistor 30 is an oxide semiconductor, which is sensitive to hydrogen and oxygen, the second thin film transistor 30 with a single-gate structure has a weak carrier control capability for the active layer 31, which causes poor carrier mobility and a drift problem of a threshold voltage, and further causes an unstable electrical performance of a driving circuit on the array substrate.
In the technical solution provided in this embodiment, the gate of the second thin film transistor 30 includes a top gate 32A and a bottom gate 32B, that is, the second thin film transistor 30 is a thin film transistor with a dual gate structure. The top grid 32A and the bottom grid 32B apply the same electric signal to drive the active layer 31 of the second thin film transistor 30, so that the carrier mobility of the thin film transistor can be greatly improved, the threshold voltage drift problem of the thin film transistor is solved, the effect of improving the electrical property stability of the thin film transistor is achieved, and the electrical property stability of the driving circuit on the array substrate is further improved. In addition, in the conventional array substrate, the gate of the second thin film transistor 30 and the source electrode 33A and the drain electrode 33B of the second thin film transistor 30 are respectively located at different layers, so that two masks are required to be used in the process of preparing the gate of the second thin film transistor 30 and the source electrode 33A and the drain electrode 33B of the second thin film transistor 30. In the technical scheme provided by this embodiment, the source 23A and the drain 23B of the first thin film transistor 20, the source 33A and the drain 33B of the second thin film transistor 30, and the top gate 32A are located on the same layer, and only one mask needs to be used in the process of preparing the source 23A and the drain 23B of the first thin film transistor 20, the source 33A and the drain 33B of the second thin film transistor 30, and the top gate 32A, so that the number of masks used in the preparation process of the array substrate is reduced, the preparation process is simplified, and the production cost is reduced.
Fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. Optionally, referring to fig. 3, the array substrate further includes: and at least one capacitor structure 40, wherein the first electrode 41 of the capacitor structure 40 and the gate 22 of the first thin film transistor 20 are located on the same layer, and the second electrode 42 of the capacitor structure 40 and the bottom gate 32B are located on the same layer.
Specifically, while the stability of the driving signal of the capacitor structure 40 is ensured, the first electrode 41 and the gate 22 of the first thin film transistor 20 are located on the same layer, the second electrode 42 of the capacitor structure 40 and the bottom gate 32B are located on the same layer, and only three metal film layers are needed in the process of preparing the thin film transistor and the capacitor structure 40, wherein a mask is used for one time in the process of patterning the first metal film layer M1, and the gate 22 of the first thin film transistor 20 and the first electrode 41 of the capacitor structure 40 are formed after patterning; a primary mask is used in the process of patterning the second metal film layer M2, and a second electrode of the capacitor structure 40 and a bottom gate 32B of the second thin film transistor 30 are formed after patterning; a mask is used once in the process of patterning the third metal film layer M3, and after patterning, the source 23A and the drain 23B of the first thin film transistor 20, the source 33A and the drain 33B of the second thin film transistor 30, and the top gate 32A are formed, so that the number of masks used in the preparation process of the array substrate is reduced, and the capacitor structure 40 is manufactured while the thin film transistor is manufactured, thereby achieving the effects of simplifying the process flow and reducing the cost.
In the above technical solution, the source 33A and the drain 33B of the second thin film transistor 30 and the top gate 32A are located at the same layer. In order to avoid that the signal traces of the source 33A and the drain 33B of the second thin film transistor 30 and the top gate 32A providing the electrical signals do not cross, the present embodiment further provides the following technical solutions:
fig. 4 is a top view of a first signal trace and a second signal trace according to an embodiment of the present invention.
Fig. 5 is a top view of another first signal trace and a second signal trace according to an embodiment of the disclosure. Fig. 6 is a top view of another first signal trace and a second signal trace according to an embodiment of the present invention. Fig. 7 is a top view of another first signal trace and a second signal trace according to an embodiment of the invention. Fig. 8 is a top view of another first signal trace and a second signal trace provided by an embodiment of the invention. Fig. 9 is a top view of still another first signal trace and a second signal trace according to an embodiment of the invention.
Optionally, referring to fig. 4 to 9, the array substrate further includes a first signal trace 51 and a second signal trace 52; the first signal trace 51 is used for providing an electrical signal to the gate of the second thin film transistor 30; the second signal trace 52 is used for providing an electrical signal for the source electrode 33A and the drain electrode 33B of the second thin film transistor 30; the portion of the projection of the first signal trace 51 on the substrate base plate 10 and the projection of the second signal trace 52 on the substrate base plate 10 are overlapped are located at different layers.
The first signal trace 51 is used for providing an electrical signal to the gate of the second thin film transistor 30, and controlling the second thin film transistor 30 to be turned on or off. The second signal trace 52 is used for providing a power supply signal for the source 33A and the drain 33B of the second thin film transistor 30. According to the above technical scheme, the overlapped portions of the projection of the first signal trace 51 on the substrate base plate 10 and the projection of the second signal trace 52 on the substrate base plate 10 are located at different layers, so that mutual interference between electrical signals of the first signal trace 51 and the second signal trace 52 can be avoided, and further the normal operation of the second thin film transistor 30 is ensured, so as to ensure the electrical stability of the driving circuit on the array base plate.
It should be noted that, for convenience of illustration, fig. 4 to 9 only show the first signal trace 51, the second signal trace 52, the top gate 32A of the second thin film transistor 30, the active layer 31 of the second thin film transistor 30, and the source 33A and the drain 33B of the second thin film transistor 30, and other layers are not shown except for the above layers. And the signal traces for providing the electrical signals for the gate 22 and the source 23A and the drain 23B of the first thin film transistor 20 are located at different layers, so that the technical problem of mutual crossing does not exist.
Illustratively, the first signal trace 51 may be a scan line, and the second signal trace 52 may be a data line or a power line.
Alternatively, referring to fig. 4 to 9, the projection of the first signal trace 51 on the substrate base 10 and the projection of the second signal trace 52 on the substrate base 10 are perpendicular to each other.
Specifically, the projection of the first signal trace 51 on the substrate 10 and the projection of the second signal trace 52 on the substrate 10 are perpendicular to each other, so that one second thin film transistor 20 can be determined quickly and accurately, and electrical signals are provided for the top gate 32A, the bottom gate 32B, the source 33A and the drain 33B of the second thin film transistor 30.
Optionally, referring to fig. 4 and 5, the first signal trace 51 includes a first portion of the signal trace 51A and a second portion of the signal trace 51B; the first part of signal routing 51A and the top gate 32A are located on the same layer and connected with the top gate 32A; the second part of the signal routing 51B and the gate 22 of the first thin film transistor 20 are located on the same layer, or located on the same layer as the bottom gate 32B, the second part of the signal routing 51B is connected with the first part of the signal routing 51A through the via 60, and the projection of the second part of the signal routing 51B on the substrate 10 overlaps with the projection of the second part of the signal routing 52 on the substrate 10; the second signal trace 52 is located on the same layer as the source 33A and the drain 33B of the second thin film transistor 30, and is connected to the source 33A and the drain 33B of the second thin film transistor 30.
It should be noted that only three metal film layers are required in the process of manufacturing the thin film transistor, wherein a primary mask is used in the process of patterning the first metal film layer M1, and the gate 22 of the first thin film transistor 20 is formed after patterning; a primary mask is used in the process of patterning the second metal film layer M2, and a bottom gate 32B of the second thin film transistor 30 is formed after patterning; a primary mask is used in the process of patterning the third metal film layer M3, and after patterning, the source 23A and the drain 23B of the first thin film transistor 20, the source 33A and the drain 33B of the second thin film transistor 30, and the top gate 32A are formed. In fig. 4, the first portion of the signal trace 51A and the top gate 32A are located on the same layer, and are connected to the top gate 32A, that is, obtained by patterning through the third metal layer M3. The second part of the signal trace 51B and the gate 22 of the first tft 20 are located on the same layer, i.e., patterned by the first metal layer M1. In fig. 5, the second portion of the signal trace 51B and the bottom gate 32B are located on the same layer, that is, patterned by the second metal layer M2. In fig. 4 and fig. 5, the second signal trace 52 is located on the same layer as the source 33A and the drain 33B of the second thin film transistor 30, that is, patterned by the third metal layer M3.
Specifically, the projection of the second signal trace 51B on the substrate 10 overlaps the projection of the second signal trace 52 on the substrate 10, but the second part of the signal trace 51B is located at the same layer as the gate 22 of the first tft 20 or at the same layer as the bottom gate 32B, the second part of the signal trace 51B is connected to the first part of the signal trace 51A through the via 60, the second signal trace 52 is located at the same layer as the source 33A and the drain 33B of the second tft 30, such that the portion of the projection of the first signal trace 51 on the substrate base 10 and the projection of the second signal trace 52 on the substrate base 10 overlap are located at different layers, mutual interference between the electrical signals of the first signal trace 51 and the second signal trace 52 can be avoided, and thus, the normal operation of the second thin film transistor 30 is ensured to ensure the electrical stability of the driving circuit on the array substrate.
Optionally, referring to fig. 6 and 7, the second signal trace 52 includes a third portion of the signal trace 52A and a fourth portion of the signal trace 52B; the third part of the signal routing 52A and the source 33A and the drain 33B of the second thin film transistor 30 are located on the same layer, and are connected with the source 33A and the drain 33B of the second thin film transistor 30; the fourth portion of the signal trace 52B and the gate 22 of the first thin film transistor 20 are located on the same layer, or located on the same layer as the bottom gate 32B, the fourth portion of the signal trace 52B is connected to the third portion of the signal trace 52A through the via 60, and a projection of the fourth portion of the signal trace 52B on the substrate 10 overlaps a projection of the first portion of the signal trace 51 on the substrate 10; the first signal trace 51 and the top gate 32A are located on the same layer, and are connected to the top gate 32A.
It should be noted that fig. 6 and fig. 7 show that the third portion of the signal trace 52A and the source 33A and the drain 33B of the second thin film transistor 30 are located at the same layer, and the third portion of the signal trace 52A is patterned by the third metal layer M3. The fourth portion of the signal trace 52B and the gate 22 of the first tft 20 are located on the same layer as shown in fig. 6, i.e., patterned by the first metal layer M1. The fourth portion of the signal trace 52B and the bottom gate 32B shown in fig. 7 are located on the same layer, i.e., patterned by the second metal layer M2.
Specifically, the projection of the fourth portion of the signal trace 52B on the substrate 10 overlaps the projection of the first signal trace 51 on the substrate 10, the fourth portion of the signal trace 52B and the gate 22 of the first thin film transistor 20 are located on the same layer, or are located on the same layer as the bottom gate 32B, the fourth portion of the signal trace 52B is connected to the third portion of the signal trace 52A through the via 60, and the first signal trace 51 and the top gate 32A are located on the same layer, so that the overlapping portion of the projection of the first signal trace 51 on the substrate 10 and the projection of the second signal trace 52 on the substrate 10 is located on the same layer, which can avoid the mutual interference between the electrical signals of the first signal trace 51 and the second signal trace 52, and further ensure the normal operation of the second thin film transistor 30, so as to ensure the electrical stability of the driving circuit on the array substrate.
Optionally, referring to fig. 8 and fig. 9, the first signal trace 51 and the bottom gate 32A or the gate 22 of the first thin film transistor 20 are located on the same layer, the first signal trace 51 is connected to the top gate 32A through the via 60, and the second signal trace 52 and the source 33A and the drain 33B of the second thin film transistor 30 are located on the same layer and connected to the source 33A and the drain 33B of the second thin film transistor 30.
It should be noted that the first signal trace 51 and the gate 22 of the first thin film transistor 20 shown in fig. 8 are located on the same layer, that is, the first signal trace 51 is patterned by the first metal layer M1. Fig. 9 shows that the first signal trace 51 and the bottom gate 32B are located on the same layer, i.e. the first signal trace 51 is patterned by the second metal layer M2. Fig. 8 and 9 show that the second signal trace 52 and the source 33A and the drain 33B of the second thin film transistor 30 are located at the same layer, i.e. the second signal trace 52 is patterned by the third metal layer M3.
According to the above technical scheme, the first signal trace 51 and the second signal trace 52 are located at different layers, so that mutual interference between electrical signals of the first signal trace 51 and the second signal trace 52 can be avoided, and further, normal operation of the second thin film transistor 30 is ensured, so that electrical stability of the driving circuit on the array substrate is ensured.
It should be noted that the first thin film transistor 20 provided in this embodiment may have a top gate structure or a bottom gate structure. In the array substrate exemplarily shown in fig. 2 and 3, the first thin film transistor 20 has a top gate structure. Fig. 10 exemplarily shows the array substrate in which the first thin film transistor 20 has a bottom gate structure.
The embodiment of the invention does not limit the position of the gate 22 of the first thin film transistor 20, and increases the flexibility of the design scheme of the driving circuit on the array substrate.
Fig. 11 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. Referring to fig. 11, a buffer layer 11, an active layer 21 of the first thin film transistor 20, a first insulating layer 12, a gate 22 of the first thin film transistor 20, a second insulating layer 13, a bottom gate 32B, a third insulating layer 14, an active layer 31 of the second thin film transistor 30, a fourth insulating layer 15, a source 23A and a drain 23B of the first thin film transistor 20, a source 33A and a drain 33B of the second thin film transistor 30, and a top gate 32A are sequentially disposed on the substrate 10; the third insulating layer 14 and the fourth insulating layer 15 are provided with a via hole 60, and the bottom gate 32B is connected to the top gate 32A through the via hole 60.
The buffer layer 11 and the insulating layer may be made of an inorganic material, or may be a stack of an inorganic material and an organic material. The thicknesses of the buffer layer 11 and the insulating layer may be selected by the practitioner according to the needs of the product.
Optionally, a passivation layer 16 is disposed over the first thin film transistor 20 and the second thin film transistor 30. The passivation layer 16 may further include a silicon nitride layer 16B and a silicon oxide layer 16A stacked together. Since the passivation layer 16 is located close to the second thin film transistor 30 in the spatial position from the active layer 32 of the second thin film transistor 30, for example, in the case where the passivation layer 16 includes the silicon nitride layer 16B and the silicon oxide layer 16A which are stacked, since the electrical properties change after hydrogenation considering that the active layer 32 of the second thin film transistor 30 is an oxide semiconductor, the silicon oxide layer 16A is disposed so as to be in contact with the source electrode 23A and the drain electrode 2B of the first thin film transistor 20 and the source electrode 33A and the drain electrode 33B of the second thin film transistor 30.
Optionally, referring to fig. 11, the array substrate further includes an organic light emitting display unit, an anode 70, a light emitting device layer 71, and a cathode 72 of the organic light emitting display unit, a pixel defining layer 73, and an isolation pillar 74. Wherein the anode 70 may be connected to the drain 23B of the first thin film transistor 20 or the drain 33B of the second thin film transistor 30 through the via 60. Fig. 11 schematically shows that the anode 70 may be connected to the drain 23B of the first thin film transistor 20 through the via 60. When the organic light emitting display panel emits light, under a certain voltage, electrons and holes are injected into the light emitting device layer 71 from the cathode 72 and the anode 70, respectively, and meet each other to form excitons and excite light emitting molecules, which emit visible light through radiative relaxation.
It should be noted that, in the embodiment of the present invention, the first thin film transistor 20 may be an NMOS transistor or a PMOS transistor, and the second thin film transistor 30 may also be an NMOS transistor or a PMOS transistor, and the channel types of the first thin film transistor 20 and the second thin film transistor 30 are not limited in the embodiment of the present invention.
In addition, the "same layer" in the embodiment of the present invention refers to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then performing a patterning process by using the same mask. Depending on the characteristic pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.
And the drawings provided by the embodiments of the present invention only show one first thin film transistor 20 and one second thin film transistor 30 and the first capacitor structure 40, the present invention does not limit the number of the first thin film transistor 20 and one second thin film transistor 30 and the first capacitor structure 40.
The embodiment of the invention also provides a display panel. As shown in fig. 12, the display panel includes the array substrate 100 according to any of the above embodiments. The display panel provided by the embodiment of the present invention includes the array substrate in the above embodiments, and therefore, the display panel provided by the embodiment of the present invention also has the beneficial effects described in the above embodiments, and details are not repeated herein. It should be noted that the display panel provided in the embodiment of the present invention may be an organic light emitting display panel, and may also be a liquid crystal display panel. Illustratively, the display panel may be any product or component with a display function, such as a notebook computer, a tablet computer, or a display.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (6)
1. An array substrate, comprising:
a substrate base plate;
at least one first thin film transistor and at least one second thin film transistor are located on one side of the substrate base plate; the active layer of the first thin film transistor is low-temperature polycrystalline silicon, the active layer of the second thin film transistor is an oxide semiconductor, the grid electrode of the second thin film transistor comprises a top grid electrode and a bottom grid electrode, and the top grid electrode and the bottom grid electrode are connected through a through hole;
the grid electrode of the first thin film transistor and the grid electrode of the second thin film transistor are positioned on different layers, and the source electrode and the drain electrode of the first thin film transistor, the source electrode and the drain electrode of the second thin film transistor and the top grid electrode are positioned on the same layer;
the circuit also comprises a first signal wire and a second signal wire;
the first signal routing is used for providing an electric signal for the grid electrode of the second thin film transistor;
the second signal routing is used for providing electrical signals for the source electrode and the drain electrode of the second thin film transistor;
the overlapped part of the projection of the first signal wire on the substrate base plate and the projection of the second signal wire on the substrate base plate is positioned at different layers;
the first signal routing comprises a first part of signal routing and a second part of signal routing;
the first part of signal routing and the top grid are positioned on the same layer and are connected with the top grid;
the second part of signal routing and the grid electrode of the first thin film transistor are positioned on the same layer or the same layer as the bottom grid electrode, the second part of signal routing is connected with the first part of signal routing through a via hole, and the projection of the second part of signal routing on the substrate base plate is overlapped with the projection of the second part of signal routing on the substrate base plate;
the second signal routing is positioned on the same layer as the source electrode and the drain electrode of the second thin film transistor and connected with the source electrode and the drain electrode of the second thin film transistor;
or the second signal traces include a third part of signal traces and a fourth part of signal traces;
the third part of signal routing and the source electrode and the drain electrode of the second thin film transistor are positioned on the same layer and are connected with the source electrode and the drain electrode of the second thin film transistor;
the fourth part of signal routing and the gate of the first thin film transistor are located on the same layer or the same layer as the bottom gate, the fourth part of signal routing is connected with the third part of signal routing through a via hole, and the projection of the fourth part of signal routing on the substrate base plate is overlapped with the projection of the first part of signal routing on the substrate base plate;
the first signal routing and the top grid are located on the same layer and are connected with the top grid.
2. The array substrate of claim 1, further comprising: and the first electrode of the capacitor structure and the grid electrode of the first thin film transistor are positioned on the same layer, and the second electrode of the capacitor structure and the bottom grid electrode are positioned on the same layer.
3. The array substrate of claim 1, wherein the projection of the first signal trace on the substrate and the projection of the second signal trace on the substrate are perpendicular to each other.
4. The array substrate of claim 1, wherein the first thin film transistor comprises a top gate structure or a bottom gate structure.
5. The array substrate of claim 4, wherein a buffer layer, an active layer of the first thin film transistor, a first insulating layer, a gate electrode of the first thin film transistor, a second insulating layer, the bottom gate electrode, a third insulating layer, an active layer of the second thin film transistor, a source electrode and a drain electrode of the first thin film transistor, a source electrode and a drain electrode of the second thin film transistor, and the top gate electrode are sequentially disposed on the substrate; the third insulating layer is provided with the via hole, and the bottom gate is connected with the top gate through the via hole.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
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| CN112420794B (en) * | 2020-11-18 | 2023-04-14 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN112542471A (en) * | 2020-12-04 | 2021-03-23 | 武汉华星光电半导体显示技术有限公司 | Preparation method of array substrate, array substrate and display panel |
| CN112735272B (en) | 2020-12-30 | 2022-05-17 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN114122007A (en) * | 2021-11-01 | 2022-03-01 | 深圳市华星光电半导体显示技术有限公司 | Array substrate |
| CN114361182A (en) * | 2021-12-17 | 2022-04-15 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and manufacturing method of array substrate |
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