CN111755338B - Atomic-level smooth electric connection sheet on surface of integrated device and preparation method thereof - Google Patents
Atomic-level smooth electric connection sheet on surface of integrated device and preparation method thereof Download PDFInfo
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- CN111755338B CN111755338B CN201910234423.2A CN201910234423A CN111755338B CN 111755338 B CN111755338 B CN 111755338B CN 201910234423 A CN201910234423 A CN 201910234423A CN 111755338 B CN111755338 B CN 111755338B
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- 238000000034 method Methods 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 19
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 10
- 229910021389 graphene Inorganic materials 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 229910002804 graphite Inorganic materials 0.000 claims description 6
- 239000010439 graphite Substances 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 239000010445 mica Substances 0.000 claims description 5
- 229910052618 mica group Inorganic materials 0.000 claims description 5
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 8
- 238000003672 processing method Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract 1
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- 230000008569 process Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 3
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- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000010944 silver (metal) Substances 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
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- 238000000151 deposition Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract
The invention provides a preparation method for forming an atomic-level smooth electric connection sheet on the surface of an integrated device, which utilizes a layer of removable material with an atomic-level smooth surface to carry out device integration on the surface of the material, and finally removes the material by an etching method through a reverse etching processing method, thereby obtaining an electric connection sheet structure with an integrated metal interconnection atomic-level smooth surface, and realizing different functions by integrating different devices.
Description
Technical Field
The invention relates to the technical field of micro-nano processing, in particular to a preparation method of an atomic-level smooth electric connection sheet on the surface of an integrated device designed and formed by a micro-processing technology.
Technical Field
With the continuous progress of the current technology, the application of the atomic-level flat surface is more and more extensive, such as a computer magnetic head, a magnetic disk, an integrated circuit chip, and the like, the atomic-level flat surface means a surface with a surface roughness less than 0.5nm and no step exceeding the atomic layer level, the atomic-level smooth surface has many excellent properties, and very precise control can be realized by extremely low fluctuation of the atomic-level smooth surface, for example: the distance between a reading head in the hard disk and the surface of the hard disk can be controlled at a nano-scale level all the time, and the distance is based on the surface of the hard disk at an atomic scale to a great extent; meanwhile, the atomically flat surface can form a super-lubrication phenomenon with extremely low friction and no abrasion with the graphite island, and the super-lubrication phenomenon can be widely applied to a plurality of industrial fields, see Chinese patents CN101794581B and CN 101941005B.
However, at present, an atomic-level flat surface only exists in a layered structure of a homogeneous material, and is difficult to realize for a device surface with a complex graphical heterostructure, and a final integrated device can be obtained by adopting a plurality of process steps from bottom to top in the traditional method, but the surface of the integrated device is difficult to achieve atomic-level flat. Due to the fact that in the growing and etching processes in the micromachining process, the growing conditions of different materials or the etching precision control is not enough, etching burrs exist at the edge of a heterogeneous material and are uneven, and the surface of a device with a final heterogeneous structure, particularly the surface at the edge, cannot form an atomically flat surface. In order to solve the above-mentioned problem of burrs or to achieve a smooth surface, a high-precision polishing apparatus and technique are required.
In short, the polishing process adopted for the surface of the device with the heterostructure has high precision control requirement and high equipment cost, and is difficult to form the atomic-level smooth electric connection sheet of the device with the heterostructure, so that a simple and convenient preparation method capable of solving the problem that the surface of the integrated device reaches the atomic-level smooth electric connection sheet is needed.
Disclosure of Invention
In order to obtain an atomic-level smooth surface of an integrated device and a relatively convenient processing method of the integrated device, the invention provides a method for performing reverse etching processing on an atomically removable flat material, which comprises the following steps: the method comprises the following steps of carrying out reverse process steps by utilizing a removable atomically flat silicon surface so as to realize the atomically flat surface of the structure, finally stabilizing by using resin, and removing silicon by using potassium hydroxide solution so as to obtain the atomically flat surface and the electric connection structure of the corresponding integrated device.
The process method adopted by the invention is a preparation method of an integrated device surface atomic-level smooth electric connection slice, and is characterized in that: the electric connection sheet comprises an electric connection structure formed on the ultra-smooth sheet, and the preparation method comprises the following steps:
forming an ultra-smooth sheet with an atomically flat surface on the surface of a substrate, wherein the ultra-smooth sheet is provided with a first surface in contact with the substrate and a second surface deviated from the substrate;
coating photoresist on the second surface of the ultra-smooth sheet, and patterning the photoresist to form an opening to expose part of the second surface of the ultra-smooth sheet;
step three, forming a conductive electric connection layer on the whole surface, wherein the electric connection layer is filled in the pattern opening of the photoresist and is formed on the second surface of the ultra-smooth sheet;
step four, adopting a stripping step to remove the photoresist and the electric connection layer thereon;
step five, coating the ultra-smooth sheet and the electric connection layer thereon with resin;
sixthly, removing the substrate and exposing the first surface of the ultra-smooth sheet;
and seventhly, removing the resin to form the ultra-smooth sheet with the electric connection layer.
The material of the substrate of the invention comprises one of Si, SiC, SOI, sapphire, mica, graphene and molybdenum disulfide or the combination thereof;
the ultra-smooth sheet material is a diamond-like carbon sheet, graphite or molybdenum disulfide, preferably a flaky diamond-like carbon sheet, flaky single crystal graphite or flaky single crystal molybdenum disulfide;
the material of the ultra-smooth thin sheet comprises SiO 2 、Si 3 N 4 And SiNO or a laminated structure composed of the above materials. The electric connection layer is one or a combination of Ni, Au, Ag and copper graphene composite materials.
The thickness of the electrical connection layer of the present invention is 10 to 150nm, preferably 20 to 50 nm.
The upper surface of the substrate of the present invention is a smooth flat surface.
The ultra-smooth sheet provided by the invention has at least one ultra-smooth surface, the ultra-smooth surface is an atomically smooth two-dimensional material, the diameter of the ultra-smooth surface is 1-100 mu m, and the thickness of the ultra-smooth sheet is 100 nm-10 mu m.
Finally, the resin coating layer may or may not be removed according to the actual use requirement of the ultra-smooth electrical connection sheet.
The invention also provides an atomically smooth electrical connection sheet for the surface of an integrated device, which comprises a substrate and an ultra-smooth sheet formed on the substrate, wherein a plurality of electrical connection structures are formed on the ultra-smooth sheet at intervals, the substrate is finally removed to expose the atomically smooth surface of the ultra-smooth sheet, the electrical connection sheet comprises the electrical connection structures formed on the ultra-smooth sheet, and the electrical connection sheet is prepared by the method of the embodiment.
Has the advantages that:
1. the method is simple and convenient, and avoids using polishing equipment and processing technology with ultrahigh requirements for obtaining a flat surface;
2. the method can efficiently obtain the atomic-level flat surface and has wide applicability.
Description of the drawings:
FIG. 1 shows a cross-sectional view of a prior art structure;
FIG. 2 illustrates prior structure processing steps;
FIG. 3 shows a topographic atomic force photo after stripping in a prior art, (a) a scanning area light mirror image; (b) scanning a two-dimensional graph at an AFM junction; (c) scanning a three-dimensional image at an AFM junction;
FIG. 4 illustrates a schematic diagram of a prior art burr formed; (a) a schematic structure diagram after the metal layer is evaporated; (b) the enlarged view in the red frame in (a) is that the photoresist at the edge of the electrode absorbs a small part of gold; (c) forming burrs on the edge after stripping;
FIG. 5 shows a prior art atomic force photo topography after lift-off; (a) scanning the regional picture; (b) scanning result 3D graph; (c) scanning a result 2D graph;
FIG. 6 illustrates process steps of the electrical connection structure of the present invention; (a) forming a super-smooth sheet on the substrate; (b) coating photoresist on the ultra-smooth sheet; (c) photoetching and patterning the photoresist to form an opening; (d) depositing to form an electric connection layer; (e) removing the photoresist by a stripping process; (f) pouring a resin covering layer to cover the upper surface; (g) removing the substrate material; (h) removing the resin covering layer;
fig. 7 shows a block flow diagram of the process for making an electrical connection structure of the present invention.
The specific implementation mode is as follows:
first, a structure having a metal electrode and an insulating layer is taken as an example to analyze the problems and disadvantages of the processes commonly used in the prior art.
Comparative example-a conventional method for obtaining atomically flat electrically connected flakes on a non-homogenous material surface.
The longitudinal section of the structure to be processed in the prior art is shown in fig. 1; wherein a patterned metal electrode structure is damascene-formed in an insulating layer and then a layer of Si is deposited thereover 3 N 4 The protective layer, generally takes the process steps as shown in fig. 2:
firstly, etching is carried out before growing metal, then metal is evaporated for filling, and the etching depth and the thickness of the grown metal can be accurately controlled, but after the whole process is finished, particularly after photoresist stripping, AFM observation shows that a plurality of burrs with the height of several nm to dozens of nm appear at the interface of the metal and silicon oxide, as shown in figure 3(c), the reason is that the metal is partially adhered at the edge of the photoresist pattern area during growth, as shown in figure 4, after the metal is evaporated, although the patterned electrode can be obtained by a stripping (Lift-off) process, because disturbance during evaporation inevitably generates some bulges near the metal edge due to the adsorption of the photoresist, and in the stripping process, the bulges can not be completely removed, so practical characterization of the burrs can be generated, as a result, as shown in fig. 4(c), these burrs cause undulation of the atomic-scale ultra-smooth surface to be formed later. That is, it is difficult for the hetero material layer itself to meet the requirement of leveling at an atomic level, that is, it is difficult to realize a smooth electrical connection sheet formed at a surface thereof with leveling at an atomic level. Even if a double-layer photoresist photoetching process is adopted, the phenomenon of burrs can be reduced to a certain extent, and the phenomenon that the adsorption phenomenon mainly occurs on the edge of the upper layer photoresist through the difference of the pattern widths of the two layers of photoresist so that the burrs adsorbed by the photoresist disappear. From the actual characterization results, it can be seen that although the burr on the edge is reduced to several nm as shown in fig. 5, the edge still has some gaps and extrusion due to the verticality of the electron beam evaporation and the non-verticality of the etched edge, and therefore, from the existing general process means, the limit is on the burr of several nm, and the requirement of an atomically flat surface is still not met.
Example a new method for obtaining atomically flat electrically connected sheets on a non-homogenous material surface.
A structure in which the metal electrode having the same structure in the comparative example was covered with the insulating resin covering layer was taken as an example. Firstly, a silicon wafer with an atomic-level smooth surface is used as a flat template, a layer of insulating material is deposited on the surface of the silicon wafer to form an electric connection slice, then the silicon wafer is polished to obtain a flat surface, a photoresist is coated on the surface, a designed pattern is carved by using an electron beam exposure method, then a layer of metal is deposited on the surface, the photoresist is completely removed by using a reactive ion etching method, a substrate insulating material is formed on the surface by injection molding, and finally the flat template silicon wafer is removed by using a potassium hydroxide solution through a chemical corrosion method to obtain a device of the atomic-level flat surface electric connection slice containing metal electrodes.
The preparation method comprises the following steps:
the method comprises the following steps of firstly, forming an ultra-smooth sheet (2) with an atomically flat surface on the surface of a substrate (1), wherein the ultra-smooth sheet (2) is provided with a first surface which is in contact with the substrate (1) and a second surface which is deviated from the substrate; the adopted substrate (1) material comprises one of Si, SiC, SOI, sapphire, mica, graphene and molybdenum disulfide or the combination of the Si, SiC, SOI, sapphire, mica, graphene and molybdenum disulfide, and the upper surface of the substrate (1) is a smooth plane; the ultra-smooth sheet (2) is made of a diamond-like carbon sheet, graphite or molybdenum disulfide, preferably a flaky diamond-like carbon sheet, flaky single crystal graphite or flaky single crystal molybdenum disulfide; the material of the ultra-smooth sheet (2) comprises SiO 2 、Si 3 N 4 And SiNO or a laminated structure composed of the above materials.
Coating a photoresist (3) on the second surface of the ultra-smooth sheet (2), and patterning the photoresist (3) to form an opening to expose part of the second surface of the ultra-smooth sheet (2).
Step three, forming a conductive electric connection layer (4) on the whole surface, wherein the electric connection layer (4) is filled in a pattern opening of the photoresist (3) and is formed on the second surface of the ultra-smooth sheet; the electric connection layer (4) is one or a combination of Ni, Au, Ag and copper graphene composite materials; the thickness of the electric connection layer (4) is 10-150nm, preferably 20-50 nm.
And step four, removing the photoresist (3) and the electric connection layer (4) on the photoresist by adopting a stripping step.
And step five, coating the ultra-smooth sheet (2) and the electric connection layer (4) thereon by using a resin coating layer (5).
And sixthly, removing the substrate to expose the first surface of the ultra-smooth sheet (2), thereby forming the ultra-smooth sheet with the electric connection layer (4). The ultra-smooth sheet (2) is provided with at least one ultra-smooth surface, the ultra-smooth surface is an atomically smooth two-dimensional material, the diameter of the ultra-smooth surface is 1-100 mu m, and the thickness of the ultra-smooth sheet (2) is 100 nm-10 mu m.
Finally, the resin coating layer (5) may or may not be removed according to the actual use requirement of the ultra-smooth electrical connection sheet.
Therefore, by adopting the process method of the invention, the specific process steps are shown in fig. 7, and the atomic-level flat surface of the heterostructure can be realized. The whole process is reversed by utilizing the atomic-level flattening of the surface of the silicon which can be removed, finally, resin is used for stabilizing, and the silicon is removed by using potassium hydroxide solution to obtain the surface with the atomic-level flattening and the same electrode structure. The method is simple and convenient, and does not adopt a polishing process for the surface of the heterostructure, thereby avoiding using polishing equipment and processing technology with ultra-high requirements for obtaining an ultra-smooth flat surface; can efficiently obtain an atomic-level flat surface and has wide applicability.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the disclosure of the present invention should be included in the scope of the present invention as set forth in the appended claims.
Claims (10)
1. A method for preparing an atomic-level smooth electric connection sheet on the surface of an integrated device is characterized by comprising the following steps: the electric connection sheet comprises an electric connection structure formed on an ultra-smooth sheet (2), and the preparation method comprises the following steps:
firstly, forming an ultra-smooth sheet (2) with an atomically flat surface on the surface of a substrate (1), wherein the upper surface of the substrate (1) is a smooth plane, the ultra-smooth sheet (2) is provided with a first surface which is in contact with the substrate (1) and a second surface which is deviated from the substrate (1), and the first surface of the ultra-smooth sheet (2) is an ultra-smooth surface;
coating a photoresist (3) on the second surface of the ultra-smooth sheet (2), and patterning the photoresist (3) to form an opening to expose part of the second surface of the ultra-smooth sheet (2);
forming a conductive electric connection layer (4) on the whole surface, wherein the electric connection layer (4) is filled in a pattern opening of the photoresist (3) and is formed on the second surface of the ultra-smooth sheet (2);
step four, removing the photoresist (3) and the electric connection layer (4) thereon by adopting a stripping step;
step five, coating the ultra-smooth sheet (2) and the electric connection layer (4) on the ultra-smooth sheet by using a resin covering layer (5);
and sixthly, removing the substrate (1), exposing the first surface of the ultra-smooth sheet (2), and forming the ultra-smooth sheet (2) with the electric connection layer (4).
2. The method of claim 1, wherein: the material of the substrate (1) comprises one of Si, SiC, SOI, sapphire, mica, graphene and molybdenum disulfide or the combination of the Si, SiC, SOI, sapphire, mica, graphene and molybdenum disulfide.
3. The method of claim 1, wherein: the ultra-smooth sheet (2) is made of sheet diamond-like carbon, sheet single crystal graphite or sheet single crystal molybdenum disulfide.
4. The method of claim 1, wherein: the material of the ultra-smooth sheet (2) comprises SiO 2 、Si 3 N 4 And SiNO or a laminated structure composed of the above materials.
5. The method of claim 1, wherein: the electric connection layer (4) is one or a combination of Ni, Au, Ag and copper graphene composite materials.
6. The method of claim 5, wherein: the thickness of the electric connection layer (4) is 10-150 nm.
7. The method of claim 6, wherein: the thickness of the electric connection layer (4) is 20-50 nm.
8. The method of claim 1, wherein: further comprising removing the resin covering layer (5).
9. The method of any one of claims 1 to 8, wherein: the ultra-smooth surface is an atomically smooth two-dimensional material, the diameter of the ultra-smooth surface is 1-100 mu m, and the thickness of the ultra-smooth sheet (2) is 100 nm-10 mu m.
10. An atomically smooth electrical connection sheet for an integrated device surface, the electrical connection sheet comprising a substrate (1) and an ultra-smooth sheet (2) formed on the substrate (1), a plurality of electrical connection structures being formed on the ultra-smooth sheet (2) at intervals, the substrate (1) being eventually removed to expose the atomically smooth surface of the ultra-smooth sheet (2), the electrical connection sheet comprising electrical connection structures formed on the ultra-smooth sheet (2), characterized in that: the atomically smooth electrically connected flakes are prepared by the method of any of claims 1-9.
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| CN101950644A (en) * | 2010-09-09 | 2011-01-19 | 西北工业大学 | Manufacturing method of flexible heat-sensitive thin film resistor array |
| CN105070347A (en) * | 2015-08-17 | 2015-11-18 | 中国科学院上海微系统与信息技术研究所 | Device structure with grapheme as contact electrode and manufacturing method thereof |
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| US7198970B2 (en) * | 2004-01-23 | 2007-04-03 | The United States Of America As Represented By The Secretary Of The Navy | Technique for perfecting the active regions of wide bandgap semiconductor nitride devices |
| CN102867740B (en) * | 2011-07-05 | 2015-08-12 | 中国科学院金属研究所 | A kind of graphic method of harmless, free of contamination nanometer carbon film |
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