CN111755035A - Power chip management system and method - Google Patents
Power chip management system and method Download PDFInfo
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- CN111755035A CN111755035A CN202010492809.6A CN202010492809A CN111755035A CN 111755035 A CN111755035 A CN 111755035A CN 202010492809 A CN202010492809 A CN 202010492809A CN 111755035 A CN111755035 A CN 111755035A
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Abstract
The invention relates to the technical field of power chips and discloses a power chip management system which comprises a power starting/low voltage detection circuit, a voltage conversion circuit, three driving circuits, a logic control circuit and a random access memory protection circuit, wherein the power starting/low voltage detection circuit is connected with the three driving circuits; the input end of the power supply starting/low voltage detection circuit is connected with the output end of the logic control circuit, and the output end of the power supply starting/low voltage detection circuit is connected with an external digital logic circuit/MCU; and the output end of the digital logic circuit/MCU is connected with the input end of the logic control circuit. The invention achieves the purpose of stable work of the system by providing stable voltage for the power supply chip, can also carry out low-voltage detection and protect the content in the memory, and in addition, realizes the dynamic control of the MCU module in the SOC on the voltage conversion, is beneficial to reducing the power consumption of the system, and is very key for the application of the SOC in an embedded system powered by a battery.
Description
Technical Field
The invention relates to the technical field of power chips, in particular to a power chip management system and a power chip management method.
Background
With the rapid development of integrated circuit design technology and ultra-deep submicron technology, the integrated circuit design has been advanced into the System-On-Chip (SOC) era, and the SOC can integrate the functional modules of digital circuits and analog circuits such as embedded microprocessors, memories, interface circuits, clock circuits and the like On a single silicon Chip, thereby realizing a complete electronic System function. The system has the characteristics of high integration level and high clock frequency, so that the appearance of the SOC puts higher requirements on a power supply for providing energy.
The existing power supply chip has many disadvantages, for example, the change of the power supply voltage can cause the digital circuit not to meet the timing requirement, so that the system can not work normally; in addition, when the voltage is too low, the content in the Random Access Memory (RAM) is damaged, which causes abnormal operation of the chip, and the power management system is introduced to solve the above problems, and especially in the mobile embedded application system which is applied more and more widely and uses the battery as the power supply, the power management is particularly important, and therefore, a power chip management system and a method are provided.
Disclosure of Invention
In view of the above problems in the prior art, the present invention provides a power chip management system and method.
In order to achieve the above object, the present invention provides a power chip management system, which comprises a power start/low voltage detection circuit, a voltage conversion circuit, three driving circuits, a logic control circuit and a random access memory protection circuit; the input end of the power supply starting/low voltage detection circuit is connected with the output end of the logic control circuit, and the output end of the power supply starting/low voltage detection circuit is connected with an external digital logic circuit/MCU; the output end of the digital logic circuit/MCU is connected with the input end of the logic control circuit; the logic control circuit is connected with the voltage conversion circuit in a bidirectional way; the output end of the voltage conversion circuit is respectively connected with the input ends of the three driving circuits; the driving circuit comprises a first driving circuit, a second driving circuit and a third driving circuit, wherein the output end of the first driving circuit is connected with the digital logic circuit/MCU, the output end of the second driving circuit is connected with an external phase-locked loop circuit, and the output end of the third driving circuit is connected with an external memory; the input end and the output end of the random access memory protection circuit are respectively connected with the logic control circuit and the external random access memory, and the input end of the random access memory protection circuit is connected with the first driving circuit.
Preferably, the power supply start/low voltage detection circuit comprises a power supply start circuit and a low voltage detection circuit; the power supply starting circuit comprises a power supply starting signal latch circuit, when an external voltage (Vddpall) rises from zero to a certain low voltage, a current reference signal (Iref) and a voltage reference signal (Vstopbias) have initial values, at the moment, a signal Por _ set is placed at a high level, the power supply starting signal latch circuit is stimulated to latch the signal Por _ set and generate a power supply starting signal (Por: PowerOnReset), the system is started, the external voltage continues to rise, after a certain value, the Por _ set is placed at a low level, but the power supply starting signal is kept effective because the power supply starting signal latch circuit latches the initial high level, and after the system is started, a logic control circuit generates a power supply starting release signal (Por _ realasc), so that the system starting process is finished after Por is released; the low-voltage detection circuit is composed of a voltage reference circuit, a comparator and a voltage division circuit, wherein the internal voltage Vregd is a voltage for supplying power to an MCU and an RAM in the SOC, and when the value of the internal voltage Vregd is reduced to a certain value, Vx is smaller than Vref, a low-voltage event signal is generated and is sent to a system, and low-voltage restart or interruption of the system is realized.
Preferably, the driving circuit adjusts the voltage Vnominal provided by the voltage conversion circuit to increase the driving capability, so as to achieve the driving purpose.
Preferably, the random access memory protection circuit comprises a comparator, a control circuit and a switch circuit, when the applied voltage Vstby is normal, the Vstby passes through the NMOS tube and the switch circuit and is output from a Vregr terminal, when the Vstby voltage is lower than Vregd, Vstyref is in a low level, Vregd passes through the switch circuit and is output from the Vregr terminal, the purpose of protecting the memory is achieved, and a high level flag signal Stby _ b is generated to indicate that the memory is supplied by the Vregd.
Preferably, the logic control circuit comprises a rewrite circuit, a state control circuit, an analog control circuit, a low voltage logic circuit and a restart control circuit, the restart control circuit receives a power supply start signal and a low voltage restart signal generated by the low voltage logic control circuit, generates a control signal to the rewrite circuit, the rewrite circuit completes the initial value setting of each state control bit when the system is started, if the power supply is started, after the rewrite is completed, the rewrite circuit receives the power supply start completion signal of the system, generates a power supply start release signal to the power supply start circuit, releases the power supply start signal, the low voltage logic control circuit receives a low voltage event signal, and determines whether the system is to restart at low voltage or interrupt at low voltage according to the state control signal provided by the MCU, the state control circuit generates a control signal to the analog control circuit and the voltage conversion circuit, and performing state control, wherein the analog control circuit receives the control signal, performs logic conversion and generates an enable signal of an analog part in the power management chip.
Preferably, the voltage conversion circuit comprises an auxiliary module, three oscillators, three feedback circuits and three pump circuits, and dynamically converts the external power supply voltage under the control of the logic control circuit to provide a stable voltage Vnominal to the driving circuit; the oscillator generates square waves according to an external voltage signal and reference voltage generated by a power management chip and provides the square waves to the pump circuit, the pump circuit receives the square waves from the oscillator and outputs relatively stable voltage Vnnina 1, and in order to obtain stable Vominal, the oscillator circuit and the pump circuit are required to complement each other so as to finally output stable voltage, the three feedback circuits respectively monitor the output voltages of the three driving circuits, and transmit control signals to the oscillator to adjust the working state of the oscillator, so that the purpose of adjusting the voltage is achieved.
A method for a power chip management system comprises the following specific steps:
(1) the power supply starting circuit is responsible for starting and restarting a power supply and generating a power supply starting signal;
(2) the low voltage detection circuit monitors an internal power supply (Vregd) and generates a low voltage event signal;
(3) the voltage conversion circuit converts an external power supply under the control of the logic control circuit, provides voltage (Vnominal) to the driving circuits, and the three driving circuits respectively provide power supply voltage for an internal memory, a phase-locked loop and a Microcontroller (MCU) in the power supply chip;
(4) the logic control circuit is mutually associated with the MCU, the power supply starting circuit and the low voltage detection circuit to control the voltage conversion circuit, so that the aim of determining the working state of the power supply management module is fulfilled, and the dynamic management of the power supply is realized;
(5) the random memory protection circuit selects between the voltage Vregd and Vstby according to the condition of the external actual voltage, and provides an uninterrupted power supply for the memory to protect the content from being damaged.
Compared with the prior art, the power chip management system and the power chip management method provided by the invention have the following beneficial effects:
the invention manages the external power supply by a dynamic method to realize stable system power supply, can provide stable voltage for a power supply chip to achieve the aim of stable work of the system, can also carry out low-voltage detection and protect the content in a memory, and also realizes the dynamic control of the MCU module in the SOC on voltage conversion, thereby being beneficial to reducing the power consumption of the system and being very key to the application of the SOC in an embedded system powered by a battery.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a schematic diagram of a power supply startup circuit of the present invention;
FIG. 3 is a schematic diagram of a low voltage detection circuit according to the present invention;
FIG. 4 is a schematic diagram of I-V characteristics of the driving circuit and its output according to the present invention;
FIG. 5 is a schematic diagram of a random access memory protection circuit according to the present invention;
FIG. 6 is a schematic diagram of a logic control circuit according to the present invention;
FIG. 7 is a schematic diagram of a voltage conversion circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure.
Referring to fig. 1-7, a power chip management system includes a power on/low voltage detection circuit, a voltage conversion circuit, three driving circuits, a logic control circuit, and a ram protection circuit; the input end of the power supply starting/low voltage detection circuit is connected with the output end of the logic control circuit, and the output end of the power supply starting/low voltage detection circuit is connected with an external digital logic circuit/MCU; the output end of the digital logic circuit/MCU is connected with the input end of the logic control circuit; the logic control circuit is connected with the voltage conversion circuit in a bidirectional way; the output end of the voltage conversion circuit is respectively connected with the input ends of the three driving circuits; the driving circuit comprises a first driving circuit, a second driving circuit and a third driving circuit, wherein the output end of the first driving circuit is connected with the digital logic circuit/MCU, the output end of the second driving circuit is connected with an external phase-locked loop circuit, and the output end of the third driving circuit is connected with an external memory; the input end and the output end of the random access memory protection circuit are respectively connected with the logic control circuit and the external random access memory, and the input end of the random access memory protection circuit is connected with the first driving circuit.
The power supply starting/low voltage detection circuit comprises a power supply starting circuit and a low voltage detection circuit; the power supply starting circuit comprises a power supply starting signal latch circuit, when an external voltage (Vddpall) rises from zero to a certain low voltage, a current reference signal (Iref) and a voltage reference signal (Vstopbias) have initial values, at the moment, a signal Por _ set is placed at a high level, the power supply starting signal latch circuit is stimulated to latch the signal Por _ set and generate a power supply starting signal (Por: PowerOnReset), the system is started, the external voltage continues to rise, after a certain value, the Por _ set is placed at a low level, but the power supply starting signal is kept effective because the power supply starting signal latch circuit latches the initial high level, and after the system is started, a logic control circuit generates a power supply starting release signal (Por _ realasc), so that the system starting process is finished after Por is released; the low-voltage detection circuit is composed of a voltage reference circuit, a comparator and a voltage division circuit, wherein the internal voltage Vregd is a voltage for supplying power to an MCU and an RAM in the SOC, and when the value of the internal voltage Vregd is reduced to a certain value, Vx is smaller than Vref, a low-voltage event signal is generated and is sent to a system, and low-voltage restart or interruption of the system is realized.
The driving circuit adjusts the voltage Vnominal provided by the voltage conversion circuit and increases the driving capability to realize the driving purpose, the driving circuit is composed of an NMOS adopting a source electrode following connection method and a bypass capacitor, the size of the NMOS needs to be noticed during design, and the NMOS is enabled to work in a weak inversion region, the circuit structure has the greatest advantage that a large output current can be obtained without a large input current, for example, a 50mA output current is obtained, if a bipolar transistor with a gain of 100 is used, a 500uA input current is needed, and if an NMOS tube working in the weak inversion region is used, a large input current is not needed, an A-B curve in figure 4 is close to a straight line and is the weak inversion region of the NMOS tube.
The random access memory protection circuit comprises a comparator, a control circuit and a switch circuit, when an applied voltage Vstby is normal, the Vstby passes through an NMOS tube and the switch circuit and is output from a Vregr end, when the Vstby voltage is lower than Vregd, Vstbyref is in a low level, the Vregd passes through the switch circuit and is output from the Vregr end, the purpose of protecting the memory is achieved, and a high-level mark signal Stby _ b is generated to indicate that the memory is powered by the Vregd.
The logic control circuit comprises a rewriting circuit, a state control circuit, an analog control circuit, a low-voltage logic circuit and a restarting control circuit, wherein the restarting control circuit receives a power supply starting signal and a low-voltage restarting signal generated by the low-voltage logic control circuit and generates a control signal to the rewriting circuit, the rewriting circuit completes the initial value setting of each state control bit when the system is started, if the power supply is started, after the rewriting is completed, the rewriting circuit receives the power supply starting completion signal of the system, generates a power supply starting release signal to the power supply starting circuit and releases the power supply starting signal, the low-voltage logic control circuit receives a low-voltage event signal and determines whether the system is restarted at low voltage or interrupted according to the state control signal provided by the MCU, and the state control circuit generates the control signal to the analog control circuit and the voltage conversion circuit, and performing state control, wherein the analog control circuit receives the control signal, performs logic conversion and generates an enable signal of an analog part in the power management chip.
The voltage conversion circuit comprises an auxiliary module, three oscillators, three feedback circuits and three pump circuits, and dynamically converts the voltage of an external power supply under the control of the logic control circuit to provide stable voltage Vnominal for the driving circuit; the oscillator generates square waves according to an external voltage signal and reference voltage generated by a power management chip and provides the square waves to the pump circuit, the pump circuit receives the square waves from the oscillator and outputs relatively stable voltage Vnnina 1, and in order to obtain stable Vominal, the oscillator circuit and the pump circuit are required to complement each other so as to finally output stable voltage, the three feedback circuits respectively monitor the output voltages of the three driving circuits, and transmit control signals to the oscillator to adjust the working state of the oscillator, so that the purpose of adjusting the voltage is achieved.
A method for a power chip management system comprises the following specific steps:
(1) the power supply starting circuit is responsible for starting and restarting a power supply and generating a power supply starting signal;
(2) the low voltage detection circuit monitors an internal power supply (Vregd) and generates a low voltage event signal;
(3) the voltage conversion circuit converts an external power supply under the control of the logic control circuit, provides voltage (Vnominal) to the driving circuits, and the three driving circuits respectively provide power supply voltage for an internal memory, a phase-locked loop and a Microcontroller (MCU) in the power supply chip;
(4) the logic control circuit is mutually associated with the MCU, the power supply starting circuit and the low voltage detection circuit to control the voltage conversion circuit, so that the aim of determining the working state of the power supply management module is fulfilled, and the dynamic management of the power supply is realized;
(5) the random memory protection circuit selects between the voltage Vregd and Vstby according to the condition of the external actual voltage, and provides an uninterrupted power supply for the memory to protect the content from being damaged.
It should be noted that Vdd in the figure is an external voltage for supplying power to digital logic circuits such as MCU, Vddpll is an external voltage for supplying power to analog circuits such as pll, Vddf is an external voltage for supplying power to memory, Vstby is an external voltage for supplying power to memory, Vregd converts an internal voltage for supplying power to digital circuits such as MCU, Vregpll converts an internal voltage for supplying power to analog circuits such as pll, Vreg converts an internal voltage for supplying power to memory, Vregr converts an internal voltage for supplying power to memory, and Stby _ b is a flag signal when power is supplied to memory.
The invention manages the external power supply by a dynamic method to realize stable system power supply, can provide stable voltage for a power supply chip to achieve the aim of stable work of the system, can also carry out low-voltage detection and protect the content in a memory, and also realizes the dynamic control of the MCU module in the SOC on voltage conversion, thereby being beneficial to reducing the power consumption of the system and being very key to the application of the SOC in an embedded system powered by a battery.
The above description is only an exemplary embodiment of the present invention, and is not intended to limit the present invention, the scope of which is defined by the claims. Various modifications and equivalents may be made by those skilled in the art within the spirit and scope of the present invention, and such modifications and equivalents should also be considered as falling within the scope of the present invention.
Claims (7)
1. A power chip management system is characterized by comprising a power starting/low voltage detection circuit, a voltage conversion circuit, three driving circuits, a logic control circuit and a random access memory protection circuit;
the input end of the power supply starting/low voltage detection circuit is connected with the output end of the logic control circuit, and the output end of the power supply starting/low voltage detection circuit is connected with an external digital logic circuit/MCU;
the output end of the digital logic circuit/MCU is connected with the input end of the logic control circuit;
the logic control circuit is connected with the voltage conversion circuit in a bidirectional way;
the output end of the voltage conversion circuit is respectively connected with the input ends of the three driving circuits;
the driving circuit comprises a first driving circuit, a second driving circuit and a third driving circuit, wherein the output end of the first driving circuit is connected with the digital logic circuit/MCU, the output end of the second driving circuit is connected with an external phase-locked loop circuit, and the output end of the third driving circuit is connected with an external memory;
the input end and the output end of the random access memory protection circuit are respectively connected with the logic control circuit and the external random access memory, and the input end of the random access memory protection circuit is connected with the first driving circuit.
2. The power chip management system according to claim 1, wherein the power on/low voltage detection circuit comprises a power on circuit and a low voltage detection circuit;
the Power supply starting circuit comprises a Power supply starting signal latch circuit, when an external voltage (Vddpall) rises from zero to a certain low voltage, a current reference signal (Iref) and a voltage reference signal (Vstopbias) have initial values, at the moment, a signal Por _ set is placed at a high level, the Power supply starting signal latch circuit is stimulated to latch the signal Por _ set and generate a Power supply starting signal (Por: Power On Reset), the system is started, the external voltage continues rising, after a certain value, the Por _ set is placed at a low level, but the Power supply starting signal latch circuit latches the initial high level, so that the Power supply starting signal is kept effective, and after the system is started, a logic control circuit generates a Power supply starting release signal (Por _ realasc), so that the system starting process is finished by releasing Por;
the low-voltage detection circuit is composed of a voltage reference circuit, a comparator and a voltage division circuit, wherein the internal voltage Vregd is a voltage for supplying power to an MCU and an RAM in the SOC, and when the value of the internal voltage Vregd is reduced to a certain value, Vx is smaller than Vref, a low-voltage event signal is generated and is sent to a system, and low-voltage restart or interruption of the system is realized.
3. The power management system of claim 1, wherein the driving circuit adjusts a voltage Vnominal provided by the voltage converting circuit to increase a driving capability, so as to achieve a driving purpose.
4. The power chip management system of claim 1, wherein the ram protection circuit comprises a comparator, a control circuit and a switch circuit, when the applied voltage Vstby is normal, the Vstby is outputted from the Vregr terminal through the NMOS transistor and the switch circuit, when the voltage of Vstby is lower than Vregd, the Vstbyref is low, the Vregd is outputted from the Vregr terminal through the switch circuit, thereby achieving the purpose of protecting the memory, and a high flag signal Stby _ b is generated to indicate that the memory is supplied with Vregd.
5. The power management chip system of claim 1, wherein the logic control circuit comprises a rewrite circuit, a status control circuit, an analog control circuit, a low voltage logic circuit, and a restart control circuit, the restart control circuit receives a power enable signal and a low voltage restart signal generated by the low voltage logic control circuit, generates a control signal to the rewrite circuit, the rewrite circuit sets the initial values of the status control bits during system start, if the power is on, the rewrite circuit receives the power enable complete signal of the system after the completion of the rewrite, generates a power enable release signal to the power enable circuit, releases the power enable signal, the low voltage logic control circuit receives the low voltage event signal, and determines whether the system is performing low voltage restart or low voltage interrupt according to the status control signal provided by the MCU, the state control circuit generates control signals to the analog control circuit and the voltage conversion circuit to carry out state control, and the analog control circuit receives the control signals to carry out logic conversion and generate enable signals of an analog part in the power management chip.
6. The power chip management system according to claim 1, wherein the voltage conversion circuit comprises an auxiliary module, three oscillators, three feedback circuits and three pump circuits, and dynamically converts the external power voltage under the control of the logic control circuit to provide a stable voltage Vnominal to the driving circuit;
the oscillator generates square waves according to an external voltage signal and reference voltage generated by a power management chip and provides the square waves to the pump circuit, the pump circuit receives the square waves from the oscillator and outputs relatively stable voltage Vnnina 1, and in order to obtain stable Vominal, the oscillator circuit and the pump circuit are required to complement each other so as to finally output stable voltage, the three feedback circuits respectively monitor the output voltages of the three driving circuits, and transmit control signals to the oscillator to adjust the working state of the oscillator, so that the purpose of adjusting the voltage is achieved.
7. The method of claim 1, wherein the method comprises the following steps:
(1) the power supply starting circuit is responsible for starting and restarting a power supply and generating a power supply starting signal;
(2) the low voltage detection circuit monitors an internal power supply (Vregd) and generates a low voltage event signal;
(3) the voltage conversion circuit converts an external power supply under the control of the logic control circuit, provides voltage (Vnominal) to the driving circuits, and the three driving circuits respectively provide power supply voltage for an internal memory, a phase-locked loop and a Microcontroller (MCU) in the power supply chip;
(4) the logic control circuit is mutually associated with the MCU, the power supply starting circuit and the low voltage detection circuit to control the voltage conversion circuit, so that the aim of determining the working state of the power supply management module is fulfilled, and the dynamic management of the power supply is realized;
(5) the random memory protection circuit selects between the voltage Vregd and Vstby according to the condition of the external actual voltage, and provides an uninterrupted power supply for the memory to protect the content from being damaged.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112736301A (en) * | 2020-12-16 | 2021-04-30 | 珠海亿智电子科技有限公司 | Self-protection method and device for lithium battery ultra-low-power SoC chip |
| CN114649014A (en) * | 2020-12-17 | 2022-06-21 | 美光科技公司 | Method of limiting power during stress testing and other limited power environments |
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| KR20060068220A (en) * | 2004-12-16 | 2006-06-21 | 주식회사 하이닉스반도체 | Circuit for generating reference voltage in semiconductor memory device |
| CN102692596A (en) * | 2011-03-24 | 2012-09-26 | 飞思卡尔半导体公司 | Selectable threshold reset circuit |
| CN107346164A (en) * | 2017-06-02 | 2017-11-14 | 江苏万邦微电子有限公司 | A kind of power-supply management system |
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| EP0295197A1 (en) * | 1987-06-11 | 1988-12-14 | United Technologies Corporation | Power supply start-up circuit |
| US20040073807A1 (en) * | 2002-10-10 | 2004-04-15 | Stmicroelectronics, Inc. | Electronic device and timer therefor with tamper event time stamp features and related methods |
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| CN114649014A (en) * | 2020-12-17 | 2022-06-21 | 美光科技公司 | Method of limiting power during stress testing and other limited power environments |
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