CN111752504A - Multi-screen display method and system for electronic equipment, electronic equipment and computer readable medium - Google Patents
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- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
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- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
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Abstract
A multi-screen display method of an electronic device, a multi-screen display system, an electronic device and a computer readable medium are provided, and the multi-screen display method includes: acquiring preset offset addresses of a plurality of DSI units; respectively acquiring the memory initial addresses of a plurality of display units based on the preset offset addresses of the DSIs, wherein each display unit has display parameters; acquiring an access parameter of each display unit based on the display parameter of each display unit and a preset offset address of each DSI unit; correspondingly generating a driver program instruction of each display unit based on the access parameter of each display unit so as to drive each display unit; writing the appointed display data into the appointed FPGA unit by accessing the appointed memory first address of the display unit; and writing the appointed display data into the appointed memory space of the display unit. Therefore, the effects of multi-screen simultaneous display and multi-screen different display can be realized.
Description
Technical Field
The present disclosure relates to the field of electronic communications, and in particular, to a multi-screen display method and a multi-screen display system for an electronic device, and a computer-readable medium.
Background
With the rapid development of electronic devices, various electronic devices are increasingly used in daily life of people, and among them, the mobile phone is most widely used. Mobile phones have become an indispensable communication tool in people's life. At present, the technology of electronic equipment such as mobile phones has been developed, but the requirements of people for electronic equipment such as mobile phones are gradually increased. Traditional electronic equipment, such as cell-phone, panel computer etc. all have a screen, and people can only operate a screen simultaneously, and this has brought the inconvenience for people, and such electronic equipment also does not adapt to the diversified demand in present cell-phone market. However, in some other electronic devices, there is also a demand for multi-screen display, for example, an augmented reality device requires multiple screens to be displayed simultaneously, and an advertisement player requires multiple screens to be displayed simultaneously with different advertisements.
In the existing multi-screen display scheme based on the android system, three-screen display can be realized through a main screen, HDMI (high definition Multimedia Interface) and WiFi (wireless local area network). However, the need for more than three screens is difficult to expand due to hardware limitations (e.g., limited number of screen controllers). Therefore, a multi-screen display method capable of overcoming the hardware limitation is now demanded.
Disclosure of Invention
An object of the present application is to provide a multi-screen Display method of an electronic device, a multi-screen Display system, an electronic device, and a computer readable medium, wherein the multi-screen Display method writes Display data into a plurality of FPGA (Field-Programmable gate array) units, and then communicatively connects the Display units through a plurality of DSI (Display-serial Interface) units to write the Display data into the plurality of Display units, so as to improve a defect that hardware limits multi-screen Display.
Another objective of the present application is to provide a multi-screen display method for an electronic device, a multi-screen display system, an electronic device, and a computer readable medium, wherein the same display data can be written into a plurality of display units respectively by the multi-screen display method, so as to achieve the effect of multi-screen simultaneous display.
Another objective of the present application is to provide a multi-screen display method, a multi-screen display system, an electronic device, and a computer readable medium for an electronic device, wherein in the multi-screen display method, different display data can be written into a designated display unit, so as to implement multi-screen different display, thereby meeting the requirement of the electronic device for displaying different contents on multiple screens simultaneously.
Another objective of the present application is to provide a multi-screen display method, a multi-screen display system, an electronic device, and a computer readable medium for an electronic device, wherein the number of screens can be selected according to needs by the multi-screen display method, so as to further meet the current requirements of the electronic device for multi-screen display and improve the user experience of the electronic device.
Another objective of the present application is to provide a multi-screen display method of an electronic device, a multi-screen display system, an electronic device, and a computer-readable medium, wherein the multi-screen display method can write a specified portion of the same display data into a specified display unit, so that a plurality of screens simultaneously display the specified portion of the display data, thereby achieving a multi-screen splicing effect.
In order to achieve at least one of the above objectives, the present application provides a multi-screen display method for an electronic device, including:
acquiring preset offset addresses of a plurality of DSI units;
respectively acquiring memory initial addresses of a plurality of display units connected with the plurality of DSI units based on preset offset addresses of the plurality of DSIs, wherein each display unit has a display parameter, and the display parameters comprise the resolution and the display format of the display unit;
acquiring an access parameter of each display unit based on the display parameter of each display unit and a preset offset address of the DSI unit coupled to the display unit, wherein the access parameter comprises an access address and an access range;
correspondingly generating a driver program instruction of each display unit based on the access parameter of each display unit so as to drive each display unit;
writing specified display data into an FPGA unit connected to the specified display unit by accessing the specified memory head address of the display unit, wherein the memory space of the FPGA unit is mapped to the specified address of the memory space of the MCU unit; and
and writing the appointed display data into the appointed memory space of the display unit.
According to an embodiment of the present application, wherein, the step of writing the specified display data into an FPGA unit coupled to the specified display unit by accessing the memory header address of the specified display unit further comprises: FIG. 2 is a block diagram illustrating a multi-screen display method of an electronic device according to another preferred embodiment of the present application
Establishing a sequence table based on the display parameters and the memory head addresses of each display unit and preset offset addresses of the DSI units, wherein the sequence table has a plurality of access sequence numbers, and the access sequence numbers respectively correspond to the memory head addresses of the display units;
scaling and format converting the specified display data based on the specified display parameters of the display unit; and
and writing the specified display data into the FPGA unit connected with the specified display unit through the access sequence number of the display unit specified in the sequence list.
According to an embodiment of the present application, writing the specified display data into an FPGA unit coupled to the specified display unit by accessing a memory header address of the specified display unit includes:
writing the specified display data into the FPGA unit coupled to a first display unit based on a memory head address of the first display unit;
writing the display data into a memory space of a first display unit based on an access parameter of the first display unit;
processing the designated display data based on the display parameters of the first display unit and a second display unit, and writing the processed display data into the FPGA unit connected with the second display unit; and
and writing the processed display data into the second display unit based on the access parameter of the second display unit.
According to an embodiment of the application, the processing the specified display data based on the display parameters of the first display unit and the second display unit comprises:
performing format conversion on the display data based on the display format of the second display unit;
acquiring a resolution ratio between the first display unit and the second display unit; and
and scaling the display data in the converted format based on the resolution ratio so as to meet the resolution of the second display unit.
In another aspect of the present application, there is further provided an electronic device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor, wherein the memory has at least one instruction, wherein the instruction is executed by the at least one processor to cause the at least one processor to perform the electronic device multi-screen display method as described above.
According to another aspect of the present application, there is further provided a computer-readable storage medium storing a computer program, which when executed by a processor, implements the multi-screen display method of an electronic device as described above.
In another aspect of the present application, there is further provided a multi-screen display system, comprising:
a plurality of display units; and
a control processing module communicatively coupled with the plurality of display units, wherein the control processing mechanism comprises:
an MCU unit;
the FPGA units are in communication connection with the MCU unit; and
the display unit comprises a plurality of DSI units, wherein one end of each DSI unit is in communication connection with the FPGA unit, and the other end of each DSI unit is connected with one display unit, and the MCU unit, the FPGA units and the DSI units are used for realizing the multi-screen display method of the electronic equipment.
Further objects and advantages of the present application will become apparent from an understanding of the ensuing description and drawings.
These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the claims.
Drawings
Fig. 1 is a block diagram illustrating a multi-screen display method of an electronic device according to a preferred embodiment of the present application.
2A-2B are block diagrams illustrating a multi-screen display method of an electronic device according to a preferred embodiment of the present application.
FIG. 3 is a block diagram of an electronic device according to a preferred embodiment of the present application.
FIG. 4 is a block diagram illustrating a multi-screen display system of an electronic device according to a preferred embodiment of the present application.
Detailed Description
The following description is presented to disclose the application and to enable any person skilled in the art to practice the application. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The underlying principles of the application, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the application.
It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or components must be in a particular orientation, constructed and operated in a particular orientation, and thus the above terms are not to be considered limiting of the present application.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
In the present application, the terms "a" and "an" in the claims and the description should be understood as meaning "one or more", that is, one element may be present in one embodiment and one element may be present in plural in another embodiment. The terms "a" and "an" should not be construed as referring to the sole or sole element, unless the disclosure expressly indicates that there is only one of the element, and the terms "a" and "an" should not be construed as limiting in number.
In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it should be noted that, unless explicitly stated or limited otherwise, the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, no unnecessary limitations are intended to the details of construction or design herein shown. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
As described above, as the requirements of the existing embedded devices (such as augmented reality devices, mobile phone projection, multi-screen advertisement machines, etc.) for multi-screen display become higher, a multi-screen display method is urgently needed to meet the needs of users. However, many existing system platforms have expansion limitations in applying multi-screen displays. For example, in the conventional android system, multi-screen display can be realized by three-screen display, namely, a dual-screen + WiFi mode, such as a main screen, an HDMI (High Definition Multimedia Interface) and a WiFi (wireless local area network). However, due to the limitation of hardware (e.g., the limited number of controllers for the display units), if more than three display units are required, expansion is difficult, and therefore, the present application provides a multi-screen display method to overcome the defect that the hardware of the electronic device limits the expansion of the number of display units.
The present application provides a plurality of FPGA units (Field-Programmable Gate arrays) communicatively coupled to an MCU (micro controller Unit) Unit of the electronic device, and a plurality of DSI (Display-serial Interface) units, where one end of each DSI Unit is communicatively coupled to the FPGA Unit, and the other end of each DSI Unit is communicatively coupled to a Display Unit, so that Display data can be written into the plurality of FPGA units first, and then written into the Display Unit through the plurality of DSI units, so as to expand the number of screens, thereby improving the defect that the existing multi-screen Display method is limited by hardware.
In practical applications, according to different functional requirements of electronic devices, multi-screen display methods are divided into a multi-screen co-display (e.g., augmented reality device), a multi-screen non-display (e.g., advertisement player) and a multi-screen mosaic (e.g., mobile phone projection), where the multi-screen mosaic is also a kind of multi-screen non-display, that is, contents displayed by a plurality of display units are the same, different, or spliced together to display one content.
As shown in fig. 1 to 4, a process diagram and a method block diagram of multi-screen display of the multi-screen display method are illustrated. The FPGA units are connected to the MCU unit through a system bus, and the memory space of each FPGA unit is mapped to a preset position in the memory space of the MCU unit. The plurality of FPGA units are communicatively coupled with the plurality of display units via the plurality of DSI units.
More specifically, the MCU unit may be simultaneously communicatively coupled to a plurality of said FPGA units, each of said FPGA units may be simultaneously communicatively coupled to a plurality of said DSI units, and each of said DSI units is simultaneously connected to one of said display units. In this manner, the plurality of FPGA units are modeled as memory devices for storing a predetermined range of display data (e.g., rendering data).
Each DSI unit has a preset offset address, and each display unit has a memory first address, wherein the memory first address of each display unit is obtained based on the preset offset address. It will be understood by those skilled in the art that the preset offset address corresponds to the size of the display data, i.e., the preset offset value of the memory address of each display unit should be greater than or equal to the size of the display data. Each display unit is provided with access data, wherein the access data is acquired through the MCU unit based on the resolution, the display format and the offset address of the DSI unit.
When the electronic equipment performs multi-screen different display, the MCU unit correspondingly generates a driver instruction of each display unit based on the access data of each display unit, and is used for driving each display unit respectively, wherein the MCU unit accesses the memory head address of each display unit through the DSI unit, and writes the specified display data into the memory space of the specified display unit through the FPGA unit, so that the multi-screen different display is realized.
In other words, the MCU unit accesses the access data of each display unit through the DSI unit to write the designated display data into the memory space of the designated display unit. Firstly, the display data is written into the memory space of the designated FPGA through the MCU unit, at this time, the designated FPGA unit is in communication connection with the designated display unit through the DSI unit, and finally, the designated display data is written into the memory space of the designated display unit through the FPGA unit. Through the mode, appointed the display element just can show appointed demonstration data to reach many screens different effect that shows, perhaps a plurality of the display element shows the different parts of a demonstration data simultaneously, thereby reaches the effect that many screens were spliced, and then satisfies the demand that present electronic equipment (like advertisement machine, cell-phone projection etc.) show to many screens different.
Accordingly, the multi-screen display method 100 includes the steps of:
s101: acquiring preset offset addresses of a plurality of DSI units;
s102: respectively acquiring memory initial addresses of a plurality of display units connected with the plurality of DSI units based on preset offset addresses of the plurality of DSIs, wherein each display unit has a display parameter, and the display parameters comprise the resolution and the display format of the display unit;
s103: acquiring an access parameter of each display unit based on the display parameter of each display unit and a preset offset address of the DSI unit coupled to the display unit, wherein the access parameter comprises an access address and an access range;
s104: correspondingly generating a driver program instruction of each display unit based on the access parameter of each display unit so as to drive each display unit;
s105: writing specified display data into an FPGA unit connected to the specified display unit by accessing the specified memory head address of the display unit, wherein the memory space of the FPGA unit is mapped to the specified address of the memory space of the MCU unit;
s106: and writing the appointed display data into the appointed memory space of the display unit.
In a possible implementation manner of this embodiment, step S105: writing a designated display data into an FPGA unit coupled to the designated display unit by accessing a memory head address of the designated display unit, wherein a memory space of the FPGA unit is mapped in the designated address of the memory space of the MCU unit, further comprising:
s1051: establishing a sequence table based on the display parameters and the memory head addresses of each display unit and preset offset addresses of the DSI units, wherein the sequence table has a plurality of access sequence numbers, and the access sequence numbers respectively correspond to the memory head addresses of the display units;
s1052: scaling and format converting the specified display data based on the specified display parameters of the display unit;
s1053: and writing the specified display data into the FPGA unit connected with the specified display unit through the access sequence number of the display unit specified in the sequence list.
Those skilled in the art will appreciate that the number of the FPGA unit, the DSI unit, and the display unit shown in fig. 4 may be increased or decreased according to the requirement of the electronic device, and is not limited to the number shown in the drawing. The manner of obtaining the sequence table (e.g., through a hardware abstraction layer) has been developed and matured in the communication field based on the resolution, the display format, the DSI offset position, and the memory first address of each display unit, which is not described again in this application. The display unit may be implemented as a liquid crystal display, a projector, etc., and may be implemented as any display device that receives the display data and presents the display data to a user, which is not limited herein.
It is worth mentioning that the multi-screen display method 100 proposed in the present application simulates the FPGA unit as a memory device to connect with the multiple display units, so that not only can the limitation of hardware devices on the expansion of the multiple display units of the electronic device be broken through, but also the specified display data can be more flexibly written into the specified display units, thereby achieving the effects of multi-screen different display and multi-screen splicing of the electronic device.
As shown in fig. 2B, after the DSI unit accesses the memory head address of the designated display unit, writes the display data designated in the MCU unit into the FPGA connected to the designated display unit, and writes the designated display data into the memory space of the designated display unit, the designated display data is processed first and then written into the other FPGA units, so that the same display data is copied into the memory spaces of the other display units through the FPGA unit and the DSI unit, and the designated display data satisfies the resolution and display format of each written display unit.
More specifically, after display data is written into the FPGA cell connected to the designated display cell, the display data is first scaled and format-converted based on the resolution and display format of the designated display cell, so that the written display data meets the resolution and display format of the designated display cell, thereby achieving the effect of multi-screen simultaneous display.
According to another preferred embodiment of the present application, the step S105: writing a designated display data into an FPGA unit coupled to the designated display unit by accessing a memory head address of the designated display unit, wherein a memory space of the FPGA unit is mapped in the designated address of the memory space of the MCU unit, further comprising:
S1051A: writing the specified display data into the FPGA unit coupled to a first display unit based on a memory head address of the first display unit;
S1052A: writing the display data into a memory space of a first display unit based on an access parameter of the first display unit;
S1053A: processing the designated display data based on the display parameters of the first display unit and a second display unit, and writing the processed display data into the FPGA unit connected with the second display unit;
S1054A: and writing the processed display data into the second display unit based on the access parameter of the second display unit.
Preferably, in this way, the same display data can be copied and processed in the MCU unit to be written into the plurality of display screens through the FPGA unit, thereby achieving the effect of displaying different display screens simultaneously. Furthermore, by applying the multi-screen display method of the electronic equipment, for the electronic equipment, not only the limitation of hardware can be broken through to achieve the purpose of expanding multi-screen display, but also other properties of the electronic equipment can be optimized. For example, by replacing hardware with an FPGA unit, the overall size of the electronic device may be reduced, thereby improving convenience for use (e.g., an augmented reality device is more convenient to wear), and reducing manufacturing cost of the electronic device, which are beneficial effects generated by applying the multi-screen display method 100.
According to another aspect of the present application, there is further provided an electronic device 200, wherein the electronic device 200 can be implemented as various electronic devices requiring multi-screen display, such as: personal digital assistants, smart phones, smart glasses, advertising machines, and other electronic computing devices with similar functionality.
As shown in fig. 3, the electronic device 200 includes: at least one processor 201; and a memory 202 communicatively coupled to the at least one processor, wherein the memory has at least one instruction 2021, wherein the instruction is executed by the at least one processor 201 to cause the at least one processor 201 to perform the electronic device multi-screen display method 100 as described above.
In one possible implementation of this embodiment, the memory 202 and the processor 201 are connected by a bus, which may include any number of interconnected buses and bridges that connect one or more of the various circuits of the processor 201 and the memory 202 together.
Those skilled in the art will appreciate that the bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, and the like. The bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or multiple elements, such as multiple receivers and multiple transmitters, wherein the transceiver is used for a transmission medium to communicate with various other devices.
The processor 201 is capable of executing instructions within the electronic device 200, including instructions stored in the memory 202. The processor 201 may be implemented as a chipset of chips that include separate and multiple analog and digital processors. The processor 201 may also provide coordination of the other components of the electronic device 200.
The memory 202 is capable of storing information to the electronic computing device. The memory 202 may be implemented as one or more of a computer-readable medium, a volatile memory unit, or a non-volatile memory unit.
Preferably, the electronic device 200 can be implemented in many different forms, for example, it can be implemented as: a smart phone, a personal digital assistant, a tablet computer, smart glasses, a smart watch, or a portion of a similar electronic device.
According to another aspect of the present application, there is also provided a computer readable storage medium for storing computer program instructions, wherein the computer program instructions, when executed by a processor, implement the multi-screen display method 100 as described above.
Those skilled in the art will appreciate that all or part of the steps in the method according to the above embodiments may be implemented by controlling the relevant hardware through program instructions, where the program instructions are stored in a storage medium, and include a plurality of instructions for controlling a device (e.g., a single chip, a chip, etc.) or a processor to execute the multi-screen display method 100 described above. The storage medium may be a usb disk, a removable hard disk, a Read-Only-Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, which may store program codes.
According to another aspect of the present application, there is further provided a multi-screen display system 300 of an electronic device, comprising: a plurality of display units 301; and a control processing module 302 communicatively coupled to the plurality of display units 301, wherein the control processing mechanism comprises: an MCU unit 3021; a plurality of FPGA units 3022 communicatively coupled with the MCU unit 3021; and a plurality of DSI units 3023, wherein each DSI unit 3023 has one end communicatively coupled to the FPGA unit 3022 and the other end communicatively coupled to one of the display units 301, wherein the MCU unit 3021, the plurality of FPGA units 3022, and the plurality of DSI units 301 are configured to implement the multi-screen display method 100 as described above.
It will be understood by those skilled in the art that the embodiments of the present application described above and illustrated in the drawings are by way of example only and are not limiting of the present application. The objectives of the present application have been fully and effectively attained. The functional and structural principles of the present application have been shown and described in the examples, and any variations or modifications of the embodiments of the present application may be made without departing from the principles.
Claims (10)
1. A multi-screen display method of an electronic device comprises the following steps:
acquiring preset offset addresses of a plurality of DSI units;
respectively acquiring memory initial addresses of a plurality of display units connected with the plurality of DSI units based on preset offset addresses of the plurality of DSIs, wherein each display unit has a display parameter, and the display parameters comprise the resolution and the display format of the display unit;
acquiring an access parameter of each display unit based on the display parameter of each display unit and a preset offset address of the DSI unit coupled to the display unit, wherein the access parameter comprises an access address and an access range;
correspondingly generating a driver program instruction of each display unit based on the access parameter of each display unit so as to drive each display unit;
writing specified display data into an FPGA unit connected to the specified display unit by accessing the specified memory head address of the display unit, wherein the memory space of the FPGA unit is mapped to the specified address of the memory space of the MCU unit; and
and writing the appointed display data into the appointed memory space of the display unit.
2. A multi-screen display method for an electronic device as recited in claim 1, wherein the step of writing the designated display data into an FPGA unit coupled to the designated display unit by accessing the memory header address of the designated display unit further comprises:
establishing a sequence table based on the display parameters and the memory head addresses of each display unit and preset offset addresses of the DSI units, wherein the sequence table has a plurality of access sequence numbers, and the access sequence numbers respectively correspond to the memory head addresses of the display units;
scaling and format converting the specified display data based on the specified display parameters of the display unit; and
and writing the specified display data into the FPGA unit connected with the specified display unit through the access sequence number of the display unit specified in the sequence list.
3. A multi-screen display method for an electronic device as recited in claim 1, wherein writing the designated display data into an FPGA cell coupled to the designated display cell by accessing a memory header address of the designated display cell comprises:
writing the specified display data into the FPGA unit coupled to a first display unit based on a memory head address of the first display unit;
writing the display data into a memory space of a first display unit based on an access parameter of the first display unit;
processing the designated display data based on the display parameters of the first display unit and a second display unit, and writing the processed display data into the FPGA unit connected with the second display unit; and
and writing the processed display data into the second display unit based on the access parameter of the second display unit.
4. A multi-screen display method for an electronic device as recited in claim 2, wherein writing the designated display data into an FPGA cell coupled to the designated display cell by accessing a memory header address of the designated display cell comprises:
writing the specified display data into the FPGA unit coupled to a first display unit based on a memory head address of the first display unit;
writing the display data into a memory space of a first display unit based on an access parameter of the first display unit;
processing the designated display data based on the display parameters of the first display unit and a second display unit, and writing the processed display data into the FPGA unit connected with the second display unit; and
and writing the processed display data into the second display unit based on the access parameter of the second display unit.
5. A multi-screen display method of an electronic device according to claim 3, wherein the processing of the specified display data based on the display parameters of the first display unit and the second display unit comprises:
performing format conversion on the display data based on the display format of the second display unit;
acquiring a resolution ratio between the first display unit and the second display unit; and
and scaling the display data in the converted format based on the resolution ratio so as to meet the resolution of the second display unit.
6. A multi-screen display method of an electronic device according to claim 4, wherein the processing of the specified display data based on the display parameters of the first display unit and the second display unit comprises:
performing format conversion on the display data based on the display format of the second display unit;
acquiring a resolution ratio between the first display unit and the second display unit; and
and scaling the display data in the converted format based on the resolution ratio so as to meet the resolution of the second display unit.
7. A multi-screen display method of an electronic device as recited in any of claims 2-6, wherein the sequence list is created through a hardware abstraction layer.
8. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor, wherein the memory has at least one instruction, wherein the instruction is executable by the at least one processor to cause the at least one processor to perform the electronic device multi-screen display method of any of claims 1-7.
9. A computer-readable storage medium for storing a computer program, wherein when the computer program is executed by a processor, the multi-screen display method of an electronic device according to any one of claims 1-7 is implemented.
10. A multi-screen display system, comprising:
a plurality of display units; and
a control processing module communicatively coupled with the plurality of display units, wherein the control processing mechanism comprises:
an MCU unit;
the FPGA units are in communication connection with the MCU unit; and
a plurality of DSI units, wherein each DSI unit has one end communicatively coupled to the FPGA unit and the other end connected to one of the display units, and wherein the MCU unit, the FPGA units and the DSI units are configured to implement the multi-screen display method of claims 1-7.
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