CN111750908A - Decoding method and decoding circuit for dual-channel rotary transformer - Google Patents
Decoding method and decoding circuit for dual-channel rotary transformer Download PDFInfo
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- CN111750908A CN111750908A CN202010624709.4A CN202010624709A CN111750908A CN 111750908 A CN111750908 A CN 111750908A CN 202010624709 A CN202010624709 A CN 202010624709A CN 111750908 A CN111750908 A CN 111750908A
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Abstract
The invention discloses a dual-channel rotary transformer decoding circuit, which comprises: the system comprises an FPGA module, a digital-to-analog conversion module, a signal amplification and differential output module, a double-channel rotary transformer, an analog-to-digital conversion module and a communication interface output module; the invention can be applied to rotary transformers of various models through a communication interface, samples signals of the rotary transformers by using a high-precision ADC, performs 18 iterations through an optimized CORDIC algorithm, processes the angles of the coarse-fine rotary transformers, and realizes high-precision angle measurement of 0-360 degrees.
Description
Technical Field
The invention relates to the field of electronic control, in particular to a decoding method and a decoding circuit of a dual-channel rotary transformer.
Background
The rotary transformer is used in a motion servo control system and used for sensing and measuring angular positions. Compared with an optical encoder and a magnetic encoder, the rotary transformer has the advantages of good vibration resistance, strong anti-interference capability, stable and reliable performance and suitability for various severe environments. The method is widely applied to military equipment such as aviation, aerospace, radar and tank fire control, and can also be applied to civil servo control systems such as numerical control machines and robots.
The conventional common scheme is that a crystal oscillator and other devices are used for generating excitation signals, the excitation signals are input to a primary side of a rotary transformer, the excitation signals are coupled and output through a secondary coil of the rotary transformer, the output signals are analog sine and cosine voltage signals containing angle information, and a decoding system is built through discrete devices. The method has the advantages of complex system, poor resolving precision, poor anti-interference capability, large volume and large power consumption.
To solve the above problem, a decoding scheme using digital signal processing instead of analog signal processing has been developed. Sampling the analog signal with angle information output by the rotary transformer through an AD converter, converting the analog signal into a digital signal, reading the digital signal of the AD converter by a DSP/FPGA, and finally calculating the angle of the rotary transformer through table look-up or arc tangent operation. The settlement precision of the method is strictly limited by the precision of the rotary transformation and the quantization bit width of the ADC.
To improve the decoding accuracy, a dual channel resolver is present. The double-channel rotary transformer simultaneously comprises a coarse-level rotary transformer and a fine-level rotary transformer, and the decoding precision is improved through the coarse-fine combination of decoding. The current double-channel decoding adopts a mode of single-channel decoding and then MCU processing to finish decoding. The system is complex, the volume is large, the anti-interference capability is poor, and the MCU can not adapt to the real-time requirement of the system for processing serial work. Therefore, a compact and efficient decoding scheme for the dual-channel rotary transformer is urgently needed to be designed.
Disclosure of Invention
In order to solve the technical problem, the technical scheme of the invention is realized as follows:
in a first aspect: the invention provides a decoding method of a double-channel rotary transformer, which comprises the following steps:
s100: after the system is initialized, a digital sinusoidal signal is output to a digital-to-analog conversion module by a DDS module in the FPGA module, the digital-to-analog conversion module converts the digital sinusoidal signal into an analog sinusoidal signal and inputs the analog sinusoidal signal to a signal amplification and differential output module, and the analog sinusoidal signal is amplified in the same direction and in the opposite direction by the signal amplification and differential output module to form a differential sinusoidal signal and is input to a dual-channel rotary transformer;
s200: the double-channel rotary transformer couples the differential sine signals with the coarse coil and the fine coil to generate differential sine and cosine signals with angle information and inputs the differential sine and cosine signals into the analog-to-digital conversion module, the analog-to-digital conversion module converts the differential sine and cosine signals into digital signals and inputs the digital signals into the CORDIC module of the FPGA module,
s300: and the CORDIC module performs iterative operation on the digital signal in the step S200 to obtain a resolving angle of the coarse-stage rotary transformer and a resolving angle of the fine-stage rotary transformer respectively, then performs coarse-fine processing through the FPGA module to resolve the dual-channel resolver resolving angle, and finally the FPGA module is connected with an upper computer through a communication interface.
Further, in step S100, the workflow includes the steps of:
s101: in the DDS module, inputting a frequency word K to a frequency word register, outputting a sinusoidal signal point by a sine ROM lookup table after phase accumulation, continuously performing phase accumulation and outputting the sinusoidal signal point by the sine ROM lookup table through clock drive, and finally outputting a sinusoidal signal;
s102: in the digital-to-analog conversion module, the digital-to-analog conversion module converts the digital sinusoidal signal into an analog sinusoidal signal;
s103: in the signal amplifying and differential output module, the first operational amplifier and the second operational amplifier respectively perform in-phase amplification and reverse amplification on the sinusoidal signal simulated in step S102 to form a differential sinusoidal signal.
Further, in step S101, the amplitude of the sinusoidal signal may also be controlled by an amplitude control word.
Further, in step S300, the iterative operation includes the following steps:
s301: inputting data of digital signal to XinAnd yinThe preprocessing circuit is according to XinAnd yinThe positive and negative of the data, the data is processed to the first or fourth quadrant and output as X0And Y0；
S302：X0And Y0The data in the x and y registers are divided into two paths, one path is sent to the shift register, the other path is directly sent to the adder/subtracter, and is sent back to the register through the multiplexer after being operated with the data from the other shifter;
s303: the number of shift bits of the shifter increases with the number of iterations, z0Initial value enters multiple paths and then arrives at registerThe data is divided into two paths, one path is directly sent into an adder/subtracter, the other path is used as a selection end of a plurality of paths of an x path, a y path and a z path, and the plurality of paths are selected as the adder or the subtracter;
wherein constn data is from the lookup table to operate with z-way data, and then sent back to the input end of the multi-way; as the iteration times are increased, the addresses of the lookup tables are increased, and the rotation angle set is stored in the lookup tables; and the data after eighteen iterations enters an output signal post-processor, and the data expanded in the calculation is restored into an initial result.
In a second aspect, the present invention provides a dual channel resolver decoding circuit, comprising: the system comprises an FPGA module, a digital-to-analog conversion module, a signal amplification and differential output module, a double-channel rotary transformer, an analog-to-digital conversion module and a communication interface output module;
the FPGA module is connected with the digital-to-analog conversion module and the analog-to-digital conversion module; the digital-to-analog conversion module is connected with the signal amplification and differential output module, the signal amplification and differential output module is connected with the dual-channel rotary transformer, and the dual-channel rotary transformer is connected with the analog-to-digital conversion module;
the FPGA module is connected with an upper computer through a communication interface output module.
Preferably, the FPGA module includes a DDS module and a CORDIC module. The DDS module comprises a frequency word register and a digital oscillator connected with the frequency word register; the digital oscillator includes: an N-bit phase accumulator, a phase accumulation register, and a sine ROM lookup table.
Further, the DDS module further includes an amplitude control word.
Preferably, the signal amplifying and differential output module includes a first operational amplifier and a second operational amplifier.
According to the double-channel resolver angle resolving scheme, the amplitude and the frequency of the excitation signal can be used for resolvers of various types through a communication interface, a high-precision ADC is used for sampling signals of the resolver, 18 iterations are carried out through an optimized CORDIC algorithm, the angle of a coarse resolver is processed, and high-precision angle measurement of 0-360 degrees is achieved.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of a two-channel convolutional decoder according to the present invention.
FIG. 2 is a flow chart of data processing of a two-channel rotary transform decoding FPGA.
FIG. 3 is a schematic diagram of an optimized CORDIC circuit inside an FPGA.
Fig. 4 is a circuit structure diagram of the DDS inside the FPGA.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
As shown in fig. 1, the present invention provides a dual channel resolver decoding circuit, comprising: the system comprises an FPGA module 1, a digital-to-analog conversion module (AD5621)2, a signal amplification and differential output module 3, a dual-channel rotary transformer 4, an analog-to-digital conversion module (AD7609)5 and a communication interface output module 6(RS 422); the FPGA module 1 is connected with the digital-to-analog conversion module 2 and the analog-to-digital conversion module 5; the digital-to-analog conversion module 2 is connected with the signal amplification and differential output module 3, the signal amplification and differential output module 3 is connected with the dual-channel rotary transformer 4, and the dual-channel rotary transformer 4 is connected with the analog-to-digital conversion module 5; the FPGA module 1 is connected with an upper computer 7 through a communication interface output module 6.
In the technical scheme of the invention, the FPGA module 1 comprises a DDS module and a CORDIC module. The DDS module comprises a frequency word register 8 and a digital oscillator connected with the frequency word register; the digital oscillator includes: an N-bit phase accumulator 9, a phase accumulator register 10 and a sine ROM look-up table 11.
Optionally, an amplitude control word 12 may be further provided in the DDS module to change the amplitude of the sinusoidal signal.
It is understood that, in order to generate a differential sinusoidal signal, in the solution of the present invention, the signal amplification and differential output module 4 comprises the same first and second operational amplifiers.
As shown in fig. 2, the present invention further provides a decoding method for a dual-channel resolver, comprising the following steps:
s100: after the system is initialized, a DDS module in the FPGA module 1 outputs a digital sine signal to a digital-to-analog conversion module 2, the digital-to-analog conversion module 2 converts the digital sine signal into an analog sine signal and inputs the analog sine signal to a signal amplification and difference output module 3, and the signal amplification and difference output module 3 amplifies the analog sine signal in the same direction and in the opposite direction to form a differential sine signal and inputs the differential sine signal to a dual-channel rotary transformer 4;
s200: the double-channel rotary transformer 4 couples the differential sine signal with the coarse coil and the fine coil to generate a differential sine signal and a differential cosine signal with angle information, and inputs the differential sine signal and the differential cosine signal into the analog-to-digital conversion module 5, the analog-to-digital conversion module 5 converts the differential sine signal and the differential cosine signal into digital signals and inputs the digital signals into the CORDIC module of the FPGA module 1,
s300: and the CORDIC module performs iterative operation on the digital signal in the step S200 to obtain a resolving angle of the coarse-stage rotary transformer and a resolving angle of the fine-stage rotary transformer respectively, then performs coarse-fine processing through the FPGA module to resolve the dual-channel resolver resolving angle, and finally the FPGA module is connected with an upper computer through a communication interface.
The technical solution of the present invention is explained in detail as shown in fig. 1, 2, 3, and 4.
In the FPGA module, a DDS module circuit is used for generating digital sinusoidal signals with configurable frequency and amplitude, wherein the upper computer can send instructions to configure the frequency and the amplitude of the digital sinusoidal signals generated by the DDS module. And inputting the sinusoidal signal into a digital-to-analog conversion module AD5621 chip connected with the sinusoidal signal, and generating an analog sinusoidal signal through digital-to-analog conversion. Analog sinusoidal signals are respectively input into two OPA551 operational amplifiers, wherein one path of operational amplifier generates the same-direction amplification, and the other path of operational amplifier generates the reverse amplification and is used for generating differential sinusoidal signals.
As shown in fig. 4, the specific workflow includes the following steps: in a DDS module, inputting a frequency word K to a frequency word register, outputting a sinusoidal signal point by a sine ROM lookup table after phase accumulation, then continuously performing phase accumulation and outputting the sinusoidal signal point by the sine ROM lookup table through clock drive of 25MHz, and finally outputting a sinusoidal signal; the amplitude of the sinusoidal signal can be controlled through the amplitude control word; in the digital-to-analog conversion module, the digital-to-analog conversion module converts the digital sinusoidal signal into an analog sinusoidal signal; in the signal amplifying and differential output module, the first operational amplifier and the second operational amplifier respectively perform in-phase amplification and reverse amplification on the sinusoidal signal simulated in step S102 to form a differential sinusoidal signal.
And taking the generated differential sinusoidal signal as an excitation signal of the dual-channel rotary transformer. After the double-channel rotary transformer receives the excitation signal, differential sin and cos signals with angle information are generated through coupling of a coarse coil and a fine coil of the double-channel rotary transformer. The analog-digital conversion module adopts an AD7609 chip to convert differential sin and cos signals generated by the dual-channel rotary transformer into digital signals, the FPGA quantizes the analog signals on each channel into digital signals to be read, and the angle of the coarse rotary transformer and the high-precision resolving angle of the fine rotary transformer are respectively obtained through 18 times of iterative operation in the FPGA through a CORDIC algorithm. And then the FPGA processes the angle of the coarse rotary transformer and the angle of the fine rotary transformer through coarse and fine processing, and finally the high-precision dual-channel rotary transformer resolving angle is obtained.
As shown in fig. 3, the specific iterative operation includes the following steps: inputting data of digital signal to XinAnd yinThe preprocessing circuit is according to XinAnd yinThe positive and negative of the data, the data is processed to the first or fourth quadrant and output as X0And Y0；X0And Y0The data in the x and y registers are divided into two paths, one path is sent to the shift register, the other path is directly sent to the adder/subtracter, and is sent back to the register through the multiplexer after being operated with the data from the other shifter; the number of shift bits of the shifter increases with the number of iterations, z0The initial value enters a plurality of paths and then enters a register, data is divided into two paths, one path is directly sent into an adder/subtracter, the other path is used as a selection end of the x path, the y path and the z path, and the plurality of paths are selected as the adder or the subtracter; wherein constn data is from the lookup table to operate with z-way data, and then sent back to the input end of the multi-way; as the iteration times are increased, the addresses of the lookup tables are increased, and the rotation angle set is stored in the lookup tables; and the data after eighteen iterations enters an output signal post-processor, and the data expanded in the calculation is restored into an initial result.
And finally, the upper computer can send a reading instruction in real time through the RS422 interface to obtain a calculation angle result.
While embodiments of the invention have been disclosed above, it is not limited to the applications listed in the description and the embodiments. It can be applied to all kinds of fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art. It is therefore intended that the invention not be limited to the exact details and illustrations described and illustrated herein, but fall within the scope of the appended claims and equivalents thereof.
Claims (9)
1. A decoding method for a dual-channel rotary transformer is characterized by comprising the following steps:
s100: after the system is initialized, a digital sinusoidal signal is output to a digital-to-analog conversion module by a DDS module in the FPGA module, the digital-to-analog conversion module converts the digital sinusoidal signal into an analog sinusoidal signal and inputs the analog sinusoidal signal to a signal amplification and differential output module, and the analog sinusoidal signal is amplified in the same direction and in the opposite direction by the signal amplification and differential output module to form a differential sinusoidal signal and is input to a dual-channel rotary transformer;
s200: the double-channel rotary transformer couples the differential sine signals with the coarse coil and the fine coil to generate differential sine and cosine signals with angle information and inputs the differential sine and cosine signals into the analog-to-digital conversion module, the analog-to-digital conversion module converts the differential sine and cosine signals into digital signals and inputs the digital signals into the CORDIC module of the FPGA module,
s300: and the CORDIC module performs iterative operation on the digital signal in the step S200 to obtain a resolving angle of the coarse-stage rotary transformer and a resolving angle of the fine-stage rotary transformer respectively, then performs coarse-fine processing through the FPGA module to resolve the dual-channel resolver resolving angle, and finally the FPGA module is connected with an upper computer through a communication interface.
2. The dual channel resolver decoding method of claim 1, wherein in step S100, the workflow comprises the steps of:
s101: in the DDS module, inputting a frequency word K to a frequency word register, outputting a sinusoidal signal point by a sine ROM lookup table after phase accumulation, continuously performing phase accumulation and outputting the sinusoidal signal point by the sine ROM lookup table through clock drive, and finally outputting a sinusoidal signal;
s102: in the digital-to-analog conversion module, the digital-to-analog conversion module converts the digital sinusoidal signal into an analog sinusoidal signal;
s103: in the signal amplifying and differential output module, the first operational amplifier and the second operational amplifier respectively perform in-phase amplification and reverse amplification on the sinusoidal signal simulated in step S102 to form a differential sinusoidal signal.
3. The dual channel resolver decoding method of claim 2, wherein in step S101, the amplitude of the sinusoidal signal is further controlled by an amplitude control word.
4. The dual channel resolver decoding method of claim 1, wherein in step S300, the iterative operation comprises the steps of:
s301: inputting data of digital signal to XinAnd yinThe preprocessing circuit is according to XinAnd yinThe positive and negative of the data, the data is processed to the first or fourth quadrant and output as X0And Y0；
S302：X0And Y0The data in the x and y registers are divided into two paths, one path is sent to the shift register, the other path is directly sent to the adder/subtracter, and is sent back to the register through the multiplexer after being operated with the data from the other shifter;
s303: the number of shift bits of the shifter increases with the number of iterations, z0The initial value enters a plurality of paths and then enters a register, data is divided into two paths, one path is directly sent into an adder/subtracter, the other path is used as a selection end of the x path, the y path and the z path, and the plurality of paths are selected as the adder or the subtracter;
wherein constn data is from the lookup table to operate with z-way data, and then sent back to the input end of the multi-way; as the iteration times are increased, the addresses of the lookup tables are increased, and the rotation angle set is stored in the lookup tables; and the data after eighteen iterations enters an output signal post-processor, and the data expanded in the calculation is restored into an initial result.
5. A dual channel resolver decoding circuit, comprising: the system comprises an FPGA module, a digital-to-analog conversion module, a signal amplification and differential output module, a double-channel rotary transformer, an analog-to-digital conversion module and a communication interface output module;
the FPGA module is connected with the digital-to-analog conversion module and the analog-to-digital conversion module; the digital-to-analog conversion module is connected with the signal amplification and differential output module, the signal amplification and differential output module is connected with the dual-channel rotary transformer, and the dual-channel rotary transformer is connected with the analog-to-digital conversion module;
the FPGA module is connected with an upper computer through a communication interface output module.
6. The dual channel resolver decoding circuit of claim 5, wherein the FPGA module comprises a DDS module and a CORDIC module.
7. The dual channel resolver decoding circuit of claim 6, wherein the DDS module comprises a frequency word register, a digital oscillator connected to the frequency word register;
the digital oscillator includes: an N-bit phase accumulator, a phase accumulation register, and a sine ROM lookup table.
8. The dual channel resolver decoding circuit of claim 7, wherein the DDS module further comprises an amplitude control word.
9. The dual channel resolver decoding circuit of claim 5, wherein the signal amplification and differential output module comprises a first operational amplifier and a second operational amplifier.
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Application publication date: 20201009 |