CN111739890A - Method for manufacturing semiconductor device - Google Patents
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- CN111739890A CN111739890A CN202010583094.5A CN202010583094A CN111739890A CN 111739890 A CN111739890 A CN 111739890A CN 202010583094 A CN202010583094 A CN 202010583094A CN 111739890 A CN111739890 A CN 111739890A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The invention provides a method for manufacturing a semiconductor device, which comprises the steps of gradually reducing the line width of a mask layer after a semiconductor substrate is etched by utilizing the mask layer to form an active region, trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface, wherein the longitudinal section of the arc-shaped curved surface is between an elliptical arc and a circular arc, and the maximum ideal value of the arc-shaped curved surface can be the circular arc. In addition, the mask layer is still reserved after the top surface of the active region is trimmed to be the arc-shaped curved surface, so that the insulating isolation layer is opened by utilizing the mask layer in the follow-up process, the process is simplified, and the cost is saved.
Description
Technical Field
The present invention relates to the field of semiconductor device manufacturing technologies, and in particular, to a method for manufacturing a semiconductor device.
Background
The technical development of the planar semiconductor device follows the forward evolution of moore's law, and the lower power consumption and the higher speed become the main melody of the current technical development of the planar semiconductor device. For logic circuits, the on-current of a MOS transistor is inversely proportional to its effective channel length, so increasing the speed of logic circuits is usually done by reducing the effective channel length of the MOS transistor, and thus logic circuits all the way evolve to today's 5 nanometer technology.
Taking a code type flash memory as an example, please refer to fig. 1, wherein programming (Program) of the code type flash memory is implemented by a Hot Electron Injection (Hot Electron Injection), specifically, during programming, a gate terminal of a transistor of a memory cell is applied with a voltage Vg of 8-10V, a source terminal is grounded (i.e., a source terminal voltage Vs is 0V), and in order to overcome a barrier height of 3.2eV between a monocrystalline silicon (i.e., a drain terminal) and a silicon dioxide (i.e., a gate dielectric layer), a drain terminal voltage Vd higher than 3.2V must be applied to a drain terminal, for example, Vd is 3.5-4.5V, so that Hot electrons can be generated at a position where a drain junction formed by the drain terminal and a channel is close to a gate electrode, and the generated Hot electrons can obtain enough energy to cross the barrier. However, the fixed drain voltage Vd limits the possibility of further shrinking the channel length of the code flash memory, and the effective channel length cannot be further decreased, which makes it difficult to increase the on-current Idsat of the memory cell of the code flash memory.
The repeated erasing times are key performance indexes of the code type flash memory. The memory cell is distinguished between a programmed state and an erased state, and the magnitude of the conduction current Idsat of the memory cell is used for judging the memory cell. As shown in fig. 2, if the on-current Idsat of the memory cell is greater than a certain value Iref, it is determined as an erased state; if the on-current Idsat of the memory cell is smaller than the specific value Iref, the memory cell is determined to be in the programmed state. The performance of the memory cell is degraded due to repeated erasing and writing, and the on-current Idsat of the memory cell in the erased state is reduced, so that the identification window Dt-1 of the next generation technology t-1 is much smaller than the identification window Dt of the previous generation technology t.
The discrimination window for determining the programmed state and the erased state must be large enough to guarantee one hundred thousand repeated erasures. And the index of the repeated erasing times of the next generation technology t-1 can not reach the standard due to the undersized identification window, so that the increase of the conduction current Idsat of the storage unit becomes a key factor in order to keep the next generation technology t-1 capable of keeping the key performance index of the previous generation technology t on the premise of not increasing the size of a device.
That is, how to increase the on-current of the transistor to improve the device speed and performance without changing the conventional design rule is one of the technical problems to be solved urgently.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which can increase the conducting current of the device and improve the speed and the performance of the device on the premise of not changing the conventional design rule.
To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
s1, providing a semiconductor substrate, and forming a mask layer on the semiconductor substrate;
s2, performing active area etching on the mask layer and the semiconductor substrate to form a plurality of active areas in the semiconductor substrate, wherein a groove is formed between every two adjacent active areas;
s3, gradually reducing the line width of the mask layer, and trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface;
s4, filling an insulation isolation layer in the groove, wherein the insulation isolation layer also exposes the top surface of the residual mask layer;
and S5, removing the mask layer, and etching back the insulation isolation layer to form a trench isolation structure.
Optionally, in the step S1, before forming the mask layer on the semiconductor substrate, the semiconductor substrate is further subjected to thermal oxidation to form a pad oxide layer.
Optionally, in step S3, the step of gradually reducing the line width of the mask layer and trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface includes:
s3.1.1, etching at least the side wall of the mask layer to reduce the line width of the mask layer;
s3.1.2, surface oxidizing the active area to form a surface oxide layer;
s3.1.3, removing the surface oxide layer to re-expose the surface of the active region;
s3.1.4, steps S3.1.1 through S3.1.3 are performed multiple times until the top surface of the active region is trimmed to the desired arcuate surface.
Optionally, in the step S3, a selective wet etching process is adopted to simultaneously etch the sidewalls and the top wall of the mask layer, so as to reduce the height of the mask layer while reducing the line width of the mask layer.
Optionally, the material of the mask layer formed in step S1 includes silicon nitride; in step S3, the etchant of the selective wet etching process includes a phosphoric acid solution, and the etching time is 5 seconds to 20 minutes.
Optionally, in the step S3.1.3, another wet etching process is used to remove the surface oxide layer.
Optionally, in the step S3.1.4, the etching time for etching the mask layer each time is the same, or the etching time for etching the mask layer is gradually shortened as the number of times of performing the steps S3.1.1 to S3.1.3 is increased, so as to trim the top surface of the active region into an arc-shaped curved surface.
Optionally, in step S3, the step of gradually reducing the line width of the mask layer and trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface includes:
s3.2.1, etching at least the side wall of the mask layer to reduce the line width of the mask layer;
s3.2.2, performing wet etching and/or ion bombardment on the top corner of the active region exposed by the mask layer to round the top corner of the active region exposed by the mask layer;
s3.2.3, steps S3.2.1 through S3.2.2 are performed multiple times until the top surface of the active region is trimmed to the desired arcuate surface.
Optionally, in step S4, the step of filling the insulating isolation layer in the trench includes:
depositing an insulating isolation layer on the semiconductor substrate and the mask layer, wherein the deposited insulating isolation layer at least fills the groove;
and carrying out top planarization on the deposited insulating isolation layer until the top surface of the mask layer is exposed.
Optionally, in the step S5, the insulating isolation layer is etched back by using a wet etching process to form the trench isolation structure.
Optionally, after the step S5, the manufacturing method further includes: and sequentially forming a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate, wherein the control gate is intersected with the active region, the inter-gate dielectric layer is sandwiched between the floating gate and the control gate and between the control gate and the trench isolation structure, the floating gate is sandwiched between the control gate and the active region, and the tunneling dielectric layer is sandwiched between the floating gate and the active region.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. in the invention, after the mask layer is used for etching the semiconductor substrate to form the active region, the line width of the mask layer is gradually reduced, the top surface of the active region exposed by the mask layer is trimmed into an arc-shaped curved surface, the longitudinal section shape of the arc-shaped curved surface is between an elliptical arc and an arc, and the maximum ideal value of the arc-shaped curved surface can be an arc.
2. After the top surface of the active area is trimmed into an arc-shaped curved surface, the mask layer still remains, the remaining mask layer is removed after the insulating isolation layer is filled in the groove, an opening for opening the insulating isolation layer can be directly formed, the insulating isolation layer is prevented from being etched and opened by using a photoetching process, the process can be simplified, and the process cost is saved.
3. When the semiconductor device to be manufactured is a code type flash memory, the top surface of the active area of the memory unit is improved to be an arc-shaped curved surface, so that the conduction current of the memory unit can be increased, the identification windows of a programming state and an erasing state can be effectively increased, and the repeatable erasing times of the memory unit can be increased.
4. When the required effective channel width is the same, the line width of the active region can be further reduced, thereby providing the possibility of continuous micro technology, and being beneficial to obtaining smaller chip area on the premise of the same product performance, thereby improving the product competitiveness and reducing the production cost.
Drawings
Fig. 1 is a schematic diagram of a cross-sectional structure and electron-tunneling of a memory cell of a conventional code type flash memory during programming.
FIG. 2 is a diagram illustrating the program and erase windows of a conventional two-generation technology for code-based flash memory.
Fig. 3 is a flow chart of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Fig. 4-12 are cross-sectional views of the device structure in the flow of the manufacturing method shown in fig. 3.
Fig. 13 is a schematic top view of the device structure in the flow of the manufacturing method shown in fig. 3.
Fig. 14 is a schematic cross-sectional view of a conventional device structure of a code type flash memory.
FIG. 15 is a diagram illustrating comparison of recognition windows under the same design rule in the present invention and the prior art.
Detailed Description
Transistor on-current principle:
in the formula, Idsat is the on-current, Cox is the parasitic capacitance, μ is a constant,w is the effective channel width, L is the effective channel length, VGSIs the difference of gate-source voltages, VTIs the threshold voltage.
As can be seen from the above equation, the transistor on current Idsat is inversely proportional to the effective channel length L and directly proportional to the effective channel width W.
As described in the background, logic circuits have evolved through the 5 nm process, which is mainly to reduce the effective channel length L of MOS transistors and increase the speed of logic circuits.
However, the transistor on-current Idsat is also proportional to the effective channel width W, so that the on-current can be increased by increasing the effective channel width W at this time.
Based on the above, the core idea of the present invention is to improve the top surface of the active region into an arc-shaped curved surface without changing the existing design rule, thereby increasing the effective channel width and further achieving the purpose of increasing the on-state current Idsat.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. As used herein, "and/or" means either or both.
Referring to fig. 3, an embodiment of the invention provides a method for manufacturing a semiconductor device, including the following steps:
s1, providing a semiconductor substrate, and forming a mask layer on the semiconductor substrate;
s2, performing active area etching on the mask layer and the semiconductor substrate to form a plurality of active areas in the semiconductor substrate, wherein a groove is formed between every two adjacent active areas;
s3, gradually reducing the line width of the mask layer, and trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface;
s4, filling an insulation isolation layer in the groove, wherein the insulation isolation layer also exposes the top surface of the residual mask layer;
and S5, removing the mask layer, and etching back the insulation isolation layer to form a trench isolation structure.
Referring to fig. 4, in the step S1, a semiconductor substrate 200 is first provided, where the semiconductor substrate 200 may be any suitable semiconductor substrate material known to those skilled in the art, such as silicon, silicon-on-insulator, germanium, silicon germanium, germanium-on-insulator, silicon germanium-on-insulator, gallium arsenide, indium phosphide, or an epitaxial wafer. Then, the semiconductor substrate 200 is oxidized by a thermal oxidation process such as dry oxidation or wet oxidation to form a pad oxide layer (pad oxide)201, wherein when the semiconductor substrate 200 is a silicon substrate or a silicon-on-insulator substrate, the pad oxide layer 201 is made of silicon dioxide. Next, a mask layer 202 is covered on the pad oxide layer 201 by a chemical vapor deposition process or the like, wherein the material of the mask layer 202 is different from that of the pad oxide layer 201, and the mask layer 202 may include at least one of silicon nitride, silicon oxynitride, silicon carbide nitride, a low-K dielectric having a dielectric constant K lower than 3, a high-K dielectric having a dielectric constant K higher than 7, an organic coating layer, and a photoresist. In this embodiment, the mask layer 202 is silicon nitride. The pad oxide layer 201 can relieve stress between the mask layer 202 and the semiconductor substrate 200. The pad oxide layer 201 may be omitted in other embodiments of the present invention.
With continued reference to fig. 4, in the step S2, the mask layer 202 and the semiconductor substrate 200 are subjected to active area etching to form a plurality of active areas 200a in the semiconductor substrate 200. The specific process comprises the following steps: first, a photoresist layer is coated on the hard mask layer 202, and the photoresist is subjected to photolithography using an active area mask plate to form an active area pattern in the photoresist layer. Then, the hard mask layer 202 is etched by taking the photoresist layer as a mask, so that the active region pattern in the photoresist layer is transferred into the hard mask layer 202, and then the photoresist layer is removed, thereby not only preventing the excessive depth of subsequent etching caused by the continuous existence of the photoresist layer, but also avoiding the excessive organic by-products generated in the subsequent etching process caused by the existence of the photoresist layer, and further ensuring the downward transfer precision of the active region pattern. Next, using the hard mask layer 202 with the active area pattern as a mask, the pad oxide layer 201 and a part of the thickness of the semiconductor substrate 200 are etched to form a plurality of active areas 200a in the semiconductor substrate 200, wherein trenches 203 are formed between adjacent active areas 200a, and the trenches 203 are used for forming an insulating isolation structure in the following to isolate adjacent elements, for example, to isolate adjacent memory cells.
Referring to fig. 4 to 7, in the step S3, the line width of the mask layer 202 is gradually reduced through an etching process, and after the line width of the mask layer 202 is reduced through each etching, the vertex angle of the active region 200a exposed by the mask layer is rounded, so as to finally trim the top surface of the active region 200a exposed by the mask layer 202 into an arc-shaped curved surface. In this embodiment, an example method for implementing step S3 includes the following steps:
s3.1.1 referring to fig. 4 and 5, a selective wet etching process is used to etch the sidewalls and the top wall of the mask layer 202 at the same time, thereby pushing back the mask layer 202 to reduce the line width of the mask layer 202 and reduce the height of the mask layer 202, at this time, the remaining mask layer after the pushing back is marked as 202a, and the line width of the mask layer 202a is relatively reduced, and at this time, the line width of the remaining mask layer 202a is smaller than the top line width of the active region 200 a. The selective wet etching process is performed by using an etchant, which is capable of making the mask layer 202 have a high etching selectivity with respect to the active region 200b, for example, when the mask layer 202 is silicon nitride, the etchant is a phosphoric acid solution, and the selective wet etching process is performed for 5 seconds to 20 minutes, for example, 1 minute to 20 minutes. When the pad oxide layer 201 exists, pushing back the mask layer 202 exposes a portion of the pad oxide layer 201 therebelow, and after pushing back the mask layer 202, further removing the pad oxide layer 201 to expose the top of the active region 200a outside the mask layer 202; when the pad oxide layer 201 is not present, the mask layer 202 is pushed back to expose the top of the underlying active region 200 a.
S3.1.2, referring to fig. 5, the exposed surface of the active region 200a may be surface-oxidized by using a Furnace thermal oxidation process (burn Oxide), an in-situ steam oxidation (ISSG Oxide), a wet oxidation (wet oxidation), or a Rapid Thermal Oxidation (RTO) process, which not only consumes the exposed surface of the active region 200a, but also repairs the damage previously suffered by the active region 200a, so as to form a surface Oxide layer (liner Oxide)204, the surface oxidation process forms the vertex angle of the active region (i.e. the top of the edge of the trench 203 a) into a rounded corner, and the remaining active region after surface oxidation is denoted as 200 b.
S3.1.3 referring to fig. 5 and 6, another selective wet etch process is used to remove the surface oxide layer 204, thereby re-exposing the surface of the active region 200 b. The selective wet etching process can make the surface oxide layer 204 have a high etching selectivity with respect to both the mask layer 202 and the active region 200 b. For example, when the semiconductor substrate 200 is silicon, the material of the surface oxide layer 204 is silicon dioxide, and the selected etchant is hydrofluoric acid solution, which does not cause unnecessary damage to the surface of the active region 200b, and the etching time is 5 seconds to 60 seconds. Due to the consumption and repair of the surface oxidation process, the surface of the active region 200b may become rounded with respect to the surface of the active region 200a, the overall line width of the active region 200b may be reduced with respect to the active region 200a in fig. 4, and the line width of the trench 203a may be increased with respect to the line width of the trench 203 in fig. 4.
S3.1.4 referring to fig. 5 to 7, steps S3.1.1 to S3.1.3 are performed several times until the top surface of the active region 200c is trimmed to the desired curved surface. Wherein the execution times is more than 1. In this process, since the top edge region (i.e., the top corner) of the active region is oxidized at a higher rate in step S3.1.2 relative to the rest of the active region, silicon in the top edge region of the active region is consumed more in step S3.1.3, and the top corner of the active region exposed by the mask layer with the further reduced line width is adjusted to be rounded every time steps S3.1.1 to S3.1.3 are performed, so that the top surface of the active region 200c can be curved after steps S3.1.1 to S3.1.3 are performed several times. At this time, the line width of the remaining mask layer 202b may be reduced to the minimum line width allowed by the process. In addition, since the surface oxidation process of step S3.1.2 is performed each time, oxygen and the semiconductor such as silicon on the surface of the active region are required to react and consume a certain thickness of the active region, the overall line width of the active region after step S3.1.3 is performed each time is reduced a little compared to the overall line width of the active region after the previous times, the overall line width of the finally formed active region 200c is reduced a little compared to the line width of the active region 200a initially formed in step S2, the width of the trench 203b is increased a little compared to the width of the trench 203 initially formed in step S2, and the overall surface of the active region 200c is more smooth compared to the active region 200 a.
In the method for implementing step S3, the etching time for etching the mask layer may be the same each time step S3.1.1 to step S3.1.3 are performed, so that the formed arc-shaped curved surface is relatively gentle and closer to an elliptical arc; it is also possible to make the etching time for etching the mask layer gradually shorter as the number of times steps S3.1.1 to S3.1.3 are performed increases, thereby making the implemented arc-shaped curved surface closer to an arc. In addition, the more times the steps S3.1.1 to S3.1.3 are performed, the smaller the line width change of each mask layer is, the more smooth the arc-shaped curved surface is, the closer to the arc is.
It should be noted that, in the above embodiments, the line width of the mask layer is gradually reduced by taking a method of etching and pushing back the mask layer in combination with surface oxidation of the active region as an example, and the vertex angle of the active region exposed by the mask layer each time is rounded, so that the top surface of the active region is finally trimmed to be the arc-shaped curved surface.
For example, the line width of the mask layer may be gradually reduced by a method of etching and pushing back the mask layer in combination with wet etching of the surface of the active region, and the top surface of the active region is trimmed to an arc-shaped curved surface, and the specific process includes:
s3.2.1, firstly, etching the mask layer by a selective wet etching process to reduce the line width of the mask layer;
s3.2.2, performing wet etching on the top corner of the active region exposed by the mask layer by using another selective wet etching process to make the top corner of the active region exposed by the mask layer round, wherein the etchant is a mixed solution of ammonium hydroxide, hydrogen peroxide and water;
s3.2.3, steps S3.2.1 through S3.2.2 are performed multiple times until the top surface of the active region is trimmed to the desired arcuate surface.
For another example, the line width of the mask layer can be gradually reduced by a method of etching and pushing the mask layer in combination with ion bombardment at the apex angle of the active region, and the top surface of the active region is trimmed into an arc-shaped curved surface, and the specific process comprises the following steps:
s3.2.1, firstly, etching the mask layer by a selective wet etching process to reduce the line width of the mask layer;
s3.2.2, performing ion bombardment on the top corner of the active region exposed by the mask layer, wherein the ions used by the ion bombardment include at least one of argon and helium, and when the top corner of the active region is subjected to ion bombardment, the ion sputtering rate at the top corner of the active region is higher, so that the ion bombardment can round part or all of the top corner;
s3.2.3, steps S3.2.1 through S3.2.2 are performed multiple times until the top surface of the active region is trimmed to the desired arcuate surface.
For another example, the line width of the mask layer may be gradually reduced by a method of combining the mask layer etching and pushing back with the active region surface wet etching and assisting with the ion bombardment at the vertex angle, and the top surface of the active region may be modified into an arc-shaped curved surface, and the specific process includes:
s3.2.1, firstly, etching the mask layer by a selective wet etching process to reduce the line width of the mask layer;
s3.2.2, performing wet etching on the top corner of the active region exposed by the mask layer by using another selective wet etching process, and performing ion bombardment on the top corner of the active region exposed by the mask layer before and/or after the wet etching to round part or all of the top corner, wherein ions used by the ion bombardment include at least one of argon and helium; when ion bombardment is carried out before wet etching, the efficiency of follow-up wet etching can be improved, the time is saved, the wet etching effect is improved, and when ion bombardment is carried out after the wet etching, the top angle of an active area can be roughened by the wet etching, so that a better process surface can be provided for the ion bombardment, and the efficiency of the ion bombardment is improved.
S3.2.3, steps S3.2.1 through S3.2.2 are performed multiple times until the top surface of the active region is trimmed to the desired arcuate surface.
With continued reference to fig. 7 and 8, in the step S4, first, an insulating isolation layer 205 may be deposited on the semiconductor substrate 200 and the finally remaining mask layer 202b by a high density plasma chemical vapor deposition (HDP CVD) process, and the deposited insulating isolation layer 205 at least fills the trench 203 b. The material of the insulating isolation layer 205 may include at least one of silicon oxide, tetraethylorthosilicate TEOS, silicon nitride, and silicon oxynitride. Then, a Chemical Mechanical Polishing (CMP) process may be used to planarize the top of the deposited insulating isolation layer 205 until the top surface of the mask layer 203b is exposed, and even further thinning until the remaining thickness of the insulating isolation layer 205 reaches the required thickness.
In step S5, referring to fig. 8 and 9, a selective wet etching process or a dry etching process may be used to remove the remaining mask layer 202b, and at this time, an opening 206 is formed at the position of the mask layer 202b, that is, the remaining mask layer 202b is used to define and open the opening of the insulating isolation layer 205, so that the insulating isolation layer 205 is not etched and etched by using a photolithography process to open the insulating isolation layer 205, the process is simplified, and the process cost is saved. When the selective wet etching process is used to remove the remaining mask layer 202b, the selective wet etching process may use substantially the same process conditions as the selective wet etching process used to reduce the line width of the mask layer in step S3, wherein only the etching time may be adjusted. Then, referring to fig. 9 and 10, another selective wet etching process is used to etch back the insulating isolation layer 205, i.e. push back the insulating isolation layer 205, so as to reduce the line width and height of the portion of the insulating isolation layer 205 higher than the top of the active region 200c, thereby forming the trench isolation structure 205 a. The etchant for etching back the insulating isolation layer 205 in this step may be the same as the etchant for the selective wet etching process for removing the surface oxide layer in step S3, and most process conditions are substantially the same, mainly the etching time is different, and the etching time for etching back the insulating isolation layer 205 is 30 seconds to 10 minutes.
The height of the trench isolation structure 205a obtained after the step S5 may be a height already meeting the device requirements, or may still be higher than the device requirements, and the height of the trench isolation structure 205a still too high may be further reduced in the subsequent processes.
Referring to fig. 11 to 13, when the semiconductor device to be fabricated is a code type flash memory, the height of the trench isolation structures 205a formed in step S5 is already the height meeting the device requirements, and the top of the trench isolation structures 205a is higher than the top of the active region 200c, and the openings 206a between adjacent trench isolation structures 205a are used to define the locations where the floating gates 208 are to be formed subsequently. Therefore, the mask layer remaining in step S3 can also avoid the need of using a photolithography process to form the opening 206a for forming the floating gate 208, which can simplify the process and save the process cost.
With continuing reference to fig. 11 to fig. 13, when the semiconductor device to be fabricated is a code type flash memory, after the step S5, the method further includes: a tunnel dielectric layer 207, a floating gate 208, an intergate dielectric layer 209 and a control gate 210 are sequentially formed. Wherein the control gate 210 and the active region 200c vertically intersect, the inter-gate dielectric layer 209 is sandwiched between the floating gate 208 and the control gate 210 and between the control gate 210 and the trench isolation structure 205a, the floating gate 208 is sandwiched between the control gate 210 and the active region 200c, and the tunneling dielectric layer 207 is sandwiched between the floating gate 208 and the active region 200 c. The specific process of the step comprises the following steps:
first, a tunnel dielectric layer 207 may be formed on the surface of the active region 200c through a thermal furnace process, a rapid thermal oxidation process, an in-situ steam generation (ISSG) process, a chemical vapor deposition (cvd) process, or the like, and the tunnel dielectric layer 207 may isolate the floating gate 208 and the active region 200c, which are subsequently formed. The process for forming tunnel dielectric layer 207 is conventional in the art and will not be described herein.
Next, a polysilicon layer may be deposited on the surfaces of the tunnel dielectric layer 207 and the trench isolation structure 205a by a deposition method commonly used in the art, such as chemical vapor deposition. When the height of the trench isolation structure 205a is sufficiently high, the polysilicon layer may be further planarized by a chemical mechanical polishing process to expose the top of the trench isolation structure 205a, and the remaining polysilicon layer has a thickness that meets the floating gate thickness requirement to form the floating gate 208. When the height of the trench isolation structure 205a is not high enough, a hard mask layer may be further deposited on the polysilicon layer and coated with a photoresist layer, the polysilicon layer may be further etched by photolithography and etching processes to expose a portion of the surface of the active region 200c, and the photoresist layer and the hard mask layer may be removed to form the floating gate 208. The processes in both cases are conventional in the art and will not be described in detail here. In addition, after the floating gate 208 is formed, if the height of the trench isolation structure 205a is still too high, a dry etching process may be further adopted to etch back the top of the trench isolation structure 205a until the height of the trench isolation structure 205a meets the requirement.
Then, an oxide layer, a nitride layer, and an oxide layer are sequentially deposited on the surfaces of the floating gate 208, the active region 200c, and the trench isolation structure 205a by a chemical vapor deposition process to form an inter-gate dielectric layer 209 (i.e., an ONO structure).
Thereafter, a polysilicon layer may be deposited on the inter-gate dielectric layer 209 by a deposition method commonly used in the art, such as chemical vapor deposition, and the polysilicon layer may be patterned by photolithography and etching processes to form the control gate 210.
The device manufacturing process after forming the control gate 210 may refer to a corresponding process flow of a flash memory in the prior art, and is not described herein again.
In addition, when the semiconductor device to be manufactured is other non-floating gate type memory or other non-memory semiconductor device, the floating gate and the inter-gate dielectric layer can be omitted.
The following will specifically describe the improvement of the technical solution of the present invention over the prior art and the technical effect brought by the improvement with reference to fig. 12 and 14 to 15. Fig. 14 is a schematic cross-sectional view of a conventional code flash memory. FIG. 15 is a diagram illustrating comparison of recognition windows under the same design rule between the present invention and the prior art.
Referring to fig. 14, the conventional code flash memory also includes a semiconductor substrate 100, a trench isolation structure 101, a tunneling dielectric layer 102, a floating gate 103, an inter-gate dielectric layer 104, and a control gate 105, wherein the trench isolation structure 101 defines a plurality of active regions with an effective channel width a in the semiconductor substrate 100, and a top surface of each active region is a flat surface. Please refer to fig. 12 and fig. 14, in the same design rule: when the design width of the active region is a, as shown in fig. 12, the scheme of the present invention modifies the top surface of the active region into an arc-shaped curved surface, which is between the elliptical arc and the circular arc, and the maximum ideal value is the circular arc, at this time, the width a of the top of the active region shown in fig. 14 is the diameter of the circle where the circular arc shown in fig. 12 is located, and the arc length of the circular arc on the top surface of the active region shown in fig. 12 is 3.14A. When the top surface of the active region shown in fig. 12 is modified to be an arc-shaped curved surface, and the arc-shaped curved surface is between the elliptical arc and the circular arc, the arc length of the arc-shaped curved surface is between a and 3.14A, that is, the effective channel width W is increased to 1 to 3.14 times of the effective channel width of the structure shown in fig. 14, according to the conduction current formula, the conduction current of the structure shown in fig. 12 can be increased to 1 to 3.14 times of the conduction current of the structure shown in fig. 14, so as to effectively improve the problem that the conduction current is too small. With further reference to FIG. 15, the t-1 generation technology recognition window D2 of the structure shown in FIG. 12 is significantly increased compared to the t-1 generation technology recognition window D1 of the structure shown in FIG. 14. Therefore, compared with the prior art, the technical scheme of the invention can effectively increase the identification windows of the programming state and the erasing state and improve the repeatable erasing times of the memory. In addition, the increase in on-current may also provide speed of the device.
Moreover, under the same design rule, under the condition that the requirement of the effective channel width is the same as that of the prior art, the design of the active region with the arc-shaped curved surface on the top surface can be favorable for further reducing the line width of the active region, so that the technical scheme of the invention provides the possibility of continuous micro technology, and is more favorable for obtaining smaller chip area on the premise of the product performance equal to that of the prior art, thereby improving the product competitiveness and reducing the production cost.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (11)
1. A method of manufacturing a semiconductor device, comprising the steps of:
s1, providing a semiconductor substrate, and forming a mask layer on the semiconductor substrate;
s2, performing active area etching on the mask layer and the semiconductor substrate to form a plurality of active areas in the semiconductor substrate, wherein a groove is formed between every two adjacent active areas;
s3, gradually reducing the line width of the mask layer, and trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface;
s4, filling an insulation isolation layer in the groove, wherein the insulation isolation layer also exposes the top surface of the residual mask layer;
and S5, removing the mask layer, and etching back the insulation isolation layer to form a trench isolation structure.
2. The manufacturing method according to claim 1, wherein in the step S1, before forming the mask layer on the semiconductor substrate, the semiconductor substrate is further subjected to thermal oxidation to form a pad oxide layer.
3. The method of claim 1, wherein in step S3, the step of gradually reducing the line width of the mask layer and trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface comprises:
s3.1.1, etching at least the side wall of the mask layer to reduce the line width of the mask layer;
s3.1.2, surface oxidizing the active area to form a surface oxide layer;
s3.1.3, removing the surface oxide layer to re-expose the surface of the active region;
s3.1.4, steps S3.1.1 through S3.1.3 are performed multiple times until the top surface of the active region is trimmed to the desired arcuate surface.
4. The method of claim 1 or 3, wherein in step S3, a selective wet etching process is used to simultaneously etch the sidewalls and the top wall of the mask layer, so as to reduce the height of the mask layer while reducing the line width of the mask layer.
5. The method of claim 4, wherein the mask layer formed in step S1 is made of silicon nitride; in step S3, the etchant of the wet etching process includes a phosphoric acid solution, and the etching time is 5 seconds to 20 minutes.
6. The method of claim 3, wherein in step S3.1.3, another selective wet etch process is used to remove the surface oxide layer.
7. The method of claim 3, wherein in the step S3.1.4, the etching time for etching the mask layer is the same for each etching, or gradually decreases as the number of times steps S3.1.1 to S3.1.3 are performed, so as to trim the top surface of the active region into an arc-shaped curved surface.
8. The method of claim 1, wherein in step S3, the step of gradually reducing the line width of the mask layer and trimming the top surface of the active region exposed by the mask layer into an arc-shaped curved surface comprises:
s3.2.1, etching at least the side wall of the mask layer to reduce the line width of the mask layer;
s3.2.2, performing wet etching and/or ion bombardment on the top corner of the active region exposed by the mask layer to round the top corner of the active region exposed by the mask layer;
s3.2.3, steps S3.2.1 through S3.2.2 are performed multiple times until the top surface of the active region is trimmed to the desired arcuate surface.
9. The method of manufacturing of claim 1, wherein the step of filling the trench with an insulating isolation layer in step S4 comprises:
depositing an insulating isolation layer on the semiconductor substrate and the mask layer, wherein the deposited insulating isolation layer at least fills the groove;
and carrying out top planarization on the deposited insulating isolation layer until the top surface of the mask layer is exposed.
10. The method according to claim 1, wherein in step S5, the insulating isolation layer is etched back by a wet etching process to form the trench isolation structure.
11. The manufacturing method according to claim 1, characterized in that after the step S5, the manufacturing method further comprises the steps of: and sequentially forming a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate, wherein the control gate is intersected with the active region, the inter-gate dielectric layer is sandwiched between the floating gate and the control gate and between the control gate and the trench isolation structure, the floating gate is sandwiched between the control gate and the active region, and the tunneling dielectric layer is sandwiched between the floating gate and the active region.
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| CN1481584A (en) * | 2000-12-14 | 2004-03-10 | �����ɷ� | Non-volatile semiconductor memory cell and method for producing same |
| CN1399310A (en) * | 2001-07-27 | 2003-02-26 | 旺宏电子股份有限公司 | Dry chemical etching process to form round edge |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |