CN111739817A - Grinding and thinning method for semiconductor epitaxial wafer - Google Patents
Grinding and thinning method for semiconductor epitaxial wafer Download PDFInfo
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- CN111739817A CN111739817A CN201910228085.1A CN201910228085A CN111739817A CN 111739817 A CN111739817 A CN 111739817A CN 201910228085 A CN201910228085 A CN 201910228085A CN 111739817 A CN111739817 A CN 111739817A
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- grinding
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- epitaxial wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
Abstract
The invention discloses a grinding and thinning method of a semiconductor epitaxial wafer, which mainly comprises the following steps of S1 providing a substrate for pretreatment; s2, reversely buckling the epitaxial wafer on the top of the tray; s3, measuring whether the surface to be ground of the semiconductor is a horizontal surface or not through a level meter; s4, fixing the semiconductor on the top of the tray by the clamping mechanism; s5, grinding the surface to be ground of the semiconductor for the first time through a grinding mechanism; s6, grinding the surface to be ground of the semiconductor for the second time through a grinding mechanism; s7, grinding the surface to be ground of the semiconductor for the third time through the grinding mechanism, the invention can ensure more stable and reliable grinding of the workpiece by placing the workpiece to be processed on the base with the clamping mechanism, and meanwhile, the invention adopts a multi-section grinding mode to ensure the grinding quality, effectively reduce the probability of fragment and increase the yield.
Description
Technical Field
The invention relates to the technical field of processing, in particular to a grinding and thinning method of a semiconductor epitaxial wafer.
Background
In most semiconductor crystal growth processes, heteroepitaxy is mainly adopted, a certain lattice constant mismatch exists between a growth substrate and a semiconductor crystal material, so that a buffer layer is preset in epitaxial growth to adjust the stress among the materials, and in the growth process, the growth substrate warps due to the fact that the lattice constant of part of the semiconductor material is smaller than that of the growth substrate, and a material crystal accumulation layer can be formed on the edge of the growth substrate. In the subsequent semiconductor device process, the substrate is generally required to be thinned because the growth substrate is thicker. However, in the above epitaxial process, the thickness of the crystal accumulation layer at the edge of the substrate is thicker than the height of the device, so that the surface of the epitaxial wafer on which the semiconductor crystal material layer grows is uneven, grinding fragments are caused in the grinding process, and the yield is reduced.
Disclosure of Invention
The invention aims to provide a method for grinding and thinning a semiconductor epitaxial wafer so as to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme: a grinding and thinning method for a semiconductor epitaxial wafer comprises the following steps:
s1 providing a base for pretreatment, the base including a tray for supporting semiconductor substrates and a chucking mechanism provided at both sides of the tray, and the top of the tray being a horizontal plane;
s2, the epitaxial wafer with the semiconductor crystal layer is reversely buckled on the top of the tray and is bonded with the top of the tray through a bonding layer, and the crystal stacking bulge at the edge of the substrate is arranged on the periphery of the tray;
s3, measuring whether the surface to be ground of the semiconductor is a horizontal surface or not through a level meter, and if the surface to be ground of the semiconductor is not the horizontal surface, continuing to adjust the position of the semiconductor on the top of the tray;
s4, when the top of the tray is horizontal, the semiconductor to be ground is fixed on the top of the tray through the clamping mechanism;
s5, grinding the surface to be ground of the semiconductor for the first time through a grinding mechanism to thin the surface to be ground of the semiconductor to a first preset thickness;
s6, grinding the surface to be ground of the semiconductor for the second time through the grinding mechanism to thin the surface to be ground of the semiconductor to a second preset thickness;
and S7, grinding the surface to be ground of the semiconductor for the third time through a grinding mechanism to thin the surface to be ground of the semiconductor to a third preset thickness.
Preferably, the first preset thickness is 2.0 to 2.5 μm; the second preset thickness is 1.0-1.5 mu m; the third preset thickness is 0.05-0.5 μm.
Preferably, the first grinding, the second grinding and the third grinding are all added with grinding fluid.
Preferably, the method further comprises step S8 of cleaning the semiconductor polishing surface with a cleaning solution.
Preferably, the method further comprises S9 detecting whether the thickness of the cleaned semiconductor is a threshold thickness by a measuring instrument, and if not, continuing to the steps S7 to S8.
Compared with the prior art, the invention has the beneficial effects that:
the workpiece to be processed is placed on the base with the clamping mechanism, so that the workpiece to be processed can be more stable and reliable during grinding, meanwhile, a multi-section grinding mode is adopted, the grinding quality can be ensured, the fragment probability is effectively reduced, and the yield is increased.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic view of a base structure according to the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise. .
Referring to fig. 1, the present embodiment provides a technical solution: a grinding and thinning method for a conductor epitaxial wafer comprises the following steps:
s1 providing a base 1 for pretreatment, the base 1 including a tray 2 for supporting semiconductor substrates and a chucking mechanism 4 disposed at both sides of the tray, and the top of the tray 2 being a horizontal plane; s2, the epitaxial wafer with the epitaxial growth semiconductor 3 crystal layer is buckled on the top of the tray 2, and is bonded with the top of the tray 2 through a bonding layer, and the crystal stacking bulge at the edge of the substrate is arranged on the periphery of the tray 2; s3, measuring whether the surface to be ground of the semiconductor 3 is a horizontal surface by a level meter, and if not, continuing to adjust the position of the semiconductor 3 on the top of the tray 2; s4, when the top of the tray 2 is horizontal, the semiconductor 3 is fixed on the top of the tray 2 by the clamping mechanism 4; s5, grinding the surface to be ground of the semiconductor 3 for the first time through a grinding mechanism to thin the surface to be ground of the semiconductor 3 to a first preset thickness; s6, grinding the surface to be ground of the semiconductor 3 for the second time through the grinding mechanism to thin the surface to be ground of the semiconductor 3 to a second preset thickness; and S7, grinding the surface to be ground of the semiconductor 3 for the third time through the grinding mechanism to thin the surface to be ground of the semiconductor 3 to a third preset thickness. Through with treating on the piece as for the base that has fixture, can ensure more reliable and stable when grinding it, adopt the grinding mode of multistage formula simultaneously, can ensure to grind the quality, effectively reduce the fragmentation probability simultaneously, increase the yield.
In this embodiment, the first predetermined thickness is 2.0 μm to 2.5 μm; the second preset thickness is 1.0-1.5 mu m; the third preset thickness is 0.05-0.5 mu m; wherein, the optimized first preset grinding is 2.0 μm thick, the second preset grinding is 1.0 μm thick, and the third preset grinding is 0.5 μm thick; by adopting the grinding mode of descending, the grinding effect can be further ensured, and the yield is improved.
In this embodiment, the polishing liquid is added in each of the first polishing, the second polishing, and the third polishing to protect the polishing disc and the semiconductor, and the polishing liquid may be water or a mixture of silicon dioxide and water.
In addition, in this embodiment, the method further includes step S8 of cleaning the polished surface of the semiconductor 3 with a cleaning solution; s9, detecting whether the thickness of the cleaned semiconductor 3 is a threshold thickness by a measuring instrument, and if not, continuing to the steps S7 to S8; after the third grinding is finished, the grinding fluid and the grinding particles on the grinding surface of the semiconductor need to be removed through cleaning fluid, and after the cleaning is finished, the measurement and confirmation of a finished product need to be carried out, so that whether the semiconductor meets the grinding thinning threshold value or not.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Exemplary embodiments according to the present application will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art, in the drawings, it is possible to enlarge the thicknesses of layers and regions for clarity, and the same devices are denoted by the same reference numerals, and thus the description thereof will be omitted.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A grinding and thinning method for a semiconductor epitaxial wafer is characterized by comprising the following steps:
s1 providing a base for pretreatment, the base including a tray for supporting semiconductor substrates and a chucking mechanism provided at both sides of the tray, and the top of the tray being a horizontal plane;
s2, the epitaxial wafer with the semiconductor crystal layer is reversely buckled on the top of the tray and is bonded with the top of the tray through a bonding layer, and the crystal stacking bulge at the edge of the substrate is arranged on the periphery of the tray;
s3, measuring whether the surface to be ground of the semiconductor is a horizontal surface or not through a level meter, and if the surface to be ground of the semiconductor is not the horizontal surface, continuing to adjust the position of the semiconductor on the top of the tray;
s4, when the top of the tray is horizontal, the semiconductor to be ground is fixed on the top of the tray through the clamping mechanism;
s5, grinding the surface to be ground of the semiconductor for the first time through a grinding mechanism to thin the surface to be ground of the semiconductor to a first preset thickness;
s6, grinding the surface to be ground of the semiconductor for the second time through the grinding mechanism to thin the surface to be ground of the semiconductor to a second preset thickness;
and S7, grinding the surface to be ground of the semiconductor for the third time through a grinding mechanism to thin the surface to be ground of the semiconductor to a third preset thickness.
2. The grinding and thinning method for the semiconductor epitaxial wafer as claimed in claim 1, wherein: the first preset thickness is 2.0-2.5 mu m; the second preset thickness is 1.0-1.5 mu m; the third preset thickness is 0.05-0.5 μm.
3. The grinding and thinning method for the semiconductor epitaxial wafer as claimed in claim 1, wherein: and adding grinding fluid into the first grinding, the second grinding and the third grinding.
4. The grinding and thinning method for the semiconductor epitaxial wafer as claimed in claim 1, wherein: and S8, cleaning the semiconductor grinding surface by using the cleaning liquid.
5. The grinding and thinning method for the semiconductor epitaxial wafer as claimed in claim 4, wherein: s9, the method includes detecting whether the thickness of the cleaned semiconductor is a threshold thickness by a measuring instrument, and if not, continuing to the steps S7-S8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910228085.1A CN111739817A (en) | 2019-03-25 | 2019-03-25 | Grinding and thinning method for semiconductor epitaxial wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910228085.1A CN111739817A (en) | 2019-03-25 | 2019-03-25 | Grinding and thinning method for semiconductor epitaxial wafer |
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| Publication Number | Publication Date |
|---|---|
| CN111739817A true CN111739817A (en) | 2020-10-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910228085.1A Pending CN111739817A (en) | 2019-03-25 | 2019-03-25 | Grinding and thinning method for semiconductor epitaxial wafer |
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| Country | Link |
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| CN (1) | CN111739817A (en) |
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- 2019-03-25 CN CN201910228085.1A patent/CN111739817A/en active Pending
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