CN111739473A

CN111739473A - GOA unit, driving method thereof, GOA driving circuit and display device

Info

Publication number: CN111739473A
Application number: CN202010725323.2A
Authority: CN
Inventors: 于洋
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-07-24
Filing date: 2020-07-24
Publication date: 2020-10-02
Anticipated expiration: 2040-07-24
Also published as: CN111739473B

Abstract

The application provides a GOA unit, a driving method of the GOA unit, a GOA driving circuit and a display device. The GOA unit comprises a front-end GOA unit and an inverter circuit, wherein the front-end GOA unit can output a low-level signal output by a signal input end to a negative voltage output end under the control of the signal input end and a first clock signal end; the inverter circuit can output a high-level signal output by the first power supply voltage end to the positive voltage output end under the control of the negative voltage output end and the second clock signal end; and outputting the low level signal output by the second power supply voltage end to the positive voltage output end under the control of the second clock signal end; the GOA unit in the embodiment of the application can simultaneously output a positive voltage pulse signal for driving the N-type thin film transistor and a negative voltage pulse signal for driving the P-type thin film transistor, and the output waveform is smooth.

Description

GOA unit, driving method thereof, GOA driving circuit and display device

Technical Field

The application relates to the technical field of display, in particular to a GOA unit, a driving method thereof, a GOA driving circuit and a display device.

Background

Compared with the conventional liquid crystal display, the Active Matrix Organic Light Emitting Diode (AMOLED) display panel has the advantages of high response speed, no need of a backlight, higher contrast ratio, Light and thin overall structure, wide viewing angle, flexibility and the like, and has wider application prospect.

In an AMOLED display panel, a special pixel circuit is often required to be designed to convert a control signal into a current signal required for the OLED device to emit light. In a conventional Low Temperature Polysilicon (LTPS) type P-type silicon semiconductor device, a P-type low temperature polysilicon thin film transistor is used for designing a pixel circuit. The oxide thin film transistor has lower leakage current than LTPS, and if the oxide thin film transistor is introduced into a pixel circuit, the voltage holding ratio of the pixel can be improved, so that the low-frequency display performance is improved.

A conventional LTPS thin film transistor is a P-type thin film transistor, and an oxide thin film transistor is generally an N-type thin film transistor, and therefore, in a display panel (i.e., a low temperature polysilicon oxide display panel) in which the LTPS thin film transistor and the oxide thin film transistor are simultaneously disposed, a gate driver array (GOA) circuit is required to simultaneously output a positive voltage pulse signal for driving the N-type thin film transistor and a negative voltage pulse signal for driving the P-type thin film transistor. However, the applicant finds that the conventional GOA circuit has the problem that the output waveform has a shoulder and is not smooth.

Disclosure of Invention

In view of this, the present application provides a GOA unit and a driving method thereof, a GOA driving circuit, and a display device, so as to solve the technical problem in the prior art that an output waveform of a GOA circuit has a shoulder and is not smooth.

In order to solve the above problem, the embodiments of the present application mainly provide the following technical solutions:

in a first aspect, an embodiment of the present application discloses a GOA unit, including:

the front-end GOA unit is respectively electrically connected with a first clock signal end, a first power supply voltage end, a second power supply voltage end, a frame starting signal input end, a signal input end and a negative voltage output end, and is used for outputting a low-level signal output by the signal input end to the negative voltage output end under the control of the signal input end and the first clock signal end, and the negative voltage output end is a first output end of the GOA unit;

the inverter circuit is respectively electrically connected with the negative voltage output end, the second clock signal end, the first power supply voltage end, the second power supply voltage end and the positive voltage output end, and is used for outputting a high-level signal output by the first power supply voltage end to the positive voltage output end under the control of the negative voltage output end and the second clock signal end, and the positive voltage output end is a second output end of the GOA unit; and outputting the low level signal output by the second power voltage terminal to the positive voltage output terminal under the control of the second clock signal terminal.

Optionally, the inverter circuit comprises an output control circuit, a first transistor and a second transistor;

the output control circuit is respectively electrically connected with the negative voltage output end, the first power supply voltage end, the positive voltage output end, the second power supply voltage end, the second clock signal end and the control end of the first transistor, and is used for outputting a high-level signal output by the first power supply voltage end to the positive voltage output end under the control of the negative voltage output end and the second clock signal end;

the control end of the first transistor is electrically connected with the first pole of the second transistor, the first pole of the first transistor is connected with the second power supply voltage end, and the second pole of the first transistor is connected with the positive voltage output end;

the control end and the second pole of the second transistor are both connected with the positive voltage output end;

the first transistor and the second transistor are used for outputting a low-level signal output by the second power supply voltage end to the positive voltage output end under the control of the second clock signal end.

Optionally, the output control circuit comprises a third transistor, a fourth transistor and a fifth transistor;

the control end of the third transistor is connected with the negative voltage output end, the first pole of the third transistor is connected with the first power supply voltage end, and the second pole of the third transistor is connected with the positive voltage output end;

the control end of the fourth transistor is connected with the negative voltage output end, the first pole of the fourth transistor is connected with the first power supply voltage end, and the second pole of the fourth transistor is respectively connected with the control end of the first transistor and the first pole of the second transistor;

the control end of the fifth transistor is connected with the second clock signal end, the first pole of the fifth transistor is connected with the second power supply voltage end, and the second pole of the fifth transistor is respectively connected with the control end of the first transistor and the first pole of the second transistor.

Optionally, the front-end GOA unit includes an input circuit, an output circuit, a pull-up control circuit, and a pull-up circuit;

the input circuit is respectively connected with the first clock signal end, the frame starting signal input end and the pull-down node, and is used for outputting a low-level signal output by the frame starting signal input end to the pull-down node under the control of the first clock signal end so as to pull down the potential of the pull-down node;

the pull-up control circuit is respectively connected with the first clock signal end, the second power voltage end, a pull-up node, the pull-down node, the signal input end and the pull-up circuit, and is used for outputting a low-level voltage signal to the pull-up node under the control of the first clock signal end, the signal input end and the pull-down node so as to pull down the potential of the pull-up node and control the pull-up circuit to operate; and outputting a high-level voltage signal to the pull-up node under the control of the first clock signal terminal, the signal input terminal and the pull-down node to pull up the potential of the pull-up node, and controlling the pull-up circuit not to operate;

the pull-up circuit is respectively connected with the pull-up node, the first power supply voltage end, the pull-up control circuit and the negative voltage output end, and is used for outputting a high-level signal output by the first power supply voltage end to the negative voltage output end under the control of the pull-up node;

the output circuit is respectively connected with the second power supply voltage end, the pull-down node, the signal input end, the pull-up circuit and the negative voltage output end, and is used for outputting a low-level signal output by the signal input end to the negative voltage output end under the control of the pull-down node and the pull-up node.

Optionally, the input circuit comprises a sixth transistor; the output circuit comprises a seventh transistor, an eighth transistor and a first capacitor;

a control end of the sixth transistor is connected with the first clock signal end, a first pole of the sixth transistor is connected with the frame starting signal input end, and a second pole of the sixth transistor is connected with the pull-down node;

the control end of the seventh transistor is respectively connected with the second pole of the eighth transistor and one end of the first capacitor, the first pole of the seventh transistor is respectively connected with the negative voltage output end and the pull-up circuit, and the second pole of the seventh transistor is connected with the signal input end;

a control end of the eighth transistor is connected with the second power supply voltage end, a first pole of the eighth transistor is connected with the pull-down node, and a second pole of the eighth transistor is connected with a control end of the seventh transistor;

the other end of the first capacitor is connected with the negative voltage output end.

Optionally, the pull-up control circuit comprises: a ninth transistor, a tenth transistor, and an eleventh transistor;

a control end of the ninth transistor is connected with the pull-down node, a first pole of the ninth transistor is respectively connected with a second pole of the tenth transistor and the pull-up node, and a second pole of the ninth transistor is connected with the first clock signal end;

a control end of the tenth transistor is connected with the first clock signal end, a first pole of the tenth transistor is connected with the second power voltage end, and a second pole of the tenth transistor is connected with the pull-up node;

and the control end of the eleventh transistor is connected with the signal input end, the first pole of the eleventh transistor is connected with the pull-up circuit, and the second pole of the eleventh transistor is connected with the pull-down node.

Optionally, the pull-up circuit comprises: a twelfth transistor, a thirteenth transistor, and a second capacitor;

a control end of the twelfth transistor is respectively connected with the pull-up node and one end of the second capacitor, a first pole of the twelfth transistor is connected with the first power supply voltage end, and a second pole of the twelfth transistor is connected with the negative voltage output end;

a control end of the thirteenth transistor is connected with a pull-up node, a first pole of the thirteenth transistor is connected with the first power supply voltage end, and a second pole of the thirteenth transistor is connected with the pull-up control circuit;

the other end of the second capacitor is connected with the first power supply voltage end.

In a second aspect, an embodiment of the present application discloses a GOA driving circuit, including N cascaded GOA units, where each GOA unit is the GOA unit described in the first aspect, and N is an integer greater than or equal to 2.

In a third aspect, an embodiment of the present application discloses a display device, which includes the GOA driving circuit described in the second aspect.

In a fourth aspect, an embodiment of the present application discloses a driving method for a GOA unit, where the method is used for the GOA unit in the first aspect, and includes:

receiving the output signals of the signal input end and the first clock signal end, and driving the negative voltage output end to output a low level signal;

and receiving output signals of the negative voltage output end and the second clock signal end, and driving the positive voltage output end to output a high-level signal.

By means of the technical scheme, the technical scheme provided by the embodiment of the application at least has the following advantages:

because the GOA unit of the embodiment of the application comprises: the device comprises a front-end GOA unit and an inverter circuit, wherein the front-end GOA unit can output a low-level signal output by a signal input end to a negative voltage output end under the control of the signal input end and a first clock signal end, and the negative voltage output end is a first output end of the GOA unit; the inverter circuit can output a high-level signal output by the first power supply voltage end to the positive voltage output end under the control of the negative voltage output end and the second clock signal end, and the positive voltage output end is a second output end of the GOA unit; and outputting the low level signal output by the second power supply voltage end to the positive voltage output end under the control of the second clock signal end; therefore, the GOA unit in the embodiment of the present application can simultaneously output a positive voltage pulse signal for driving the N-type thin film transistor and a negative voltage pulse signal for driving the P-type thin film transistor; and the applicant obtains through experimental simulation, the GOA unit of the embodiment of the present application has smoother output waveform compared with the GOA unit of the prior art.

The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and the embodiments of the present application can be implemented according to the content of the description in order to make the technical means of the embodiments of the present application more clearly understood, and the detailed description of the embodiments of the present application will be given below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present application more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the alternative embodiments. The drawings are only for purposes of illustrating alternative embodiments and are not to be construed as limiting the embodiments of the present application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a block diagram of a GOA unit according to an embodiment of the present disclosure;

fig. 2 is a block diagram of a specific structure of a GOA unit according to an embodiment of the present disclosure;

fig. 3 is a circuit diagram of a GOA unit according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram of the GOA unit shown in FIG. 3;

fig. 5 is a circuit diagram of a GOA unit in the first stage of operation according to an embodiment of the present disclosure;

FIG. 6 is a circuit diagram of a GOA unit in a second stage according to an embodiment of the present invention;

fig. 7 is a circuit diagram of a GOA unit in the third stage of operation according to the embodiment of the present disclosure;

fig. 8 is a circuit diagram of a GOA unit in a fourth stage according to an embodiment of the present disclosure;

fig. 9 is a flowchart of a driving method of a GOA unit according to an embodiment of the present disclosure.

The reference numerals are introduced as follows:

1-GOA unit; 2-front end GOA unit; a 3-inverter circuit; 31-an output control circuit; 4-an input circuit; 5-an output circuit; 6-a pull-up control circuit; 7-pull-up circuit.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is to be understood that the term "and/or" as used herein is intended to include all or any and all combinations of one or more of the associated listed items.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The following describes in detail a specific circuit of the GOA unit and its operating principle according to the embodiments of the present application with reference to the drawings.

In a first aspect, as shown in fig. 1, the present application discloses a GOA unit 1. The GOA unit 1 includes: front end GOA unit 2 and inverter circuit 3, front end GOA unit 2 is connected with first clock signal end CK, first power voltage end VGH, second power voltage end VGL, frame initial signal input end STV, signal input part CB and negative voltage output end P-output electricity respectively, be used for under the control of signal input part CB and first clock signal end CK, the low level signal output of signal input part CB is exported to negative voltage output end P-output, negative voltage output end P-output is GOA unit 1's first output. The inverter circuit 3 is electrically connected to the negative voltage output terminal P-output, the second clock signal terminal CK1, the first power voltage terminal VGH, the second power voltage terminal VGL, and the positive voltage output terminal N-output, respectively, and is configured to output a high level signal output by the first power voltage terminal VGH to the positive voltage output terminal N-output under the control of the negative voltage output terminal P-output and the second clock signal terminal CK1, where the positive voltage output terminal N-output is a second output terminal of the GOA unit 1; and, under the control of the second clock signal terminal CK1, outputting the low level signal output from the second power voltage terminal VGL to the positive voltage output terminal N-output.

Because GOA unit 1 of the embodiment of the present application includes: the front-end GOA unit 2 and the inverter circuit 3, the front-end GOA unit 2 can output a low level signal output by the signal input end CB to a negative voltage output end P-output under the control of the signal input end CB and the first clock signal end CK, and the negative voltage output end P-output is a first output end of the GOA unit 1; the inverter circuit 3 is capable of outputting a high level signal output by the first power supply voltage terminal VGH to a positive voltage output terminal N-output under the control of the negative voltage output terminal P-output and the second clock signal terminal CK1, where the positive voltage output terminal N-output is the second output terminal of the GOA unit 1; and outputting the low level signal output from the second power voltage terminal VGL to the positive voltage output terminal N-output under the control of the second clock signal terminal CK 1; therefore, the GOA unit 1 in the embodiment of the present application can simultaneously output a positive voltage pulse signal for driving the N-type thin film transistor and a negative voltage pulse signal for driving the P-type thin film transistor; and the applicant obtains through experimental simulation, the GOA unit 1 of the embodiment of the present application has smoother output waveform compared with the GOA unit of the prior art.

In the embodiment of the present application, the first output terminal is connected to a gate of an LTPS thin film transistor disposed in the low temperature polysilicon oxide display panel, and the first output terminal outputs a low level signal to drive the LTPS thin film transistor; the second output end is connected with a grid electrode of an oxide thin film transistor arranged in the low-temperature polycrystalline silicon oxide display screen, and the second output end outputs a high-level signal to drive the oxide thin film transistor.

Alternatively, fig. 2 and fig. 3 respectively show a specific structural block diagram and a circuit diagram of a GOA unit in an embodiment of the present application. As shown in fig. 2 and 3, the inverter circuit 3 includes an output control circuit 31, a first transistor T10, and a second transistor T13. The output control circuit 31 is electrically connected to the negative voltage output terminal P-output, the first power voltage terminal VGH, the positive voltage output terminal N-output, the second power voltage terminal VGL, the second clock signal terminal CK1, and the control terminal of the first transistor T10, and is configured to output the high level signal output by the first power voltage terminal VGH to the positive voltage output terminal N-output under the control of the negative voltage output terminal P-output and the second clock signal terminal CK 1. The control terminal of the first transistor T10 is electrically connected to the first pole of the second transistor T13, the first pole is connected to the second power voltage terminal VGL, and the second pole is connected to the positive voltage output terminal N-output. The control terminal and the second pole of the second transistor T13 are both connected to the positive voltage output terminal N-output. And a first transistor T10 and a second transistor T13 for outputting a low level signal output from the second power voltage terminal VGL to the positive voltage output terminal N-output under the control of the second clock signal terminal CK 1.

In the embodiment of the present application, the second transistor T13 is arranged to feed back the output waveform of the positive voltage output terminal N-output to the gate of the first transistor T10, and compared with the way of arranging a capacitor for feedback, the arrangement of the second transistor T13 enables the first transistor T10 to be turned on faster, so that the falling edge is more ideal, and the output waveform is smoother. In addition, in order to simulate a real application scene, the inventor of the present application performs simulation on the GOA unit in the embodiment of the present application, the positive voltage output N-output is simulated by adding a 40 picofarad capacitor and a 40 ohm resistor, and the output waveform obtained through simulation shows that the GOA unit can output a steeper forward pulse and the output waveform is smoother.

Alternatively, as shown in fig. 3, the output control circuit 31 includes a third transistor T9, a fourth transistor T11, and a fifth transistor T12. The control terminal of the third transistor T9 is connected to the negative voltage output terminal P-output, the first pole is connected to the first power voltage terminal VGH, and the second pole is connected to the positive voltage output terminal N-output. A control terminal of the fourth transistor T11 is connected to the negative voltage output terminal P-output, a first pole is connected to the first power voltage terminal VGH, and a second pole is connected to the control terminal of the first transistor T10 and the first pole of the second transistor T13, respectively. The control terminal of the fifth transistor T12 is connected to the second clock signal terminal CK1, the first pole is connected to the second power voltage terminal VGL, and the second pole is connected to the control terminal of the first transistor T10 and the first pole of the second transistor T13, respectively.

Alternatively, with continued reference to fig. 2 and 3, the front-end GOA unit 2 includes an input circuit 4, an output circuit 5, a pull-up control circuit 6 and a pull-up circuit 7. The input circuit 4 is respectively connected to the first clock signal terminal CK, the frame start signal input terminal STV and the pull-down node N1, and is configured to output a low level signal output from the frame start signal input terminal STV to the pull-down node N1 under the control of the first clock signal terminal CK, so as to pull down the potential of the pull-down node N1. And the output circuit 5 is respectively connected with the second power supply voltage terminal VGL, the pull-down node N1, the signal input terminal CB, the pull-up circuit 7 and the negative voltage output terminal P-output, and is used for outputting a low-level signal output by the signal input terminal CB to the negative voltage output terminal P-output under the control of the pull-down node N1 and the pull-up node N2. The pull-up control circuit 6 is respectively connected with the first clock signal terminal CK, the second power voltage terminal VGL, the pull-up node N2, the pull-down node N1, the signal input terminal CB and the pull-up circuit 7, and is used for outputting a low-level voltage signal to the pull-up node N2 under the control of the first clock signal terminal CK, the signal input terminal CB and the pull-down node N1, so as to pull down the potential of the pull-up node N2 and control the pull-up circuit 7 to operate; and, under the control of the first clock signal terminal CK, the signal input terminal CB, and the pull-down node N1, outputting a high level voltage signal to the pull-up node N2 to pull up the potential of the pull-up node N2, controlling the pull-up circuit 7 not to operate. And the pull-up circuit 7 is respectively connected with the pull-up node N2, the first power supply voltage end VGH, the pull-up control circuit 6 and the negative voltage output end P-output, and is used for outputting a high-level signal output by the first power supply voltage end VGH to the negative voltage output end P-output under the control of the pull-up node N2.

Alternatively, as shown in fig. 3, the input circuit 4 includes a sixth transistor T1; the output circuit 5 includes a seventh transistor T5, an eighth transistor T8, and a first capacitor C1. The control terminal of the sixth transistor T1 is connected to the first clock signal terminal CK, the first pole is connected to the frame start signal input terminal STV, and the second pole is connected to the pull-down node N1. A control terminal of the seventh transistor T5 is connected to the second pole of the eighth transistor T8 and one end of the first capacitor C1, respectively, a first pole thereof is connected to the negative voltage output terminal P-output and the pull-up circuit 7, respectively, and a second pole thereof is connected to the signal input terminal CB. The control terminal of the eighth transistor T8 is connected to the second power voltage terminal VGL, the first pole is connected to the pull-down node N1, and the second pole is connected to the control terminal of the seventh transistor T5. The other end of the first capacitor C1 is connected to the negative voltage output terminal P-output.

Optionally, with continued reference to fig. 3, the pull-up control circuit 6 comprises: a ninth transistor T2, a tenth transistor T3, and an eleventh transistor T7. The ninth transistor T2 has a control terminal connected to the pull-down node N1, a first terminal connected to the second terminal of the tenth transistor T3 and the pull-up node N2, respectively, and a second terminal connected to the first clock signal terminal CK. The tenth transistor T3 has a control terminal connected to the first clock signal terminal CK, a first pole connected to the second power voltage terminal VGL, and a second pole connected to the pull-up node N2. A control terminal of the eleventh transistor T7 is connected to the signal input terminal CB, a first pole thereof is connected to the pull-up circuit 7, and a second pole thereof is connected to the pull-down node N1.

Optionally, with continued reference to fig. 3, the pull-up circuit 7 comprises: a twelfth transistor T4, a thirteenth transistor T6, and a second capacitor C2. A control terminal of the twelfth transistor T4 is connected to the pull-up node N2 and one end of the second capacitor C2, respectively, a first electrode thereof is connected to the first power voltage terminal VGH, and a second electrode thereof is connected to the negative voltage output terminal P-output. The thirteenth transistor T6 has a control terminal connected to the pull-up node N2, a first pole connected to the first power voltage terminal VGH, and a second pole connected to the pull-up control circuit 6. The other end of the second capacitor C2 is connected to the first power voltage terminal VGH.

The following describes in detail the specific working process of the GOA unit according to the embodiment of the present application with reference to fig. 4 to 8:

the transistors used in the embodiments of the present application may be thin film transistors, field effect transistors, or other devices with the same characteristics, all the transistors in the embodiments of the present application are illustrated by taking P-type transistors as an example, and certainly, during actual design, some transistors may also be designed as N-type transistors, or all transistors may be designed as N-type transistors, which is not limited in the embodiments of the present application.

The GOA unit of the embodiment of the present application includes four different working phases, as shown in fig. 4, in the drawing, INPUT is a timing sequence INPUT to the start signal INPUT STV of a frame, CK is a timing sequence INPUT to the first clock signal terminal CK, CB is a timing sequence INPUT to the signal INPUT terminal, CK1 is a timing sequence INPUT to the second clock signal terminal CK1, Poutput is a waveform output by the negative voltage output terminal P-output, and Noutput is a waveform output by the positive voltage output terminal N-output.

As shown in fig. 4 and 5, in the first phase P1, since the first clock signal terminal CK outputs a low level signal, the signal input terminal outputs a high level signal, and the frame start signal input terminal STV outputs a low level signal in the front-end GOA unit, at this time, the sixth transistor T1, the ninth transistor T2, the tenth transistor T3, the twelfth transistor T4, the seventh transistor T5, the thirteenth transistor T6, and the eighth transistor T8 are all in an on state, only the eleventh transistor T7 is in an off state, and at this time, the negative voltage output terminal P-output outputs a high level signal. In the inverter circuit 3, since the second clock signal terminal CK1 outputs a high level signal and the negative voltage output terminal P-output outputs a high level signal, the third transistor T9, the fourth transistor T11 and the fifth transistor T12 are all in an off state, the first transistor T10 and the second transistor T13 are in an on state, and the positive voltage output terminal N-output outputs a low level signal. The negative voltage output end P-output outputs a high level signal, the positive voltage output end N-output outputs a low level signal, and the low-temperature polycrystalline silicon oxide display screen is in a non-display working state.

As shown in fig. 4 and 6, in the second stage P2, since the first clock signal terminal CK outputs a high level signal and the signal input terminal outputs a low level signal, the ninth transistor T2, the seventh transistor T5, the eleventh transistor T7 and the eighth transistor T8 are all turned on, the sixth transistor T1, the tenth transistor T3, the twelfth transistor T4 and the thirteenth transistor T6 are turned off, and the negative voltage output terminal P-output outputs a low level signal. In the inverter circuit 3, since the second clock signal terminal CK1 outputs a high level signal and the negative voltage output terminal P-output outputs a low level signal, the third transistor T9 and the fourth transistor T11 are all in an on state, the first transistor T10, the second transistor T13 and the fifth transistor T12 are all in an off state, and the positive voltage output terminal N-output outputs a high level signal. The negative voltage output end P-output outputs a low level signal, the positive voltage output end N-output outputs a high level signal, and the low-temperature polycrystalline silicon oxide display screen is in a display working state.

As shown in fig. 4 and 7, in the front-end GOA unit, since the first clock signal terminal CK outputs a low level signal and the signal input terminal outputs a high level signal in the third stage P3, the sixth transistor T1, the tenth transistor T3, the twelfth transistor T4, the thirteenth transistor T6 and the eighth transistor T8 are all turned on, the ninth transistor T2, the seventh transistor T5 and the eleventh transistor T7 are turned off, and the negative voltage output terminal P-output outputs a high level signal in the third stage P3. In the inverter circuit 3, since the second clock signal terminal CK1 outputs a low level signal and the negative voltage output terminal P-output outputs a high level signal, the first transistor T10, the second transistor T13 and the fifth transistor T12 are all in an on state, the third transistor T9 and the fourth transistor T11 are all in an off state, and the positive voltage output terminal N-output outputs a low level signal. In the third stage P3, the second transistor T13 can feed back the waveform of the low-level signal outputted from the positive voltage output terminal N-output to the gate of the first transistor T10 at a faster speed, so that the first transistor T10 can quickly turn on the response, so that the falling edge of the output waveform of the positive voltage output terminal N-output is more ideal, and the shoulder of the output waveform of the positive voltage output terminal N-output is reduced.

As shown in fig. 4 and 8, in the fourth stage P4, in the front-end GOA unit, since the first clock signal terminal CK outputs a high level signal and the signal input terminal outputs a low level signal, the twelfth transistor T4, the thirteenth transistor T6, the eleventh transistor T7 and the eighth transistor T8 are all in an on state, the sixth transistor T1, the tenth transistor T3, the ninth transistor T2 and the seventh transistor T5 are all in an off state, and the negative voltage output terminal P-output outputs a high level signal. In the inverter circuit 3, since the second clock signal terminal CK1 outputs a high level signal and the negative voltage output terminal P-output outputs a high level signal, the first transistor T10 and the second transistor T13 are both in an on state, the third transistor T9, the fifth transistor T12 and the fourth transistor T11 are all in an off state, and the positive voltage output terminal N-output outputs a low level signal. The negative voltage output end P-output outputs a high level signal, the positive voltage output end N-output outputs a low level signal, and the low-temperature polycrystalline silicon oxide display screen is in a non-display working state.

Based on the same inventive concept, in a second aspect, an embodiment of the present application discloses a GOA driving circuit, including N cascaded GOA units 1, where each GOA unit 1 is the GOA unit 1 of the first aspect, where N is an integer greater than or equal to 2, and a specific cascading manner of each GOA unit 1 is similar to the prior art, and is not described herein again since it does not relate to a point of improvement of the present application.

Since the GOA driving circuit of the second aspect includes the GOA unit of the first aspect, the GOA driving circuit of the second aspect has the same beneficial effects as the GOA unit of the first aspect. Therefore, the beneficial effects of the GOA driving circuit of the second aspect are not repeated.

Based on the same inventive concept, in a third aspect, embodiments of the present application disclose a display device comprising the GOA driving circuit of the second aspect. Since the display device of the third aspect includes the GOA driving circuit of the second aspect, the display device of the third aspect has the same beneficial effects as the GOA driving circuit of the second aspect. Therefore, the advantageous effects of the display device of the third aspect are not repeated.

Based on the same inventive concept, in a fourth aspect, the embodiments of the present application disclose a driving method of the GOA unit 1, which is used for the GOA unit 1 of the first aspect. As shown in fig. 9, the driving method includes:

s101: and receiving output signals of the signal input end CB and the first clock signal end CK, and driving the negative voltage output end P-output to output a low level signal.

S102: and receiving output signals of the negative voltage output end P-output and the second clock signal end CK1, and driving the positive voltage output end N-output to output a high-level signal.

In the driving method of the embodiment of the application, the GOA unit can receive output signals of the signal input terminal CB and the first clock signal terminal CK, and drive the negative voltage output terminal P-output to output a low level signal; and receiving the output signals of the negative voltage output end P-output and the second clock signal end CK1, and driving the positive voltage output end N-output to output a high level signal, so that the GOA unit can simultaneously output negative voltage pulses and positive voltage pulses, and the GOA unit can be used for driving a low-temperature polycrystalline silicon oxide display screen.

The specific driving operation process of the GOA unit in the embodiment of the present application has already been described in the section of the above GOA unit, and is not described herein again.

The beneficial effects obtained by applying the embodiment of the application comprise:

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A GOA unit, comprising:

2. The GOA cell of claim 1, wherein the inverter circuit comprises an output control circuit, a first transistor and a second transistor;

3. The GOA unit according to claim 2, wherein the output control circuit comprises a third transistor, a fourth transistor and a fifth transistor;

4. The GOA unit of claim 1, wherein the front-end GOA unit comprises an input circuit, an output circuit, a pull-up control circuit and a pull-up circuit;

5. The GOA unit of claim 4, wherein the input circuit comprises a sixth transistor; the output circuit comprises a seventh transistor, an eighth transistor and a first capacitor;

6. The GOA unit of claim 4, wherein the pull-up control circuit comprises: a ninth transistor, a tenth transistor, and an eleventh transistor;

7. The GOA cell of claim 4, wherein the pull-up circuit comprises: a twelfth transistor, a thirteenth transistor, and a second capacitor;

8. GOA driving circuit comprising a cascade of N GOA units, wherein each GOA unit is a GOA unit according to any one of claims 1-7, wherein N is an integer equal to or greater than 2.

9. A display device comprising the GOA driver circuit of claim 8.

10. A driving method for a GOA unit, for a GOA unit according to any one of claims 1 to 7, comprising: