CN111736763A - Storage data reading control method and device - Google Patents
Storage data reading control method and device Download PDFInfo
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- CN111736763A CN111736763A CN202010446718.9A CN202010446718A CN111736763A CN 111736763 A CN111736763 A CN 111736763A CN 202010446718 A CN202010446718 A CN 202010446718A CN 111736763 A CN111736763 A CN 111736763A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention provides a stored data reading control method and a stored data reading control device, wherein the device comprises an external memory, a storage controller, a memory and a processing unit; the storage controller comprises a hash engine and a cache module, wherein the cache module comprises a data cache module and a hash value cache module; the external memory is connected with the memory through a memory controller. According to the method and the device, the hash engine is arranged in the storage controller, the hash value is directly calculated through the hash engine, the data do not need to be moved to another calculation unit (such as a CPU and an independent hardware acceleration unit) to generate the firmware hash value, and data bandwidth consumption caused by extra data movement is effectively reduced.
Description
Technical Field
The present invention relates to the field of SOC, and in particular, to a method and an apparatus for controlling reading of stored data.
Background
In SOC-based embedded systems, it is often necessary to perform integrity checks on externally stored files, including but not limited to: in the system starting process, integrity verification is carried out on the firmware in each stage, such as common safe starting (which is based on the integrity verification and carries out validity verification), integrity verification is carried out on key system files in the system using process, integrity and validity verification are carried out on copyright audio and video files during multimedia playing, and the like.
In a general SOC design, an independent memory controller reads and writes data from and to different peripherals, and an independent encryption and decryption engine calculates hash values, RSA, and the like. A typical firmware integrity check flow includes the following steps: 1. reading the firmware of the next stage and the hash value corresponding to the firmware from the external storage equipment to an internal RAM; 2. calculating the hash value of the specified mode of the firmware in the RAM by using CPU software operation or calling a special hardware acceleration engine; 3. and (3) comparing the hash value obtained by calculation in the step (2) with the hash value obtained by direct reading, and if the hash value is equal, indicating that the firmware is legal.
As shown in fig. 1, the external storage is a firmware read and verify flow exemplified by eMMC. For the device supporting the safe start, the signature of the firmware and the public key for the signature are stored externally, then the public key is used for decrypting the signature of the firmware by using CPU software operation or calling a special hardware acceleration engine, a hash value is obtained and then comparison is carried out. In an embedded system, performance requirements such as starting time and the like are often high, hardware resource capacity which can be provided is limited, the performance requirements are high and the resource capacity is insufficient, and the three steps in a typical firmware integrity verification process are executed in series, and speed acceleration is only realized by improving the performance of a CPU or a hardware acceleration engine.
Disclosure of Invention
Therefore, it is necessary to provide a technical solution for reading and controlling stored data, so as to reduce the data bandwidth consumption caused by data movement in the process of reading and controlling stored data
To achieve the above object, in a first aspect, the inventors provide a stored data reading control apparatus, which includes an external memory, a storage controller, a memory, and a processing unit; the storage controller comprises a hash engine and a cache module, wherein the cache module comprises a data cache module and a hash value cache module; the external memory is connected with the memory through a memory controller;
the processing unit is used for reading the storage data in the external storage into the data cache module of the storage controller, and then writing the external storage data in the data cache module into the memory;
when the hash engine is enabled every time, taking all read data streams as input, calculating to obtain a new first hash value by taking the data of the current hash value cache module as an initial value according to a preset hash algorithm, and updating the new first hash value into the hash cache module; the processing unit is further configured to, after all the stored data in the external memory are completely read, obtain a first hash value from the hash value cache module and read a second hash value from the external memory, and determine whether the read first hash value and the read second hash value are consistent, if so, the check is passed, and otherwise, the check fails.
As an optional embodiment, the processing unit is further configured to clear the hash value caching module, read the stored data from the external memory to the data caching module, and write the stored data in the data caching module into the memory.
As an alternative embodiment, when the storage data is read into the data cache module each time, it is determined whether hash value calculation needs to be performed on the storage data in the current data cache module, and if yes, the hash engine performs step S1: and calculating a first hash value according to the stored data in the current data cache module, otherwise, the hash engine does not execute the step S1.
As an optional embodiment, the processing unit is further configured to set a hash engine enable flag after the hash value caching module is cleared; and after all the stored data in the external memory are read, the hash engine enabling mark is clear.
As an alternative embodiment, the hash engine calculates the first hash value by using a hash algorithm, where the hash algorithm includes any one of SHA1, SHA3, SHA256, SHA384, SHA512, MACTripleDES, MD5, and RIPEMD 160.
As an alternative embodiment, the storage controller includes any one of an MMC controller, an SPI controller, a NAND controller, a SATA controller, a PCI controller, a USB controller, and a UFS controller.
In a second aspect, the inventor further provides a stored data reading control method, which is applied to the stored data reading control device as described above, and comprises the following steps:
reading the storage data in the external storage into a cache module of a storage controller, and then writing the storage data in the cache module into a memory;
when the hash engine is enabled, taking all read data streams as input, calculating to obtain a new first hash value by taking the data of the current hash value cache module as an initial value according to a preset hash algorithm, and updating the new first hash value into the hash cache module; and reading the second hash value from the external memory, and judging whether the finally obtained first hash value and the second hash value are consistent, if so, the verification is passed, and otherwise, the verification fails.
As an alternative embodiment, the method comprises the steps of:
clearing data in the hash value cache module, and setting a hash engine enabling mark;
reading storage data with a certain size from an external memory to a data cache module each time;
after each reading, judging whether all the stored data in the current external memory are completely read, if so, reading a first hash value finally obtained from the hash value cache module, and clearing a hash engine enabling mark; and if not, continuously reading next storage data from the external memory, taking all read data streams as input, calculating by taking the hash value cache region data as an initial value according to a specified algorithm to obtain a new hash value, and outputting the new hash value to the hash value cache region.
Different from the prior art, the stored data reading control method and the stored data reading control device comprise an external memory, a storage controller, a memory and a processing unit; the storage controller comprises a hash engine and a cache module, wherein the cache module comprises a data cache module and a hash value cache module; the external memory is connected with the memory through a memory controller. According to the method and the device, the hash engine is arranged in the storage controller, the hash value is directly calculated through the hash engine, the data do not need to be moved to another calculation unit (such as a CPU and an independent hardware acceleration unit) to generate the firmware hash value, and data bandwidth consumption caused by extra data movement is effectively reduced.
Drawings
Fig. 1 is a flowchart of a storage data read control method according to the prior art;
FIG. 2 is a flowchart illustrating a method for controlling reading of stored data according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for controlling reading of stored data according to another embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for controlling reading of stored data according to another embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method for controlling reading of stored data according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of a stored data read control device according to an embodiment of the present invention.
Reference numerals:
1. an external memory;
2. a storage controller;
21. a hash engine;
22. a cache module; 221. a data caching module; 222. and a hash value caching module.
3. A memory;
4. and a processing unit.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 5, the present invention provides a stored data reading control device, which includes an external memory 1, a storage controller 2, a memory 3 and a processing unit 4; the storage controller 2 comprises a hash engine 21 and a cache module 22, and the cache module 22 comprises a data cache module 221 and a hash value cache module 222; the external memory 1 is connected with the memory 3 through a memory controller 2;
the processing unit 4 is configured to first read the storage data in the external storage 1 into the data cache module 221 of the storage controller 2, and then write the external storage data in the data cache module 221 into the memory 3; the processing unit is a CPU or an independent hardware acceleration unit.
When the hash engine is enabled each time, the storage controller 2 takes all the read data streams as input, calculates a new first hash value with the data of the current hash value cache module 222 as an initial value according to a preset hash algorithm, and updates the new first hash value into the hash cache module 222.
The processing unit 4 is further configured to, after all the stored data in the external memory 1 are completely read, obtain a first hash value from the hash value caching module 222 and read a second hash value from the external memory 1, and determine whether the read first hash value and the read second hash value are consistent, if yes, the check is passed, and if not, the check fails. The processing unit is an element with a data read-write control function, such as a CPU, or an independent circuit with a hardware acceleration function.
The first hash value is obtained by real-time calculation according to the read data, the second hash value is a check value, and the integrity of the read data can be checked by comparing the first hash value with the second hash value. The hash engine is arranged in the storage controller and directly utilizes the stored data in the current data cache module and the hash value in the hash value cache module to calculate and generate a new hash value, so that the stored data does not need to be moved to another computing unit (a CPU is used for soft solution, and an independent hardware acceleration unit is used for hardware) to generate a first hash value, and the data bandwidth consumption caused by extra data movement is effectively reduced.
In some embodiments, the processing unit is further configured to clear the hash value cache module, read the stored data from the external memory to the data cache module, and write the stored data in the data cache module into the memory. Therefore, the hash value stored by the hash value caching module before each data reading can be ensured to be empty, the influence of the last cached hash value can be avoided, and the integrity and the accuracy of the verification can be improved.
In some embodiments, each time the storage data is read into the data cache module, it is determined whether hash calculation needs to be performed on the storage data in the current data cache module, and if yes, the hash engine performs step S1: and calculating a first hash value according to the stored data in the current data cache module, otherwise, the hash engine does not execute the step S1. In short, when the integrity check of the read data is required, the hash engine performs step S1, otherwise, does not perform step S1, so that the requirement of more application scenarios can be met.
In some embodiments, the processing unit is further configured to set a hash engine enable flag after the hash value caching module is cleared; and after all the stored data in the external memory are read, clearing the hash engine enabling mark. In short, by setting the hash engine enable flag, whether the current hash engine is in operation can be effectively known, and after all the stored data in the external memory are completely read, the hash engine enable flag is cleared to stop the operation of the hash engine, so that the purpose of saving power consumption is achieved.
In some embodiments, the hash engine computes the first hash value using a hash algorithm comprising any one of SHA1, SHA3, SHA256, SHA384, SHA512, MACTripleDES, MD5, RIPEMD 160.
In certain embodiments, the storage controller comprises any one of an MMC controller, an SPI controller, a NAND controller, a SATA controller, a PCI controller, a USB controller, and a UFS controller.
As shown in fig. 5, the present invention further provides a stored data reading control method, which is applied to the stored data reading control device as described above, and the method includes the following steps:
firstly, step S501 is entered to read the storage data in the external storage to the cache module of the storage controller, and then the storage data in the cache module is written into the memory;
then, when the hash engine is enabled in step S502, taking all read data streams as input, calculating to obtain a new first hash value according to a preset hash algorithm by taking the data of the current hash value cache module as an initial value, and updating the new first hash value into the hash cache module;
and then, step S503 is executed to read the second hash value from the external memory, and determine whether the finally obtained first hash value and the second hash value are consistent, if yes, the verification is passed, otherwise, the verification fails.
The hash engine is arranged in the storage controller and directly utilizes the stored data in the current data cache module and the hash value in the hash value cache module to calculate and generate a new hash value, so that the stored data does not need to be moved to another computing unit (a CPU is used for soft solution, and an independent hardware acceleration unit is used for hardware) to generate a first hash value, and the data bandwidth consumption caused by extra data movement is effectively reduced.
In certain embodiments, the method comprises the steps of: clearing data in the hash value cache module, and setting a hash engine enabling mark; reading storage data with a certain size from an external memory to a data cache module each time; after each reading, judging whether all the stored data in the current external memory are completely read, if so, reading a first hash value finally obtained from the hash value cache module, and clearing a hash engine enabling mark; and if not, continuously reading next storage data from the external memory, taking all read data streams as input, calculating by taking the hash value cache region data as an initial value according to a specified algorithm to obtain a new hash value, and outputting the new hash value to the hash value cache region. Therefore, the hash value stored by the hash value caching module before each data reading can be ensured to be empty, the influence of the last cached hash value can be avoided, and the integrity and the accuracy of the verification can be improved.
As shown in fig. 2, 3, and 4, the description will be made of firmware reading and verification performed by an eMMC controller with a hash engine (i.e., the aforementioned "memory controller") by taking an example in which the external memory cell is an eMMC.
One of the difficulties in implementing this scheme is whether the hash engine embedded in the storage controller can flexibly support hash calculation of data of any size, since the size of the file or firmware data to be checked may be from several KB to several GB or even larger. The hash algorithm used for data integrity check is a progressive algorithm, that is, it is not necessary to prepare all data at one time to obtain the result, but it can be used to perform operation accumulation on newly added data of any size based on the existing result to obtain the final result. Therefore, a hash engine, a hash calculation enable bit, and a hash buffer space may be added to the eMMC controller for circuit implementation.
As shown in fig. 3, the controller reading flow is illustrated by taking an eMMC controller with a hash engine as an example, since the FIFO of the eMMC controller is generally not large (e.g., 1KB in some SOC chips), and one MMC command may read data of several tens of MB, the data reading progress between the eMMC controller and an external eMMC device is controlled by a hardware handshake signal, and the hash engine may perform an accumulation calculation on each piece of data entering the FIFO.
Taking fig. 4 as an example, if a size of a firmware datum (assuming that the read storage datum is "firmware datum") is 512MB, the maximum data amount of the underlying eMMC read driver for a single time supporting reading is 32MB, and the system needs to call the eMMC read interface driver 16 times to complete the firmware reading. And after all the firmware data are read, reading the firmware hash data from the hash cache and clearing the hash engine enabling mark.
The invention provides a stored data reading control method and a stored data reading control device, wherein the device comprises an external memory, a storage controller, a memory and a processing unit; the storage controller comprises a hash engine and a cache module, wherein the cache module comprises a data cache module and a hash value cache module; the external memory is connected with the memory through a memory controller. According to the method and the device, the hash engine is arranged in the storage controller, the hash value is directly calculated through the hash engine, the data do not need to be moved to another calculation unit (such as a CPU and an independent hardware acceleration unit) to generate the firmware hash value, and data bandwidth consumption caused by extra data movement is effectively reduced.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (8)
1. A stored data reading control device is characterized by comprising an external memory, a storage controller, a memory and a processing unit; the storage controller comprises a hash engine and a cache module, wherein the cache module comprises a data cache module and a hash value cache module; the external memory is connected with the memory through a memory controller;
the processing unit is used for reading the storage data in the external storage into the data cache module of the storage controller, and then writing the external storage data in the data cache module into the memory;
when the hash engine is enabled every time, taking all read data streams as input, calculating to obtain a new first hash value by taking the data of the current hash value cache module as an initial value according to a preset hash algorithm, and updating the new first hash value into the hash cache module;
the processing unit is further configured to, after all the stored data in the external memory are completely read, obtain a first hash value from the hash value cache module and read a second hash value from the external memory, and determine whether the read first hash value and the read second hash value are consistent, if so, the check is passed, and otherwise, the check fails.
2. The stored data reading control device according to claim 1, wherein the processing unit is further configured to clear the hash value cache module, read the stored data from the external memory to the data cache module, and write the stored data in the data cache module into the memory.
3. The stored data reading control device according to claim 2, wherein each time the stored data is read into the data cache module, it is determined whether hash value calculation is required for the stored data in the current data cache module, and if so, the hash engine performs step S1: and calculating a first hash value according to the stored data in the current data cache module, otherwise, the hash engine does not execute the step S1.
4. The stored data reading control apparatus of claim 2, wherein the processing unit is further configured to set a hash engine enable flag after the hash value caching module is cleared; and after all the stored data in the external memory are read, the hash engine enabling mark is clear.
5. A stored data read control apparatus as claimed in claim 1 wherein the hash engine calculates the first hash value using a hash algorithm comprising any one of SHA1, SHA3, SHA256, SHA384, SHA512, MACTripleDES, MD5, ripemmd 160.
6. A stored data read control apparatus as claimed in claim 1, wherein said storage controller comprises any one of MMC controller, SPI controller, NAND controller, SATA controller, PCI controller, USB controller, UFS controller.
7. A stored data reading control method applied to the stored data reading control apparatus according to any one of claims 1 to 6, the method comprising the steps of:
reading the storage data in the external storage into a cache module of a storage controller, and then writing the storage data in the cache module into a memory;
when the hash engine is enabled, taking all read data streams as input, calculating to obtain a new first hash value by taking the data of the current hash value cache module as an initial value according to a preset hash algorithm, and updating the new first hash value into the hash cache module;
and reading the second hash value from the external memory, and judging whether the finally obtained first hash value and the second hash value are consistent, if so, the verification is passed, and otherwise, the verification fails.
8. The stored data read control method of claim 7, wherein the method comprises the steps of:
clearing data in the hash value cache module, and setting a hash engine enabling mark;
reading storage data with a certain size from an external memory to a data cache module each time;
after each reading, judging whether all the stored data in the current external memory are completely read, if so, reading a first hash value finally obtained from the hash value cache module, and clearing a hash engine enabling mark; and if not, continuously reading next storage data from the external memory, taking all read data streams as input, calculating by taking the hash value cache region data as an initial value according to a specified algorithm to obtain a new hash value, and outputting the new hash value to the hash value cache region.
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Address after: 350003 building 18, No.89, software Avenue, Gulou District, Fuzhou City, Fujian Province Applicant after: Ruixin Microelectronics Co.,Ltd. Address before: 350003 building 18, No.89, software Avenue, Gulou District, Fuzhou City, Fujian Province Applicant before: FUZHOU ROCKCHIP ELECTRONICS Co.,Ltd. |
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