CN111736654B - Clock model implementation method and device, computer equipment and storage medium - Google Patents
Clock model implementation method and device, computer equipment and storage medium Download PDFInfo
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Abstract
The invention relates to a clock model realization method, a device, computer equipment and a storage medium, wherein the method comprises the steps of setting a clock generation component for generating a clock; obtaining a test case; generating a clock generation mode according to the test case, adding the clock generation mode into a clock generation component, and generating a corresponding clock by the clock generation component; and transmitting the clock to the top layer of the verification environment in an interface mode, and performing clock verification by adopting the clock and the module to be verified. According to the invention, the clock generation component is independent from the verification environment top layer, the corresponding clock generation mode is generated according to the test case, the clock generation component calls the clock generation mode by adopting a callback mechanism and generates the corresponding clock, and then the clock generation mode is transmitted to the verification environment top layer by utilizing the interface to perform clock verification of the module to be verified, so that the verification environment top layer code maintenance is simplified, the clock scene is controllable, the clock scene is more flexible, and the maintenance is clearer.
Description
Technical Field
The present invention relates to a clock generation method, and more particularly, to a clock model implementation method, apparatus, computer device, and storage medium.
Background
In the module-level verification process of the chip, a clock signal is usually generated by a verification environment, and a real PLL (Phase Locked Loop) is not used, so that the configuration process of the PLL can be omitted; and secondly, because the module-level verification only concerns about the functional correctness of the module, and does not concern whether the system-level PLL can work normally. In general, module level verification environments implement clock generation functions on top of the verification environment, and are often generated by using procedural statement initial and always syntax of verilog or system verilog. The clock generated by the method is poor in flexibility, and is difficult to directly meet the requirements of various scenes with different clock frequencies; in addition, as the number of clock scenes is large, all the scenes are maintained in one file, so that the using scenes are not clear.
Taking the verification of a certain module as an example, the module is provided with a plurality of clocks which are all in an asynchronous relation, the clock frequencies are completely independent, and in order to verify the signal interaction logic among the clock frequencies, the frequencies of the clocks need to be completely randomly combined; for example, in some test scenarios, a certain clock frequency needs to be fixed, while another clock needs to be random, or two clock frequencies need to be fixed, and the like; and for example, analog clock jitter, uncertain duty ratio and the like are needed. The types of clocks are various, if each scene is written into the top layer of the verification environment, the needed clock scene is selected in a macro mode, all possible scenes need to be prepared in the top layer of the verification environment for selection, and maintenance is inconvenient. More importantly, if the clock needs to dynamically change according to the test case, the modification by transferring variables to the top layer of the verification environment through the test case is not flexible, and it is difficult to completely simulate the clock state desired by the test case.
Referring to FIG. 1, a conventional Verification scheme is shown, in which the entire platform is referred to as ENV and includes three parts, namely TB _ TOP, UVM (Universal Verification Methodology) component and test case, wherein the TB _ TOP includes clk _ gen and DUT, the DUT is the module to be tested, and the clk _ gen is a clock generation part for generating various types of required clocks. In a conventional verification diagram, when different test cases need different clock scenarios, the addition and modification can only be performed in clk _ gen, the clock scenarios can be generally distinguished in a macro manner, and different macros are opened by different test cases. In this way, clk _ gen is complicated along with the increase of clock scenes, and the clock scenes needing to be maintained are not clear enough; in addition, because the test case and the clk _ gen are completely independent, if a clock scene which dynamically changes along with the test case needs to be realized, signal transmission is needed, and the clock scene can be realized only by adopting methods such as handshaking and the like between the test case and the clk _ gen, so that the method is troublesome and not flexible enough.
Therefore, it is necessary to design a new method, which simplifies the maintenance of top-level codes in the verification environment, and is controllable, more flexible and clearer in maintenance of clock scenes.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a clock model implementation method, a clock model implementation device, computer equipment and a storage medium.
In order to achieve the purpose, the invention adopts the following technical scheme: the clock model implementation method comprises the following steps:
setting a clock generation component for generating a clock;
obtaining a test case;
generating a clock generation mode according to the test case, adding the clock generation mode into a clock generation component, and generating a corresponding clock by the clock generation component;
and transmitting the clock to a top layer of a verification environment in an interface mode, and performing clock verification by adopting the clock and a module to be verified.
The further technical scheme is as follows: the clock generation assembly is written in a class mode and uses a callback mechanism to build a clock model of the main body part.
The further technical scheme is as follows: the clock generation component is independent of the verification environment top level.
The further technical scheme is as follows: the generating a clock generating mode according to the test case and adding the clock generating mode into a clock generating component to generate a corresponding clock by the clock generating component comprises the following steps:
and generating a specific type of clock generation mode according to the test case, adding the specific type of clock generation mode into the clock generation component by adopting a callback mechanism, and generating a specific clock by the clock generation component according to the clock generation mode.
The further technical scheme is as follows: the transmitting the clock to a verification environment top layer through an interface mode, and after the clock and the module to be verified are adopted for clock verification, the method further comprises the following steps:
judging whether the clock scene needs to be modified or not;
and if the clock scene needs to be modified, modifying the test case, executing the clock generation mode generated according to the test case, and adding the clock generation mode into the clock generation component so as to generate a corresponding clock by the clock generation component.
The further technical scheme is as follows: after the determining whether the clock scene needs to be modified, the method further includes:
and if the clock scene does not need to be modified, entering an end step.
The further technical scheme is as follows: the clock generation assembly is arranged in the UVM assembly.
The invention also provides a clock model implementation device, which comprises:
a component setting unit for setting a clock generation component for generating a clock;
the case acquisition unit is used for acquiring a test case;
the clock generation unit is used for generating a clock generation mode according to the test case, adding the clock generation mode into the clock generation assembly and generating a corresponding clock by the clock generation assembly;
and the verification unit is used for transmitting the clock to a top layer of a verification environment in an interface mode and verifying the clock by adopting the clock and the module to be verified.
The invention also provides computer equipment which comprises a memory and a processor, wherein the memory is stored with a computer program, and the processor realizes the method when executing the computer program.
The invention also provides a storage medium storing a computer program which, when executed by a processor, is operable to carry out the method as described above.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the clock generation component is independent from the verification environment top layer, the corresponding clock generation mode is generated according to the test case, the clock generation component calls the clock generation mode by adopting a callback mechanism and generates the corresponding clock, and then the clock generation mode is transmitted to the verification environment top layer by utilizing the interface to perform clock verification of the module to be verified, so that the verification environment top layer code maintenance is simplified, the clock scene is controllable, the clock scene is more flexible, and the maintenance is clearer.
The invention is further described below with reference to the accompanying drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of prior art authentication;
fig. 2 is a schematic flowchart of a clock model implementation method according to an embodiment of the present invention;
fig. 3 is a schematic verification diagram of a clock model implementation method according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of a clock model implementation method according to another embodiment of the present invention;
FIG. 5 is a schematic block diagram of a clock model implementation apparatus provided in an embodiment of the present invention;
FIG. 6 is a schematic block diagram of a clock model implementation apparatus according to another embodiment of the present invention;
FIG. 7 is a schematic block diagram of a computer device provided by an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Referring to fig. 2, fig. 2 is a schematic flow chart of a clock model implementation method according to an embodiment of the present invention. The clock model implementation method is applied to a controller with a chip.
Fig. 2 is a schematic flowchart of a clock model implementation method according to an embodiment of the present invention. As shown in fig. 2, the method includes the following steps S110 to S140.
And S110, setting a clock generation component for generating the clock.
In this embodiment, the clock generation component is a clock for generating different verification scenarios, and generates a clock according to a clock generation method input by the test case when generating the clock.
Specifically, the clock generation component is a clock model which is written in a class mode and uses a callback mechanism to build a main body part.
In particular, the clock generation component is independent of the verification environment top level.
Clock generation is separated from the top layer of the verification environment to form a clock model, a clock is generated by the clock model and then introduced to the top layer of the verification environment, and all clock scenes are realized in the clock model. In this way, code maintenance of complex clocks at the top level of the verification environment is freed. And all clock scenes cannot be compiled in the clock model, and the test cases can be freely compiled according to requirements and then added into the clock model for implementation. In order to reduce the maintenance of the code, the clock model structure is required not to change along with the requirement of the test case on the clock scene. Once the clock model is fixed, no further code needs to be added. All clocks are directly related to the test cases, the clock scenes are directly compiled by the test cases instead of being compiled by the top layer of the verification environment, so that the clock scenes are controllable and more flexible, and the clocks are more clearly maintained.
And S120, obtaining a test case.
In this embodiment, the test case refers to an example input by a person in charge in real time according to actual conditions.
And S130, generating a clock generation mode according to the test case, and adding the clock generation mode into a clock generation component to generate a corresponding clock by the clock generation component.
In this embodiment, the clock generation method refers to a clock generation method corresponding to a clock generation scenario.
Specifically, a specific type of clock generation mode is generated according to the test case, and a callback mechanism is added to the clock generation component, so that the clock generation component generates a specific clock according to the clock generation mode.
And S140, transmitting the clock to a top layer of a verification environment in an interface mode, and performing clock verification by adopting the clock and a module to be verified.
In this embodiment, the clock generation component is independent from the top layer of the verification environment, the clock generated by the clock generation component is transmitted to the top layer of the verification environment in an interface transmission manner, and the clock is verified after being combined with the model to be verified. The clock generation assembly is arranged on the UVM assembly and is realized by using a UVM verification methodology, and not only can clocks with different frequencies be randomly generated, but also clocks conforming to a scene can be generated according to the requirements of a specific scene; the module to be verified needs to use a clock.
Referring to fig. 3, the interface in the figure indicates that the clock generated by the clock generation component is introduced into the TOP TB _ TOP of the verification environment through an interface for the TOP TB _ TOP of the verification environment to use; the clock generation component is compiled in a class mode, and the main part of the internal clock generation is realized by using a callback mechanism, so that a corresponding clock can be generated in a test case conveniently according to a specific scene; the interior of the test case is also realized by using a callback mechanism, a specific type of clock is generated according to the requirement of the test case, and then the clock generation mode is added into the clock generation component by using the callback. Because the clock generation source comes from a specific test case in a callback mode, and the code of the clock generation component is not required to be modified in different clock scenes, the clock generation component is maintained more clearly. The clock generation is also more flexible, more elaborate and richer since it is generated directly from the specific test case.
Different verification scenes have different requirements on the clock, the clock generation scenes correspond to the test scenes one by one, and the clock is generated and maintained by a specific test case responsible person according to the self requirement, so that the clock is generated more flexibly and is easy to maintain, and all required clock scenes can be generated.
According to the clock model implementation method, the clock generation component is independent of the verification environment top layer, the corresponding clock generation mode is generated according to the test case, the clock generation component calls the clock generation mode by adopting a callback mechanism and generates the corresponding clock, and the clock generation mode is transmitted to the verification environment top layer by utilizing the interface to perform clock verification of the module to be verified, so that the verification environment top layer code maintenance is simplified, the clock scene is controllable, the clock scene is more flexible, and the maintenance is clearer.
Fig. 4 is a flowchart illustrating a clock model implementation method according to another embodiment of the present invention. As shown in fig. 4, the clock model implementation method of the present embodiment includes steps S210 to S260. Steps S210 to S240 are similar to steps S110 to S140 in the above embodiments, and are not described herein again. The added steps S250 to S260 in the present embodiment are explained in detail below.
S250, judging whether a clock scene needs to be modified or not;
s260, if the clock scene needs to be modified, modifying the test case, and executing the step S230;
and if the clock scene does not need to be modified, entering an end step.
The clock generation scenes correspond to the test scenes one by one, and the clock generation is generated and maintained by a responsible person of a specific test case according to the own needs, namely the test case is changed so as to change the clock generation. In order to reduce the maintenance of the code, the clock model structure is required not to change along with the requirement of the test case on the clock scene. Once the clock model is fixed, no further code needs to be added. All clocks are directly related to the test cases, the clock scenes are directly compiled by the test cases instead of being compiled by the top layer of the verification environment, so that the clock scenes are controllable and more flexible, and the clocks are more clearly maintained.
Fig. 5 is a schematic block diagram of a clock model implementation apparatus 300 according to an embodiment of the present invention. As shown in fig. 5, the present invention further provides a clock model implementation apparatus 300 corresponding to the above clock model implementation method. The clock model implementation apparatus 300 includes a unit for performing the clock model implementation method described above, and the apparatus may be configured in a controller. Specifically, referring to fig. 5, the clock model implementation apparatus 300 includes a component setting unit 301, a use case obtaining unit 302, a clock generating unit 303, and a verifying unit 304.
A component setting unit 301 for setting a clock generation component for generating a clock; a case obtaining unit 302, configured to obtain a test case; the clock generating unit 303 is configured to generate a clock generating manner according to the test case, add the clock generating manner to the clock generating component, and generate a corresponding clock by the clock generating component; and the verification unit 304 is configured to transmit the clock to a top layer of a verification environment in an interface manner, and perform clock verification by using the clock and a module to be verified.
Specifically, the clock generating unit 303 is configured to generate a specific type of clock generating manner according to the test case, and add the specific type of clock generating manner to the clock generating component by using a callback mechanism, so that the clock generating component generates a specific clock according to the clock generating manner.
Fig. 6 is a schematic block diagram of a clock model implementation apparatus 300 according to another embodiment of the present invention. As shown in fig. 6, the clock model implementation apparatus 300 of the present embodiment is the above embodiment, and adds a determination unit 305 and a modification unit 306.
A judging unit 305, configured to judge whether a clock scene needs to be modified; and if the clock scene does not need to be modified, entering an end step. And the modifying unit 306 is configured to modify the test case if the clock scenario needs to be modified, execute the clock generating manner according to the test case, and add the test case to the clock generating component so that the clock generating component generates a corresponding clock.
It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation processes of the clock model implementation apparatus 300 and each unit may refer to the corresponding descriptions in the foregoing method embodiments, and for convenience and brevity of description, no further description is provided herein.
The clock model implementation apparatus 300 may be implemented in the form of a computer program that can be run on a computer device as shown in fig. 7.
Referring to fig. 7, fig. 7 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 500 may be a server, wherein the server may be an independent server or a server cluster composed of a plurality of servers.
Referring to fig. 7, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.
The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer programs 5032 comprise program instructions that, when executed, cause the processor 502 to perform a clock model implementation method.
The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.
The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 can be enabled to execute a clock model implementation method.
The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 7 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
Wherein the processor 502 is configured to run the computer program 5032 stored in the memory to implement the following steps:
setting a clock generation component for generating a clock; obtaining a test case; generating a clock generation mode according to the test case, adding the clock generation mode into a clock generation component, and generating a corresponding clock by the clock generation component; and transmitting the clock to a top layer of a verification environment in an interface mode, and performing clock verification by adopting the clock and a module to be verified.
The clock generation assembly is written in a class mode and uses a callback mechanism to build a clock model of the main body part.
The clock generation component is independent of the verification environment top level.
The clock generation assembly is arranged in the UVM assembly.
In an embodiment, when the processor 502 implements the clock generation manner according to the test case, and adds the clock generation manner to the clock generation component, so as to generate a corresponding clock step by the clock generation component, the following steps are specifically implemented:
and generating a specific type of clock generation mode according to the test case, adding the specific type of clock generation mode into the clock generation component by adopting a callback mechanism, and generating a specific clock by the clock generation component according to the clock generation mode.
In an embodiment, after the processor 502 implements the clock transmission to the top layer of the verification environment by the interface method, and performs the clock verification step by using the clock and the module to be verified, the following steps are further implemented:
judging whether the clock scene needs to be modified or not; and if the clock scene needs to be modified, modifying the test case, executing the clock generation mode generated according to the test case, and adding the clock generation mode into the clock generation component so as to generate a corresponding clock by the clock generation component.
In an embodiment, after the step of determining whether the clock scenario needs to be modified is implemented, the processor 502 further implements the following steps:
and if the clock scene does not need to be modified, entering an end step.
It should be understood that in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.
Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program, when executed by a processor, causes the processor to perform the steps of:
setting a clock generation component for generating a clock; obtaining a test case; generating a clock generation mode according to the test case, adding the clock generation mode into a clock generation component, and generating a corresponding clock by the clock generation component; and transmitting the clock to a top layer of a verification environment in an interface mode, and performing clock verification by adopting the clock and a module to be verified.
The clock generation assembly is written in a class mode and uses a callback mechanism to build a clock model of the main body part.
The clock generation component is independent of the verification environment top level.
The clock generation assembly is arranged in the UVM assembly.
In an embodiment, when the processor executes the computer program to implement the clock generation manner according to the test case, and adds the clock generation manner to the clock generation component to generate a corresponding clock by the clock generation component, the following steps are specifically implemented:
and generating a specific type of clock generation mode according to the test case, adding the specific type of clock generation mode into the clock generation component by adopting a callback mechanism, and generating a specific clock by the clock generation component according to the clock generation mode.
In an embodiment, after the processor executes the computer program to realize that the clock is transmitted to the top layer of the verification environment through the interface mode, and the clock and the module to be verified are adopted to perform the clock verification step, the following steps are further realized:
judging whether the clock scene needs to be modified or not; and if the clock scene needs to be modified, modifying the test case, executing the clock generation mode generated according to the test case, and adding the clock generation mode into the clock generation component so as to generate a corresponding clock by the clock generation component.
In an embodiment, after the step of determining whether the clock scene needs to be modified is implemented by the processor executing the computer program, the following steps are further implemented:
and if the clock scene does not need to be modified, entering an end step.
The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. The clock model implementation method is characterized by comprising the following steps:
setting a clock generation component for generating a clock;
obtaining a test case;
generating a clock generation mode according to the test case, adding the clock generation mode into a clock generation component, and generating a corresponding clock by the clock generation component;
transmitting the clock to a top layer of a verification environment in an interface mode, and performing clock verification by adopting the clock and a module to be verified;
the clock generation component is independent of the verification environment top level.
2. The clock model implementation method of claim 1, wherein the clock generation component is a clock model written in a class manner and building a body part using a callback mechanism.
3. The method for implementing a clock model according to claim 1, wherein the generating a clock generation manner according to the test case and adding the generated clock generation manner to a clock generation component to generate a corresponding clock by the clock generation component includes:
and generating a specific type of clock generation mode according to the test case, adding the specific type of clock generation mode into the clock generation component by adopting a callback mechanism, and generating a specific clock by the clock generation component according to the clock generation mode.
4. The clock model implementation method of claim 1, wherein after the clock is transmitted to a top layer of a verification environment by an interface manner and verified by using the clock and a module to be verified, the method further comprises:
judging whether the clock scene needs to be modified or not;
and if the clock scene needs to be modified, modifying the test case, executing the clock generation mode generated according to the test case, and adding the clock generation mode into the clock generation component so as to generate a corresponding clock by the clock generation component.
5. The clock model implementation method of claim 4, wherein after determining whether the clock scenario needs to be modified, the method further comprises:
and if the clock scene does not need to be modified, entering an end step.
6. The clock model implementation method of claim 1, wherein the clock generation component is disposed in a UVM component.
7. The clock model implementation apparatus includes:
a component setting unit for setting a clock generation component for generating a clock;
the case acquisition unit is used for acquiring a test case;
the clock generation unit is used for generating a clock generation mode according to the test case, adding the clock generation mode into the clock generation assembly and generating a corresponding clock by the clock generation assembly;
the verification unit is used for transmitting the clock to a top layer of a verification environment in an interface mode and verifying the clock by adopting the clock and a module to be verified;
the clock generation component is independent of the verification environment top level.
8. A computer device, characterized in that the computer device comprises a memory, on which a computer program is stored, and a processor, which when executing the computer program implements the method according to any of claims 1 to 6.
9. A storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 6.
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