CN111736570A - Controller clock frequency detection method and device, computer equipment and storage medium - Google Patents
Controller clock frequency detection method and device, computer equipment and storage medium Download PDFInfo
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0259—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the response to fault detection
- G05B23/0267—Fault communication, e.g. human machine interface [HMI]
- G05B23/027—Alarm generation, e.g. communication protocol; Forms of alarm
Abstract
The application relates to a method and a device for detecting clock frequency of a controller, computer equipment and a storage medium. The clock frequency detection method of the controller comprises the following steps: acquiring a reference count value; controlling a timing module to perform timing work according to preset time; the control counting module counts fixed period pulses when the timing module performs timing work, and interrupts counting when the timing module completes the timing work, so as to obtain a work count value; calculating the clock drift amount of the controller according to the deviation of the work counting value relative to the reference counting value; and judging whether the clock frequency of the controller is normal or not according to the clock drift amount. The method and the device can enable the clock frequency detection result of the controller to be more accurate.
Description
Technical Field
The present application relates to the field of controller technologies, and in particular, to a method and an apparatus for detecting a clock frequency of a controller, a computer device, and a storage medium.
Background
The controller is a component for instructing each component of the computer to coordinate according to the functional requirements of the instructions, and is a neural center and a command center of the computer. Whether the clock frequency of the controller is normal or not can affect the running safety of the system software program. Therefore, it needs to be detected.
The existing detection method is that a clock chip of an independent time slot is additionally arranged outside a controller, the clock frequency of the external independent clock chip is compared with the clock frequency of the controller, and when the occurrence time difference between the clock frequency and the clock frequency is found, the clock frequency is judged to be wrong.
However, when the method is used, if the frequency of the reference clock chip itself drifts, false alarm or false alarm can occur in detection, and further the detection is inaccurate.
Disclosure of Invention
In view of the above, it is necessary to provide a method and an apparatus for detecting a clock frequency of a controller, a computer device, and a storage medium.
A controller clock frequency detection method, comprising:
acquiring a reference count value, wherein the reference count value is the count of the fixed-period pulse in a preset time by a counting module;
controlling a timing module to perform timing work according to the preset time, wherein the timing frequency of the timing module is obtained by frequency division of the clock frequency of the controller;
controlling the counting module to count the fixed period pulse when the timing module performs the timing work, and interrupting the counting when the timing module completes the timing work, so as to obtain a work count value;
calculating the clock drift amount of the controller according to the deviation of the work count value relative to the reference count value;
and judging whether the clock frequency of the controller is normal or not according to the clock drift amount.
In one embodiment, the obtaining the reference count value includes:
controlling the timing module to perform initial timing according to the preset time, wherein the initial timing is the first timing performed by the timing module when the controller is in an initial state;
and controlling the counting module to count the fixed period pulse when the timing module performs the initial timing, and interrupting the counting when the timing module completes the initial timing, so as to obtain the reference count value.
In one embodiment, the method further comprises the following steps: setting the priority of the interrupt to a highest level.
In one embodiment, after the determining whether the clock frequency of the controller is normal according to the clock drift amount, the method further includes:
if the clock frequency of the controller is abnormal, performing clock frequency fault processing operation;
and if the clock frequency of the controller is normal, executing other functions and continuously detecting whether the clock frequency of the controller is normal.
In one embodiment, the performing the clock frequency failure handling operation includes issuing an alarm message.
In one embodiment, after the determining whether the clock frequency of the controller is normal according to the clock drift amount, the method further includes:
and clearing the count of the counting module.
A controller clock frequency detection apparatus, comprising:
the pulse generating module is used for transmitting fixed-period pulses;
the timing module is used for carrying out timing work according to preset time, and the timing frequency is obtained by frequency division of the clock frequency of the controller;
the counting module is connected with the pulse generating module and used for counting the pulses transmitted by the pulse generating module when the timing module performs the timing work and interrupting the counting when the timing module completes the timing work so as to obtain a work count value;
the acquisition module is used for acquiring a reference count value, wherein the reference count value is the count of the counting module on the fixed-period pulse within the preset time;
the calculation module is used for calculating the clock drift amount of the controller according to the work count value and the reference count value;
and the judging module is used for judging whether the clock frequency of the controller is normal or not according to the clock drift amount.
In one embodiment, the timing module is a timer in the controller and/or the counting module is a counter in the controller.
In one embodiment, the obtaining module includes the timing module and the counting module, and the reference count value is obtained by the counting module counting the fixed period pulses at an initial timing by the timing module according to a preset time, where the initial timing is a first timing performed by the timing module when the controller is in an initial state.
A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor when executing the computer program implements the steps of:
acquiring a reference count value, wherein the reference count value is the count of the fixed-period pulse in a preset time by a counting module;
controlling a timing module to perform timing work according to the preset time, wherein the timing frequency of the timing module is obtained by frequency division of the clock frequency of the controller;
controlling the counting module to count the fixed period pulse when the timing module performs the timing work, and interrupting the counting when the timing module completes the timing work, so as to obtain a work count value;
calculating the clock drift amount of the controller according to the deviation of the work count value relative to the reference count value;
and judging whether the clock frequency of the controller is normal or not according to the clock drift amount.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
acquiring a reference count value, wherein the reference count value is the count of the fixed-period pulse in a preset time by a counting module;
controlling a timing module to perform timing work according to the preset time, wherein the timing frequency of the timing module is obtained by frequency division of the clock frequency of the controller;
controlling the counting module to count the fixed period pulse when the timing module performs the timing work, and interrupting the counting when the timing module completes the timing work, so as to obtain a work count value;
calculating the clock drift amount of the controller according to the deviation of the work count value relative to the reference count value;
and judging whether the clock frequency of the controller is normal or not according to the clock drift amount.
According to the controller clock frequency detection method and device, the computer equipment and the storage medium, the counting module counts the fixed period pulse when the timing module works regularly according to the preset time, and then the timing deviation of the timing module is calculated through the counting deviation of the counting module, so that the drift condition of the clock frequency is reflected. The period of the fixed period pulse is fixed, so the detection result of the embodiment is more accurate.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method for detecting a clock frequency of a controller according to an embodiment;
FIG. 2 is a flow diagram illustrating a process for obtaining a reference count value according to one embodiment;
FIG. 3 is a flowchart illustrating a process of determining whether the clock frequency of the controller is normal according to the clock drift amount in one embodiment;
fig. 4 is a block diagram of a controller clock frequency detection apparatus according to an embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.
With the development of information technology, embedded system software has been widely applied to equipment in key fields such as aerospace, rail transit, nuclear power, automotive electronics and the like. How to guarantee the safety of the embedded software and prevent serious personal, property and environmental loss is a core problem concerned by the development and development of the software of the products.
Functional safety standards such as IEC61508, IEC62279 and IEC60880 are issued by European and American countries and used for stipulating functional safety technical requirements which are mandatory or recommended to be adopted by high-safety software, but how to design an effective technical approach to meet the standards is a great challenge in the industry.
In IEC 61508.1-2010 "part 1 of electric/electronic programmable electronic controller: in the general requirements standard, the embedded controllers are classified into SIL 1-SIL 4 controllers according to their potential safety hazards, and the safety measures that must be taken by the relevant controllers are specified. Wherein the controller clock frequency monitoring is a safety measure that the controller must take above the SIL2 level. The controller clock frequency detection method of the present application can be (but is not limited to) applied to the detection of whether the clock frequency of the controller is normal or not.
In one embodiment, as shown in fig. 1, there is provided a controller clock frequency detection method, including:
in step S1, a reference count value is acquired.
The reference count value is the count of the fixed period pulse within the preset time by the counting module. The preset time may be set according to actual conditions, and for example, it may be set to 1 millisecond. The reference count value may be denoted as Cref。
And step S2, controlling the timing module to work regularly according to the preset time.
The timing frequency of the timing module is obtained by dividing the clock frequency of the controller, and the two are in linear relation. In particular, the timing module may control a timer within the controller. Of course, the present application is not limited thereto, and may be an external timer or the like.
And step S3, controlling the counting module to count the fixed period pulse when the timing module performs timing work, and interrupting the counting when the timing module completes the timing work, thereby obtaining a work count value.
The counting module may control a counter within the controller. Of course, the present application is not limited thereto, and may be an external counter or the like. And after the timing module finishes timing work and interrupts counting, reading the counting to obtain a work counting value.
The priority of "interrupt" here may be set to the highest level. At the moment, the counting of the counting module can be effectively prevented from being influenced by other interrupt events, and the counting of the working counting value is accurate.
In step S4, the clock drift amount of the controller is calculated based on the deviation of the duty count value from the reference count value.
The timing frequency of the timing module is obtained by dividing the clock frequency. Therefore, when the clock frequency of the controller drifts, the timing frequency of the timing module also drifts. Accordingly, the timing time of the timing module for performing the timing operation may actually deviate from the preset time.
The counting module counts the fixed period pulses. Therefore, if the time of the two counting is the same, the counting of the counting module should be the same. If the counting time of the two times of counting is actually different, the counting of the counting module is also different.
Therefore, the counting module generates a deviation between the working count value obtained within the timing time of the timing module for performing the timing operation and the reference count value. Therefore, the clock drift amount of the controller can be calculated according to the deviation of the work count value relative to the reference count value.
The amount of clock drift here can be expressed as;
Fwarp＝(|Creal-Cref|/Cref)*Fosc
wherein, FwarpAs an amount of frequency drift, CrealIs a work count value, CrefTo refer to the count value, FoscThe controller normal clock frequency.
And step S5, judging whether the clock frequency of the controller is normal according to the clock drift amount.
The specific determination process may be, for example: and judging whether the clock drift amount is smaller than a drift threshold value or not. And when the clock drift amount is smaller than the offset threshold value, judging that the clock frequency of the controller is normal. When the clock drift amount is notAnd when the frequency is smaller than the offset threshold value, judging that the clock frequency of the controller is abnormal. The offset threshold may be set according to practical requirements, for example, it may be 0.707Fosc
In the clock frequency detection method of the controller according to the embodiment, the counting module is controlled to count the fixed period pulses when the timing module performs timing work according to the preset time, and then the timing deviation of the timing module is calculated through the counting deviation of the counting module, so that the drift condition of the clock frequency is reflected. The period of the fixed period pulse is fixed, so the detection result of the embodiment is more accurate.
In one embodiment, as shown in fig. 2, the step S1 (acquiring the reference count value) includes:
and step S11, controlling the timing module to perform initial timing according to the preset time.
The "initial timing" here is the first timing of the timing module performed when the controller is in the initial state. The controller is in an initial state, namely, the controller is in a state of brand new use.
In step S12, the counting module is controlled to count the fixed period pulses when the timing module performs initial timing, and to interrupt counting when the timing module completes the initial timing, so as to obtain a reference count value.
The priority of "interrupt" here may also be set to the highest level. At the moment, the counting of the counting module can be effectively prevented from being influenced by other interrupt events, and the counting of the parameter counting value is accurate. After the reference count value is obtained, the count of the count module may be cleared.
Because the timing module performs initial timing, the controller is in a brand-new initial state, and the clock frequency of the controller is hardly drifted at this time. Therefore, the count value of the fixed-period pulse performed by the count module at the initial timing by the timing module may be taken as the reference count value. After the timing module finishes the initial timing and interrupts the counting, the counting is read to obtain a reference counting value. The reference count value can be simply and effectively obtained.
Of course, the present application is not limited to the foregoing, and in other embodiments, the process of obtaining the reference count value may be different from this. For example, the reference count value may be stored in its memory as an inherent performance parameter of the controller. The reference count value is obtained by directly reading the value at the time of use.
In one embodiment, referring to fig. 3, after step S5 (determining whether the controller clock frequency is normal according to the clock drift amount), the method further includes:
s51, if the controller clock frequency is abnormal, performing a clock frequency failure handling operation.
Performing the clock frequency fault handling operation may specifically include issuing an alarm message to notify a user. After obtaining the alarm information, the user can take protective measures, thereby ensuring the safety of the system. After the clock frequency fault handling operation is performed, other functions can be performed and the detection of whether the clock frequency of the controller is normal can be continued. Of course, in order to further ensure safety, other functions may not be executed after the fault handling operation, and the other functions may be executed after the clock frequency of the controller is detected to be normal and then normal.
S52, if the controller clock frequency is normal, performing other functions and continuing to detect whether the controller clock frequency is normal.
After judging whether the clock frequency of the controller is normal or not, continuously detecting whether the clock frequency of the controller is normal or not, so that the clock frequency of the controller can be continuously monitored, and the safe operation of the system when other functions are executed is further ensured.
In one embodiment, after the step S5, determining whether the controller clock frequency is normal according to the clock drift amount, the method further includes: in step S6, the count of the count module is cleared.
In this case, step S6 and the step after the counting module interrupts counting may constitute an interrupt service, and the interrupt service may be triggered by an interrupt trigger manner, so as to facilitate the counting of the subsequent counting module from zero. Of course, the present application is not limited thereto, and the reset may be performed before the counting module counts the next time (for example, the counting module counts the fixed period pulse when the timing module performs the next timing operation).
It should be understood that although the various steps in the flowcharts of fig. 1-3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-3 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps or stages.
In one embodiment, referring to fig. 4, a controller clock frequency detection apparatus is provided and includes a pulse generation module 100, a timing module 200, a counting module 300, an acquisition module 400, a calculation module 500, and a determination module 600.
The pulse generating module 100 may be a pulse generating chip or a pulse generator. The pulse generation module 100 may transmit a fixed period pulse to the counting module 300.
The timing frequency of the timing module 200 is obtained by dividing the clock frequency of the controller, so as to reflect the deviation of the clock frequency of the controller. The timing module 200 performs timing according to a preset time. The preset time may be set according to actual conditions, and for example, it may be set to 1 millisecond. The timing module 200 may control a timer within the controller. Of course, the present application is not limited thereto, and may be an external timer or the like.
The counting module 300 is connected to the pulse generating module 100 and can receive the fixed-period pulse signal transmitted by the pulse generating module 100. The counting module 300 may control a counter within the controller. At this time, the controller may be provided with a corresponding pin to receive the pulse signal transmitted by the pulse generating module 100. Of course, the present application is not limited thereto, and may be an external counter or the like.
When the timing module 200 can be a timer in the controller and the counting module 300 is a counter in the controller, no additional device is required to be added outside the controller, thereby reducing the product cost.
The counting module 300 counts the pulses emitted by the pulse generating module when the timing module performs the timing operation, and interrupts the counting when the timing module completes the timing operation, thereby obtaining a working count value.
The obtaining module 400 is configured to obtain a reference count value. The reference count value is the count of the fixed period pulse in the preset time by the counting module.
The calculating module 500 is used for calculating the clock drift amount of the controller according to the work count value and the reference count value.
The counting module 300 counts fixed period pulses. Therefore, if the time of the two counting times is the same, the counting of the counting module 300 should be the same. If the counting time of the two counts is different, the count of the counting module 300 will be different.
Since the clocking frequency of the timing module 200 is obtained by dividing the clock frequency. Therefore, when the clock frequency of the controller drifts, the timing frequency of the timing module 200 also drifts. Accordingly, the timing time of the timing module 200 actually deviates from the preset time.
Therefore, the counting module 300 may generate a deviation between the operation count value obtained during the timing period of the timing module 200 performing the timing operation and the reference count value. Therefore, the clock drift amount of the controller can be calculated according to the deviation of the work count value relative to the reference count value.
The amount of clock drift here can be expressed as;
Fwarp＝(|Creal-Cref|/Cref)*Fosc
wherein, FwarpAs an amount of frequency drift, CrealIs a work count value, CrefTo refer to the count value, FoscThe controller normal clock frequency.
The determining module 600 determines the controller clock according to the clock drift amountWhether the frequency is normal. The determining module may specifically determine the process as follows: and judging whether the clock drift amount is smaller than a drift threshold value or not. And when the clock drift amount is smaller than the offset threshold value, judging that the clock frequency of the controller is normal. And when the clock drift amount is not less than the offset threshold value, judging that the clock frequency of the controller is abnormal. The offset threshold may be set according to practical requirements, for example, it may be 0.707Fosc
In the clock frequency detection device of the controller according to the embodiment, the counting module counts the fixed period pulses when the timing module performs timing work according to preset time, and then calculates the timing deviation of the timing module according to the counting deviation of the counting module, so that the drift condition of the clock frequency is reflected. The period of the fixed period pulse is fixed, so the detection result of the embodiment is more accurate.
In one embodiment, the obtaining module 400 includes a timing module 200 and a counting module 300. The obtaining module 400 obtains the reference count value through the counting module 200 and the timing module 300.
The counting module 300 counts the fixed period pulses to obtain a reference count value when the timing module 200 performs initial timing according to a preset time. The initial timing is the first timing of the timing module when the controller is in the initial state. The controller is in an initial state, namely, the controller is in a state of brand new use. At which time the controller clock frequency has hardly drifted.
Therefore, the present embodiment may use the count value of the fixed-period pulse counted by the counting module 300 at the initial timing of the timing module 200 as the reference count value, so as to obtain the reference count value easily and effectively.
For specific limitations of the controller clock frequency detection device, reference may be made to the above limitations of the controller clock frequency detection method, which is not described herein again. The modules in the controller clock frequency detection device can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
in step S1, a reference count value is obtained, where the reference count value is the count of the fixed-period pulse counted by the counting module within a preset time.
And step S2, controlling the timing module to perform timing work according to preset time, wherein the timing frequency of the timing module is obtained by frequency division of the clock frequency of the controller.
And step S3, controlling the counting module to count the fixed period pulse when the timing module performs timing work, and interrupting the counting when the timing module completes the timing work, thereby obtaining a work count value.
In step S4, the clock drift amount of the controller is calculated based on the deviation of the duty count value from the reference count value.
And step S5, judging whether the clock frequency of the controller is normal according to the clock drift amount.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and step S11, controlling the timing module to perform initial timing according to the preset time, wherein the initial timing is the first timing performed by the timing module when the controller is in the initial state. In step S12, the counting module is controlled to count the fixed period pulses when the timing module performs initial timing, and to interrupt counting when the timing module completes the initial timing, so as to obtain a reference count value.
In one embodiment, the processor, when executing the computer program, further performs the steps of: in step S51, if the controller clock frequency is abnormal, a clock frequency failure handling operation is performed. In step S52, if the controller clock frequency is normal, other functions are performed and it is continuously detected whether the controller clock frequency is normal.
In one embodiment, the processor, when executing the computer program, further performs the steps of: in step S6, the count of the count module is cleared.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
in step S1, a reference count value is obtained, where the reference count value is the count of the fixed-period pulse counted by the counting module within a preset time.
And step S2, controlling the timing module to perform timing work according to preset time, wherein the timing frequency of the timing module is obtained by frequency division of the clock frequency of the controller.
And step S3, controlling the counting module to count the fixed period pulse when the timing module performs timing work, and interrupting the counting when the timing module completes the timing work, thereby obtaining a work count value.
In step S4, the clock drift amount of the controller is calculated based on the deviation of the duty count value from the reference count value.
And step S5, judging whether the clock frequency of the controller is normal according to the clock drift amount.
In one embodiment, the computer program when executed by the processor further performs the steps of: and step S11, controlling the timing module to perform initial timing according to the preset time, wherein the initial timing is the first timing performed by the timing module when the controller is in the initial state. In step S12, the counting module is controlled to count the fixed period pulses when the timing module performs initial timing, and to interrupt counting when the timing module completes the initial timing, so as to obtain a reference count value.
In one embodiment, the computer program when executed by the processor further performs the steps of: in step S51, if the controller clock frequency is abnormal, a clock frequency failure handling operation is performed. In step S52, if the controller clock frequency is normal, other functions are performed and it is continuously detected whether the controller clock frequency is normal.
In one embodiment, the computer program when executed by the processor further performs the steps of: in step S6, the count of the count module is cleared.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile memory may include Read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
In the description herein, references to the description of "one embodiment," "another embodiment," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (11)
1. A method for detecting a clock frequency of a controller, comprising:
acquiring a reference count value, wherein the reference count value is the count of the fixed-period pulse in a preset time by a counting module;
controlling a timing module to perform timing work according to the preset time, wherein the timing frequency of the timing module is obtained by frequency division of the clock frequency of the controller;
controlling the counting module to count the fixed period pulse when the timing module performs the timing work, and interrupting the counting when the timing module completes the timing work, so as to obtain a work count value;
calculating the clock drift amount of the controller according to the deviation of the work count value relative to the reference count value;
and judging whether the clock frequency of the controller is normal or not according to the clock drift amount.
2. The controller clock frequency detection method of claim 1, wherein the obtaining a reference count value comprises:
controlling the timing module to perform initial timing according to the preset time, wherein the initial timing is the first timing performed by the timing module when the controller is in an initial state;
and controlling the counting module to count the fixed period pulse when the timing module performs the initial timing, and interrupting the counting when the timing module completes the initial timing, so as to obtain the reference count value.
3. The controller clock frequency detection method according to claim 1 or 2, characterized by further comprising: setting the priority of the interrupt to a highest level.
4. The method for detecting the clock frequency of the controller according to claim 1, wherein after determining whether the clock frequency of the controller is normal according to the clock drift amount, the method further comprises:
if the clock frequency of the controller is abnormal, performing clock frequency fault processing operation;
and if the clock frequency of the controller is normal, executing other functions and continuously detecting whether the clock frequency of the controller is normal.
5. The method according to claim 4, wherein the performing a clock frequency failure handling operation comprises issuing an alarm message.
6. The method for detecting the clock frequency of the controller according to claim 1, wherein after determining whether the clock frequency of the controller is normal according to the clock drift amount, the method further comprises:
and clearing the count of the counting module.
7. A controller clock frequency detection apparatus, comprising:
the pulse generating module is used for transmitting fixed-period pulses;
the timing module is used for carrying out timing work according to preset time, and the timing frequency is obtained by frequency division of the clock frequency of the controller;
the counting module is connected with the pulse generating module and used for counting the pulses transmitted by the pulse generating module when the timing module performs the timing work and interrupting the counting when the timing module completes the timing work so as to obtain a work count value;
the acquisition module is used for acquiring a reference count value, wherein the reference count value is the count of the counting module on the fixed-period pulse within the preset time;
the calculation module is used for calculating the clock drift amount of the controller according to the work count value and the reference count value;
and the judging module is used for judging whether the clock frequency of the controller is normal or not according to the clock drift amount.
8. The apparatus of claim 7, wherein the timing module is a timer in the controller and/or the counting module is a counter in the controller.
9. The apparatus according to claim 7 or 8, wherein the obtaining module includes the timing module and the counting module, and the reference count value is obtained by counting the fixed-period pulses by the counting module when the timing module performs an initial timing according to a preset time, where the initial timing is a first timing performed by the timing module when the controller is in an initial state.
10. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 6.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.
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