CN111726198B - Iterative detection and decoding circuit and method thereof, and MIMO receiver - Google Patents
Iterative detection and decoding circuit and method thereof, and MIMO receiver Download PDFInfo
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- CN111726198B CN111726198B CN201910223235.XA CN201910223235A CN111726198B CN 111726198 B CN111726198 B CN 111726198B CN 201910223235 A CN201910223235 A CN 201910223235A CN 111726198 B CN111726198 B CN 111726198B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0047—Decoding adapted to other signal detection operation
- H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/0413—MIMO systems
Abstract
Iterative detection and decoding circuit and method thereof, and multi-input multi-output receiver, the decoding circuit is configured to perform M external iterations on a received signal, and N is performed in the ith external iteration of the external iterations i A plurality of internal iterations, wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N 1 To N M Are positive integers and include at least two distinct values.
Description
Technical Field
The present disclosure is directed to an iterative detection and decoding circuit, an iterative detection and decoding method, and a multiple-input multiple-output (MIMO) receiver using a recursive detection and decoding (iterative detection and decoding; IDD) technique.
Background
In recent years, with the development of information technology, the demand for transmission rate has increased. In response to the high transmission rate requirement, one of the solutions proposed in the industry is mimo communication technology, which uses multiple antennas to transmit and receive signals to achieve the high transmission rate requirement. However, in the mimo communication system, the number of transmit/receive antennas, the number of bits of symbols, and/or the code constraint length (code constraint length) are greatly increased, resulting in limited transmission performance.
Disclosure of Invention
The present disclosure is directed to an iterative detection and decoding circuit, an iterative detection and decoding method, and a mimo receiver, which can reduce the packet error rate and the operation complexity under the high transmission rate requirement, thereby increasing the transmission performance.
One embodiment of the present disclosure is an iterative detection and decoding circuit, whichConfigured to perform M outer iterations of the received signal, and N in an i-th outer iteration of the outer iterations i A plurality of internal iterations, wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N 1 To N M Are positive integers and include at least two distinct values.
Another embodiment of the present disclosure is an iterative detection and decoding method comprising: performing M external iterations on the received signal; n in the ith external iteration of the external iterations i Performing internal iteration; wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N 1 To N M Are positive integers and include at least two distinct values.
Yet another embodiment of the present disclosure is a multiple-input multiple-output (mimo) receiving circuit including a plurality of antennas, a demapper, and an iterative detection and decoding circuit. The antennas are configured to receive multiple-input multiple-output signals. The demapper is coupled to the antennas and configured to demodulate the multiple-input multiple-output signals. The iterative detection and decoding circuit is coupled to the demapper and configured to perform M external iterations on the MIMO signals to obtain decoded signals, and N in the ith external iteration of the external iterations i A plurality of internal iterations, wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N 1 To N M Are positive integers and include at least two distinct values.
Drawings
For a more complete understanding of the embodiments and advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a MIMO receiver according to an embodiment of the present disclosure;
FIGS. 3A-3C are graphs of K values versus signal-to-noise ratio for different iterations with 4X 4 MIMO, B/D/E channels, modulation and coding schemes (modulation and coding scheme; MCS) of MCS-11, decoding using low density parity check (low density parity check; LDPC) codes, and packet error rates of 0.1;
FIGS. 4A-4C are graphs of SNR versus packet error rate for different iterations with high efficiency (4×4 MIMO, B/D/E channel, modulation and coding scheme of MCS-11, decoding using low density parity check code, and K value equal to 64;
FIG. 5 is a chart showing statistics of the number of additions corresponding to different iterations in a 4×4 MIMO, 160MHz channel bandwidth, modulation and coding scheme of MCS-11, decoding using low density parity check code, and K value equal to 64; and
FIG. 6 is a graph showing the number of additions in different iterations and the SNR to achieve a packet error rate of 0.1 in a 4×4 MIMO, D-channel, modulation and coding scheme of MCS-11, decoding using low density parity check codes, and K value equal to 64.
Detailed Description
Embodiments of the present disclosure are discussed in detail below. However, it is to be understood that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The particular embodiments discussed are merely illustrative and are not meant to limit the scope of the present disclosure.
The term "coupled," as used herein, may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other. "coupled" may also mean that two or more elements are operational or acts with each other.
It will be understood that, although the terms "first," "second," and the like may be used herein to describe various signals and/or entities, these signals and/or entities should not be limited by these terms. These terms are merely intended to distinguish one signal and/or entity from another signal and/or entity.
Referring to fig. 1, fig. 1 is a schematic diagram of a communication system 100 according to some embodiments of the disclosure. The communication technology employed by communication system 100 may be, for example, wireless local area network communication technology, cellular network (cellular network) communication technology, long-term evolution-Advanced (long-term evolution Advanced), and/or other suitable wireless communication technology. The communication system 100 includes communication devices 110, 120 and a wireless channel 130, wherein the communication devices 110, 120 are communicatively connected via the wireless channel 130. Each communication device 110, 120 may be a signal transmitting end, a signal receiving end, or a signal transmitting/receiving end. The communication devices 110, 120 each include an antenna array 112, 122 of multiple antennas that wirelessly communicate over a wireless channel 130. The number of antennas in the antenna arrays 112, 122 may be the same or different. Further, all or part of the antennas of the antenna arrays 112, 122 may be selectively enabled for transmission and reception of radiated signals upon signal transmission between the communication devices 110, 120. The wireless channel 130 may support multiple-input multiple-output (MISO) transmissions, single-input multiple-output (SIMO) transmissions, and single-input single-output (SISO) transmissions between the communication devices 110, 120.
Herein, a communication device (e.g., communication devices 110, 120, etc.) may represent a variety of different implementations including, but not limited to, mobile devices Such As Stations (STAs), mobile Stations (MSs), user Equipment (UEs), laptops, mobile phones, and other mobile devices and Access Points (APs), base Stations (BSs), evolved nodebs (enbs), calculator devices, server devices, workstations, and other stationary devices. Further, the communication devices herein may communicate wirelessly with remote entities in a mobile environment or in a fixed environment.
Fig. 2 is a schematic diagram of a mimo receiver 200 according to an embodiment of the present disclosure. The mimo receiver 200 includes an antenna array 210, fast fourier transformers (fast Fourier transformer; FFTs) 220 (1) through 220 (X), a demapper (demapper) 230, an iterative detection and decoding circuit 240, and a decision circuit 250. The mimo receiver 200 is suitable for use in the communication system 100 of fig. 1 and the communication device 110 and/or the communication device 120 of fig. 1 may be implemented as the mimo receiver 200 or as a device that includes the functionality performed by the mimo receiver 200.
Antenna array 210 includes antennas 212 (1) -212 (X) to receive mimo signals, fast fourier transformers 220 (1) -220 (X) to convert the received mimo signals from a time domain or spatial domain to a frequency domain, and demapper 230 is configured to demodulate the mimo signals. The iterative detection and decoding circuit 240 is coupled to the demapper 230 and is configured to perform external iterations on the mimo signal to obtain a decoded signal. The decision circuit 250 is used for converting the decoded signal outputted from the iterative detection and decoding circuit 240 into binary data. In some embodiments, the decision circuit 250 is a hard decision circuit, which compares a threshold value with the level of the decoded signal outputted from the iterative detection and decoding circuit 240, and determines the bit value represented by the level of the decoded signal according to the comparison result of the threshold value and the level of the decoded signal.
In the iterative detection and decoding circuit 240, the detector 241 receives the input signal from the demapper 230 and the delayed signal from the buffer 246, and generates a first detection result by detecting the input signal; adder 242 sums the detection result and the delayed signal from buffer 246 to generate a first summed signal. The buffer 243 is used for temporarily storing and delaying the summation signal from the adder 242 to generate a delay signal; the decoder 244 receives and decodes the delayed signal from the buffer 243 to generate a decoded signal; adder 245 sums the decoded signal and the delayed signal from buffer 243 to generate a summed signal; buffer 246 buffers and delays the summed signal from adder 245 to generate a delayed signal. In the iterative operation of the iterative detection and decoding circuit 240, the iteration performed between the detector 241 and the decoder 244 is an outer iteration (outer iteration), and the iteration performed inside the decoder 244 is an inner iteration (inner iteration).
In some embodiments, the detector 241 is a soft-in soft-out (soft input soft output; SISO) type MIMO detector, the decoder 244 is a soft-in soft-out type error correction code (error correction code; ECC) decoder, and the detector 241 is a soft-in soft-out type MIMO detector, and the detector 241 is configured to exchange external messages with the decoder 244. Further, the detector 241 may employ a soft-in soft-out K-best (K-best) detection method or a soft-in soft-out lattice reduction (lattice reduction; LR) aided K-best detection method, and the decoder 244 may be a low-density parity check code (Low-density parity check; LDPC) decoder. In other embodiments, decoder 244 may be a binary convolutional code (binary convolutional code; BCC) decoder.
In the following description, (M, N) iterative means that M external iterations are performed and N internal iterations are performed in all external iterations, (2, N) 1 /N 2 ) The iterative approach represents 2 external iterations and N in each of the two external iterations 1 、N 2 A number of internal iterations, (3, N 1 /N 2 /N 3 ) The iterative approach represents performing 3 external iterations and N in each of the three external iterations 1 、N 2 、N 3 And (5) performing internal iteration.
Fig. 3A to 3C are graphs of K values versus signal to noise ratio for different iterations under the conditions of 4×4 mimo, B/D/E channel, modulation and coding scheme of MCS-11, decoding using low density parity check code and packet error rate of 0.1, where K values are candidate size parameters for K-best detection. In the graphs of fig. 3A-3C, curves 302, 304, 306, 308, 310 represent (1, 12), (2, 12), (3, 12), (4, 12), and (5, 12) iterations, respectively. As can be seen from fig. 3A to 3C, the signal to noise ratio decreases with increasing number of external iterations, wherein the signal to noise ratio difference between the curve 302 and the curve 304 exceeds 1dB, the signal to noise ratio difference between the curve 304 and the curve 306 is between 0.3dB and 0.5dB, and the signal to noise ratio difference between the curve 306 and the curve 308 is below 0.3 dB. Furthermore, for each curve 304, 306, 308, 310, the signal-to-noise ratio gap between K value 32 and K value 64 does not exceed 0.5dB and is less than the signal-to-noise ratio gap between K value 16 and K value 32 under the same channel.
Fig. 4A-4C are graphs of snr versus packet error rate for different iterations with an efficient 4 x 4 mimo, B/D/E channel, modulation and coding scheme of MCS-11, decoding using low density parity check codes, and K value equal to 64. In the graphs of the relationships shown in FIGS. 4A-4C, curves 402, 404, 406, 408, 410, 412, 414, 416 represent (1, 12), (3, 2/8/2), (2, 12/12), (3, 2/6/4), (3, 2/4/6), (3, 6/6/6), (3, 2/4/12), and (3, 12/12/12) iterative modes, respectively. As can be seen from fig. 4A to fig. 4C, for the same iteration mode with the total internal iteration number, the iteration mode with the larger external iteration number has better packet error rate performance under the same signal-to-noise ratio, and further, for the iteration mode with the same total internal iteration number and the same external iteration number, the iteration mode with the increasing internal iteration number has better packet error rate performance under the same signal-to-noise ratio. In addition, the (3, 2/4/6) and (3, 6/6/6) iterative modes have similar packet error rates under the same signal-to-noise ratio, and the (3, 2/4/12) and (3, 12/12/12) iterative modes have similar packet error rates under the same signal-to-noise ratio.
FIG. 5 is a statistical plot of the number of additions corresponding to different iterations in a 4×4 MIMO, 160MHz channel bandwidth, modulation and coding scheme of MCS-11, decoding using low density parity check codes, and K value equal to 64. In fig. 5, "qrd+lr", "K-best", "LLR" and "LDPC" are QR decomposition (QR composition) operation plus lattice reduction operation, K-best detection method, log likelihood ratio (log likelihood ratio; LLR) operation and low density parity check code decoding operation, respectively. As can be seen from fig. 5, the number of addition operations in the (3, 2/4/6) iterative mode is only increased by about 10% compared with the number of addition operations in the (1, 12) iterative mode, whereas the number of addition operations in the (3, 2/4/12) iterative mode is only 25% but less than the number of addition operations in the (1, 12) iterative mode.
Next, fig. 6 is a graph showing the number of additions in different iterations and achieving a snr of 0.1 for a 4×4 mimo D channel, modulation and coding scheme of MCS-11, decoding using low density parity check codes, and K value equal to 64. As can be seen from FIG. 6, the (3, 2/4/6) iterative approach and the (3, 2/4/12) iterative approach have good comprehensive performance under the comprehensive consideration of the addition times and the signal-to-noise ratio. In practical applications, the (3, 2/4/12) iterative approach may be chosen if the packet error rate performance is the primary consideration, while the (3, 2/4/6) iterative approach may be chosen if the complexity (operand) performance is the primary consideration.
While the present disclosure has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present disclosure, and the scope of the present disclosure is therefore defined by the appended claims.
[ symbolic description ]
100 communication system
110. 120 communication device
112. 122 antenna array
130. Channel
200. Multiple input multiple output receiver
210. Antenna array
212 (1) -212 (X) antennas
220 (1) -220 (X) fast Fourier transformer
230. Demapper
240. Iterative detection and decoding circuit
241. Detector for detecting a target object
242. 245 adder
243. 246 buffer
244. Decoder
250. Decision circuit
302. 304, 306, 308, 310, 402, 404, 406, 408, 410, 412, 414, 416 curves.
Claims (7)
1. An iterative detection and decoding circuit comprising:
a detector configured to receive an input signal and a first delay signal and generate a first detection result by detecting the input signal;
a first adder coupled to the detector, the first adder configured to sum the first detection result and the first delay signal to generate a first sum signal;
a first buffer coupled to the first adder, the first buffer configured to temporarily store and delay the first sum signal to generate a second delay signal;
a decoder coupled to the first buffer, the decoder configured to receive and decode the second delayed signal to generate a decoded signal;
a second adder coupled to the decoder and the first buffer, the second adder configured to sum the decoded signal and the second delay signal to generate a second sum signal; and
a second buffer coupled to the first adder, the second adder and the detector, the second buffer configured to temporarily store and delay the second sum signal to generate the first delay signal;
wherein the iterative detection and decoding circuit is configured to perform M external iterations on the input signal between the detector and the decoder, and N within the decoder in an i-th external iteration of the external iterations i A plurality of internal iterations, wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N 1 To N M Are all positive integers and N 1 To N M Sequentially increasing.
2. The iterative detection and decoding circuit of claim 1 wherein M is 3.
3. The iterative detection and decoding circuit of claim 2 wherein N 1 、N 2 And N 3 2, 4 and 6, respectively.
4. The iterative detection and decoding circuit of claim 1 in which the detector is a soft-input soft-output detector and the decoder is a soft-input soft-output decoder.
5. The iterative detection and decoding circuit of claim 4 in which the soft-input soft-output detector is based on a K-best detection method.
6. An iterative detection and decoding method for an iterative detection and decoding circuit, comprising:
receiving an input signal and a first delay signal by a detector of the iterative detection and decoding circuit, and generating a first detection result by detecting the input signal;
summing the first detection result and the first delay signal by a first adder of the iterative detection and decoding circuit coupled to the detector to generate a first summed signal;
temporarily storing and delaying the first summation signal by a first buffer coupled to the first adder of the iterative detection and decoding circuit to generate a second delay signal;
receiving and decoding the second delay signal by a decoder of the iterative detection and decoding circuit coupled to the first buffer to generate a decoded signal;
summing the decoded signal and the second delayed signal by a second adder of the iterative detection and decoding circuit coupled to the decoder and the first buffer to generate a second summed signal;
temporarily storing and delaying the second summation signal by a second buffer of the iterative detection and decoding circuit coupled to the first adder, the second adder and the detector to generate the first delay signal;
m outer iterations of the input signal between the detector and the decoder by the iterative detection and decoding circuit, and N inside the decoder in an i-th outer iteration of the outer iterations i Performing internal iteration;
wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N 1 To N M Are all positive integers and N 1 To N M Sequentially increasing.
7. A multiple-input multiple-output receiver comprising:
a plurality of antennas configured to receive multiple-input multiple-output signals;
a demapper coupled to the plurality of antennas, the demapper configured to demodulate the multiple-input multiple-output signal; and
an iterative detection and decoding circuit coupled to the demapper, the iterative detection and decoding circuit comprising:
a detector configured to receive the mimo signal and a first delay signal and generate a first detection result by detecting the mimo signal;
a first adder coupled to the detector, the first adder configured to sum the first detection result and the first delay signal to generate a first sum signal;
a first buffer coupled to the first adder, the first buffer configured to temporarily store and delay the first sum signal to generate a second delay signal;
a decoder coupled to the first buffer, the decoder configured to receive and decode the second delayed signal to generate a decoded signal;
a second adder coupled to the decoder and the first buffer, the second adder configured to sum the decoded signal and the second delay signal to generate a second sum signal; and
a second buffer coupled to the first adder, the second adder and the detector, the second buffer configured to temporarily store and delay the second sum signal to generate the first delay signal;
wherein the iterative detection and decoding circuit is configured to perform M outer iterations on the multiple-input multiple-output signal between the detector and the decoder to obtain the decoded signal, and N inside the decoder in an i-th outer iteration of the outer iterations i A plurality of internal iterations, wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N 1 To N M Are all positive integers and N 1 To N M Sequentially increasing.
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