CN111726198A

CN111726198A - Iterative detection and decoding circuit and method thereof, and multi-input multi-output receiver

Info

Publication number: CN111726198A
Application number: CN201910223235.XA
Authority: CN
Inventors: 杨家骧; 王耀斌; 文及志; 柳德政; 黄崇荣
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-03-22
Filing date: 2019-03-22
Publication date: 2020-09-29
Anticipated expiration: 2039-03-22
Also published as: CN111726198B

Abstract

An iterative detection and decoding circuit and method, and a multi-input multi-output receiver, the decoding circuit is configured to perform M external iterations on a received signal, and perform N external iterations in the ith external iteration of the external iterations_iA sub-internal iteration, where M is an integer greater than 1, i is a positive integer less than or equal to M, N₁To N_MAre all positive integers and contain at least two distinct values.

Description

Iterative detection and decoding circuit and method thereof, and multi-input multi-output receiver

Technical Field

The present disclosure relates to an iterative detection and decoding circuit, an iterative detection and decoding method, and a multiple-input multiple-output (MIMO) receiver using an Iterative Detection and Decoding (IDD) technique.

Background

In recent years, with the development of information technology, the demand for transmission rate has increased. In response to the high transmission rate requirement, the industry has proposed a corresponding solution, one of which is mimo communication technology, which utilizes an antenna array with multiple antennas to transmit and receive signals to achieve the high transmission rate requirement. However, in the mimo communication system, the complexity of decoding and decoding, the amount of computation, and the like are greatly increased due to the number of transmit/receive antennas, the number of bits of a symbol, and/or the code constraint length (code constraint length), and thus the transmission performance is limited.

Disclosure of Invention

It is therefore an objective of the present disclosure to provide an iterative detection and decoding circuit, an iterative detection and decoding method, and a mimo receiver using recursive detection and decoding techniques, which can improve the packet error rate and reduce the computational complexity under the requirement of high transmission rate, thereby increasing the transmission performance.

One embodiment of the disclosure is an iterative detection and decoding circuit configured to perform M external iterations on a received signal and perform N in an i-th one of the external iterations_iA sub-internal iteration, where M is an integer greater than 1, i is a positive integer less than or equal to M, N₁To N_MAre all positive integers and contain at least two distinct values.

Another embodiment of the present disclosure is an iterative detection and decoding method, comprising: performing M external iterations on the received signal; performing N in an i-th one of the external iterations_iA secondary internal iteration; wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N₁To N_MAre all positive integers and contain at least two distinct values.

Another embodiment of the present disclosure is a mimo receiving circuit comprising a plurality of antennas, a demapper, and an iterative detection and decoding circuit. The antennas are configured to receive multiple-input multiple-output signals. A demapper is coupled to the antennas and configured to demodulate the multiple-input multiple-output signals. The iterative detection and decoding circuit is coupled to the demapper and is configured to perform M external iterations on the multiple-input multiple-output signals to obtain decoded signals, and perform N external iterations in the ith external iterations of the external iterations_iA sub-internal iteration, where M is an integer greater than 1, i is a positive integer less than or equal to M, N₁To N_MAre all positive integers and contain at least two distinct values.

Drawings

For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram of a communication system according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a multiple-input multiple-output receiver according to an embodiment of the disclosure;

FIGS. 3A to 3C are graphs showing K value and SNR relationships for different iterations under the condition of 4 × 4 MIMO, B/D/E channel, Modulation and Coding Scheme (MCS) of MCS-11, decoding using Low Density Parity Check (LDPC) code, and packet error rate of 0.1;

FIGS. 4A-4C are graphs of SNR vs. PER for different iterations with high efficiency (high efficiency)4 × 4 MIMO, B/D/E channel, modulation and coding scheme MCS-11, decoding using low density parity check code, and K equal to 64;

FIG. 5 is a statistical chart of the number of addition operations corresponding to different iterations in an environment with 4 × 4 MIMO, 160MHz channel bandwidth, modulation and coding scheme MCS-11, low density parity check code decoding, and a K value equal to 64; and

FIG. 6 is a diagram of the number of additions and SNR for achieving a packet error rate of 0.1 for different iterations in a 4 × 4 MIMO, D-channel, modulation and coding scheme MCS-11, decoding using low density parity check codes and a K value of 64.

Detailed Description

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

As used herein, the term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other. "coupled" may also mean that two or more components interoperate or act.

It will be understood that, although the terms first, second, etc. may be used herein to describe various signals and/or entities, these signals and/or entities should not be limited by these terms. These terms are only used to distinguish one signal and/or entity from another signal and/or entity.

Referring to fig. 1, fig. 1 is a schematic diagram of a communication system 100 according to some embodiments of the present disclosure. The communication technology employed by the communication system 100 may be, for example, a wireless local area network (wlan) communication technology, a cellular network (cellular network) communication technology, a long-term evolution Advanced (LTE-Advanced) technology, and/or other suitable wireless communication technologies. The communication system 100 includes

communication devices

110, 120 and a wireless channel 130, wherein the

communication devices

110, 120 are communicatively connected via the wireless channel 130. Each

communication device

110, 120 may be a signal transmitting end, a signal receiving end, or a signal transmitting/receiving end. The

communication devices

110, 120 each include an

antenna array

112, 122 of multiple antennas that communicate wirelessly over a wireless channel 130. The number of antennas in the

antenna arrays

112, 122 may be the same or different. In addition, all or a portion of the

antenna arrays

112, 122 may be selectively enabled for transmitting and receiving radiated signals during signal transmission between the

communication devices

110, 120. The wireless channel 130 may support multiple-input multiple-output (MISO), single-input multiple-output (SIMO), and single-input single-output (SISO) transmissions between the

communication devices

110, 120.

In this context, a communication device (e.g.,

communication devices

110, 120, etc.) may represent a variety of different embodiments including, but not limited to, mobile devices Such As Stations (STAs), Mobile Stations (MSs), User Equipment (UEs), laptops, mobile phones, and fixed devices such as Access Points (APs), Base Stations (BSs), evolved node BS (enbs), calculator equipment, server equipment, workstations, etc. Further, the communication devices herein may wirelessly communicate with remote entities in a mobile environment or in a fixed environment.

Fig. 2 is a schematic diagram of a mimo receiver 200 according to an embodiment of the present disclosure. The mimo receiver 200 includes an antenna array 210, a Fast Fourier Transformer (FFT) 220(1) -220 (X), a demapper 230, an iterative detection and decoding circuit 240, and a decision circuit 250. The mimo receiver 200 is suitable for use in the communication system 100 of fig. 1, and the communication device 110 and/or the communication device 120 of fig. 1 may be implemented as the mimo receiver 200 or as a device including the functions performed by the mimo receiver 200.

The antenna array 210 includes antennas 212(1) -212 (X) for receiving mimo signals, fast fourier transformers 220(1) -220 (X) for converting the received mimo signals from time domain or spatial domain to frequency domain, and a demapper 230 configured for demodulating the mimo signals. The iterative detection and decoding circuit 240 is coupled to the demapper 230, which is configured to perform an outer iteration on the multiple-input multiple-output signal to obtain a decoded signal. The decision circuit 250 is used to convert the decoded signal outputted from the iterative detection and decoding circuit 240 into binary data. In some embodiments, the decision circuit 250 is a hard decision circuit, which compares a threshold value with the level of the decoded signal output by the iterative detection and decoding circuit 240, and determines the bit value represented by the level of the decoded signal according to the comparison result between the threshold value and the level of the decoded signal.

In the iterative detection and decoding circuit 240, the detector 241 receives the input signal from the demapper 230 and the delayed signal from the buffer 246, and generates a first detection result by detecting the input signal; the adder 242 adds the detection result and the delayed signal from the buffer 246 to generate a first added signal. The buffer 243 is used for temporarily storing and delaying the summed signal from the adder 242 to generate a delayed signal; the decoder 244 receives and decodes the delayed signal from the buffer 243 to generate a decoded signal; an adder 245 adds the decoded signal and the delayed signal from the buffer 243 to generate a summed signal; buffer 246 temporarily stores and delays the summed signal from adder 245 to generate a delayed signal. In the iterative operation performed by the iterative detection and decoding circuit 240, the iteration performed between the detector 241 and the decoder 244 is an outer iteration (outer iteration), and the iteration performed inside the decoder 244 is an inner iteration (inner iteration).

In some embodiments, the detector 241 is a Soft Input Soft Output (SISO) type MIMO detector, the decoder 244 is an Error Correction Code (ECC) decoder, the detector 241 is a soft input soft output type MIMO detector, and the detector 241 is for exchanging external information with the decoder 244. Further, the detector 241 may use a soft input soft output type K-best (K-best) detection method or a soft input soft output type Lattice Reduction (LR) assisted K-best detection method, and the decoder 244 may be a low-density parity check code (LDPC) decoder. In other embodiments, decoder 244 may be a Binary Convolutional Code (BCC) decoder.

In the following description, the (M, N) iteration mode represents that M external iterations are performed and N internal iterations are performed in all the external iterations, (2, N)₁/N₂) The iterative mode represents 2 external iterations and N is performed in each of the two external iterations₁、N₂Second internal iteration, (3, N)₁/N₂/N₃) The iterative mode represents that 3 external iterations are performed and N is performed in the three external iterations respectively₁、N₂、N₃And (5) secondary internal iteration.

FIGS. 3A to 3C are graphs showing K values of candidate scale (candidate size) parameters of the K-best detection method in different iterations under the conditions of 4 × 4 MIMO, B/D/E channel, modulation and coding scheme MCS-11, decoding using low density parity check code, and packet error rate 0.1. In the relationship graphs shown in fig. 3A to 3C, the

curves

302, 304, 306, 308, 310 represent the iteration modes of (1,12), (2,12), (3,12), (4,12) and (5,12), respectively. As can be seen from fig. 3A to 3C, the signal-to-noise ratio decreases with the increase of the number of external iterations, wherein the signal-to-noise ratio difference between the curve 302 and the curve 304 exceeds 1dB, the signal-to-noise ratio difference between the curve 304 and the curve 306 is between 0.3dB and 0.5dB, and the signal-to-noise ratio difference between the curve 306 and the curve 308 is below 0.3 dB. In addition, for each

curve

304, 306, 308, 310, the difference in SNR between K32 and K64 does not exceed 0.5dB for the same channel and is less than the difference in SNR between K16 and K32.

FIGS. 4A-4C are graphs of SNR vs. PER for different iterations with high performance 4 x 4 MIMO, B/D/E channel, modulation and coding scheme MCS-11, decoding using low density parity check code, and K equal to 64. In the relationship graphs shown in fig. 4A to 4C, the

curves

402, 404, 406, 408, 410, 412, 414, 416 represent the iteration modes of (1,12), (3,2/8/2), (2,12/12), (3,2/6/4), (3,2/4/6), (3,6/6/6), (3,2/4/12), and (3,12/12/12), respectively. As can be seen from fig. 4A to 4C, for the iteration method with the same total internal iteration number, the iteration method with a larger number of external iterations has better performance of the packet error rate under the same signal-to-noise ratio, and further, for the iteration method with the same total internal iteration number and the same number of external iterations, the iteration method with an increasing number of internal iterations has better performance of the packet error rate under the same signal-to-noise ratio. Furthermore, the packet error rates at the same signal-to-noise ratio for the (3,2/4/6) and (3,6/6/6) iterations behave similarly, and the packet error rates at the same signal-to-noise ratio for the (3,2/4/12) and (3,12/12/12) iterations behave similarly.

FIG. 5 is a statistical chart of the number of addition operations corresponding to different iterations in an environment with 4 × 4 MIMO, 160MHz channel bandwidth, modulation and coding scheme MCS-11, low density parity check code decoding, and a K value equal to 64. In FIG. 5, "QRD + LR", "K-best", "LLR", and "LDPC" are QR decomposition (QR decomposition) operations plus lattice reduction operations, K-best detection methods, Log Likelihood Ratio (LLR) operations, and low density parity check code decoding operations, respectively. As can be seen from fig. 5, the number of addition operations in the (3,2/4/6) iterative method is increased by about 10% only compared to the number of addition operations in the (1,12) iterative method, and the number of addition operations in the (3,2/4/12) iterative method is 25% more than the number of addition operations in the (1,12) iterative method but less than the number of addition operations in the (2,12/12) iterative method.

Next, FIG. 6 is a diagram of the number of additions and SNR for achieving a packet error rate of 0.1 for different iterations in a 4 × 4 MIMO, D-channel, modulation and coding scheme MCS-11, decoding using low density parity check codes and a K value equal to 64. As can be seen from fig. 6, the (3,2/4/6) iterative method and the (3,2/4/12) iterative method have good comprehensive performance under the comprehensive consideration of the number of addition operations and the signal-to-noise ratio performance. For practical applications, the (3,2/4/12) iteration mode may be selected if the packet error rate performance is the main consideration, and the (3,2/4/6) iteration mode may be selected if the complexity (computation) performance is the main consideration.

While the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure, and therefore the scope of the present disclosure should be limited only by the terms of the appended claims.

[ notation ] to show

100 communication system

110. 120 communication device

112. 122 antenna array

130 channel

200 MIMO receiver

210 antenna array

212(1) -212 (X) antenna

220(1) -220 (X) fast Fourier transformer

230 demapper

240 iterative detection and decoding circuit

241 detector

242. 245 adder

243. 246 buffer

244 decoder

250 decision circuit

302. 304, 306, 308, 310, 402, 404, 406, 408, 410, 412, 414, 416.

Claims

1. An Iterative Detection and Decoding (IDD) circuit configured to perform M external iterations on a received signal and perform N in an i-th external iteration of the external iterations_iA sub-internal iteration, where M is an integer greater than 1, i is a positive integer less than or equal to M, N₁To N_MAre all positive integers and contain at least two distinct values.

2. The iterative detection and decoding circuit of claim 1, wherein N₁Less than N_M。

3. The iterative detection and decoding circuit of claim 1, wherein M is 3.

4. The iterative detection and decoding circuit of claim 3, wherein N₁Is less than or equal to N₂And N is₂Is less than or equal to N₃。

5. The iterative detection and decoding circuit of claim 3, wherein N₁、N₂And N₃Respectively 2, 4 and 6.

6. The iterative detection and decoding circuit of any one of claims 1-5, comprising:

a detector configured to receive an input signal and a first delayed signal and generate a first detection result by detecting the input signal;

a first adder coupled to the detector, the first adder configured to add the first detection result and the first delayed signal to generate a first added signal;

a first buffer coupled to the first adder, the first buffer configured to buffer and delay the first summed signal to generate a second delayed signal;

a decoder coupled to the first buffer, the decoder configured to receive and decode the first delayed signal to generate a decoded signal;

a second adder coupled to the decoder and the first buffer, the second adder configured to sum the decoded signal and the second delayed signal to generate a second summed signal; and

a second buffer coupled to the first adder, the second adder, and the detector, the second buffer configured to buffer and delay the second summed signal to generate the first delayed signal.

7. The iterative detection and decoding circuit of claim 6, wherein said detector is a Soft Input Soft Output (SISO) detector and said decoder is a soft input soft output decoder.

8. The iterative detection and decoding circuit of claim 7 wherein said soft-input soft-output detector is based on a K-best (K-best algorithm) detection method.

9. An Iterative Detection and Decoding (IDD) method, comprising:

performing M external iterations on the received signal;

performing N in an i-th one of the external iterations_iA secondary internal iteration;

wherein M is an integer greater than 1, i is a positive integer less than or equal to M, N₁To N_MAre all positive integers and contain at least two distinct values.

10. A multiple-input multiple-output (MIMO) receiver, comprising:

a plurality of antennas configured to receive a multiple-input multiple-output signal;

a demapper (demapper) coupled to said plurality of antennas, said demapper configured to demodulate said multiple-input multiple-output signal; and

an Iterative Detection and Decoding (IDD) circuit coupled to the demapper, the IDD circuit configured to perform M external iterations on the MIMO signal to obtain a decoded signal, and perform N external iterations in an ith external iteration of the external iterations_iA sub-internal iteration, where M is an integer greater than 1, i is a positive integer less than or equal to M, N₁To N_MAre all positive integers and contain at least two distinct values.