CN111726139A

CN111726139A - Divide by two frequency division circuit and bluetooth transceiver

Info

Publication number: CN111726139A
Application number: CN202010552867.3A
Authority: CN
Inventors: 闫广; 钱永学; 王同; 刘澎; 李嘉文; 魏文钦; 蔡光杰; 孟浩; 黄鑫
Original assignee: Guangzhou Aung Rui Microelectronics Technology Co ltd
Current assignee: Guangzhou Aung Rui Microelectronics Technology Co ltd
Priority date: 2020-06-17
Filing date: 2020-06-17
Publication date: 2020-09-29
Anticipated expiration: 2040-06-17
Also published as: CN111726139B

Abstract

The application discloses divide-by-two frequency divider circuit and bluetooth transceiver, in the divide-by-two frequency divider circuit, through control bias module state, can realize Q way and produce the control of the operating condition of module and injection locking module, when signal reception, can place the bias module in first state, drive I way and produce the module, Q way produces the module, drive module and injection locking module work jointly, produce orthogonal I way output signal and Q way output signal, and when signal transmission, can place the bias module in the second state, only drive I way and produce the module and drive the module work and can satisfy bluetooth transceiver's signal transmission requirement, the power consumption of dividing the divide-by-two frequency divider circuit has been reduced promptly in signal transmission process. Meanwhile, in the process of receiving the signals by the two-frequency dividing circuit, the I path generation module and the Q path generation module are subjected to injection locking through the injection locking module, so that the phase of the signals generated by the I path generation module is enabled to be 90 degrees ahead of the phase of the signals generated by the Q path generation module.

Description

Divide by two frequency division circuit and bluetooth transceiver

Technical Field

The present application relates to the field of integrated circuit technology, and more particularly, to a divide-by-two frequency divider circuit and a bluetooth transceiver.

Background

For a Bluetooth Low Energy (BLE) transceiver with two-point modulation, the transceiver generally includes a receiver and a transmitter, where the receiver receives a signal, mixes the signal with an I-path signal and a Q-path signal generated by a divide-by-two circuit (div2) in a PLL (Phase Locked Loop), down-converts the received signal to a Low frequency, amplifies and samples the signal, and outputs the signal to a digital baseband for processing, thereby completing a signal receiving process.

The transmitter adopts a two-point modulation mode, a signal to be transmitted by a digital baseband is injected into a PLL from a Voltage-Controlled Oscillator (VCO) and a frequency Divider (Multi-module Divider, MMD), the output of the Voltage-Controlled Oscillator is subjected to frequency division by a div2 circuit and is output to an amplifier, and the signal is transmitted to the air to complete a signal transmission process.

It is an effort of those skilled in the art to reduce the power consumption of a bluetooth transceiver during operation and thereby improve the endurance of a device on which the bluetooth transceiver is mounted.

Disclosure of Invention

In order to solve the technical problem, the application provides a divide-by-two frequency dividing circuit and a bluetooth transceiver to realize the purpose of reducing the power consumption of the divide-by-two frequency dividing circuit in the working process and reducing the power consumption of the bluetooth transceiver.

In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:

a divide-by-two circuit, comprising: the device comprises a bias module, an injection locking module, an I path generation module, a Q path generation module and a driving module; wherein the content of the first and second substances,

the bias module comprises a first state and a second state, and is used for generating a first bias signal, a second bias signal and a first driving signal when in the first state; generating a first bias signal, a third bias signal and a second drive signal when in the second state;

the I path generating module is used for generating a first injection signal to transmit to the injection locking module when receiving the first bias signal, and is used for generating an initial I path signal to transmit to the driving module when receiving the first bias signal;

the Q-path generating module is used for generating a second injection signal to transmit to the injection locking module and generating an initial Q-path signal to transmit to the driving module when receiving the second bias signal; and for stopping operation upon receipt of said third bias signal;

the driving module is used for processing the initial I path signal to generate an I path output signal when receiving the initial I path signal and processing the initial Q path signal to generate a Q path output signal when receiving the initial Q path signal;

and the injection locking module is used for generating a first feedback signal to transmit to the I-path generation module and generating a second feedback signal to transmit to the Q-path generation module when receiving the first injection signal and the second injection signal at the same time so as to perform injection locking on the I-path generation module and the Q-path generation module.

Optionally, the injection locking module includes: a first transistor and a second transistor; wherein the content of the first and second substances,

the control end of the first transistor is used for receiving the first injection signal, the first end of the first transistor is grounded, and the second end of the first transistor is used for outputting the second feedback signal;

the control end of the second transistor is used for receiving the second injection signal, the first end of the second transistor is grounded, and the second end of the second transistor is used for outputting the first feedback signal.

Optionally, the I-path generating module and the Q-path generating module include: a first signal circuit;

the first signal circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; wherein the content of the first and second substances,

a control end of the third transistor is electrically connected with a first end of a first resistor and a first end of a first capacitor, a second end of the first resistor is used as a first receiving end of the first signal circuit, and a second end of the first capacitor is used as a first input end of the first signal circuit; the first end of the third transistor is electrically connected with the first end of the seventh transistor, the first end of the eleventh transistor and the first end of the thirteenth transistor and used for receiving a first working voltage; a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor;

a control end of the fourth transistor is electrically connected with a control end of the fifth transistor, a second end of the eleventh transistor, a second end of the twelfth transistor, a control end of the thirteenth transistor and a control end of the fourteenth transistor and serves as a second output end of the first signal circuit; a second end of the fourth transistor is electrically connected with a second end of the fifth transistor, a control end of the eighth transistor and a control end of the ninth transistor and serves as a first feedback end of the first signal circuit;

a first terminal of the fifth transistor is electrically connected with a second terminal of the sixth transistor; a control end of the sixth transistor is electrically connected with a first end of the third resistor and a first end of the third capacitor, and a second end of the third resistor is used as a second receiving end of the first signal circuit; a second end of the third capacitor is used as a second input end of the first signal circuit; a first end of the sixth transistor is electrically connected with a first end of the tenth transistor, a first end of the twelfth transistor and a first end of the fourteenth transistor;

a control end of the seventh transistor is electrically connected with a first end of the second resistor and a first end of the second capacitor, a second end of the second resistor is used as a first receiving end of the first signal circuit, and a second end of the second capacitor is used as a second receiving end of the first signal circuit; a second terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor;

a second end of the eighth transistor is electrically connected with a second end of the ninth transistor, a control end of the eleventh transistor and a control end of the twelfth transistor and serves as a first output end of the first signal circuit;

a first terminal of the ninth transistor is electrically connected to a second terminal of the tenth transistor;

a control end of the tenth transistor is electrically connected with a first end of the fourth resistor and a first end of a fourth capacitor, a second end of the fourth resistor is used as a second receiving end of the first signal circuit, and a second end of the fourth capacitor is used as a first input end of the first signal circuit;

a second terminal of the thirteenth transistor is electrically connected to a second terminal of the fourteenth transistor.

Optionally, the first bias signal includes a first sub-bias signal and a second sub-bias signal;

a first input end of a first signal circuit in the I-path generation module is configured to receive a first input signal, a second input end of the first signal circuit is configured to receive a second input signal, a first receiving end of the first signal circuit is configured to receive a first sub-bias signal, a second receiving end of the first signal circuit is configured to receive a second sub-bias signal, a first feedback end of the first signal circuit is configured to receive the first feedback signal, a first output end of the first signal circuit is configured to output a first sub-output signal, a second output end of the first signal circuit is configured to output a second sub-output signal, the first sub-output signal and the second sub-output signal form the initial I-path signal, and the first sub-output signal is further transmitted to the injection locking module as the first injection signal.

Optionally, the second bias signal includes a third sub-bias signal and a fourth sub-bias signal;

the third bias signal comprises a fifth sub-bias signal and a sixth sub-bias signal;

a first input end of a first signal circuit in the Q-path generation module is configured to receive the second input signal, a second input end of the first signal circuit is configured to receive the first input signal, a first receiving end of the first signal circuit is configured to receive a third sub-bias signal or a fifth sub-bias signal, a second receiving end of the first signal circuit is configured to receive the fourth sub-bias signal or the seventh sub-bias signal, a first feedback end of the first signal circuit is configured to receive the second feedback signal, a first output end of the first signal circuit is configured to output a third sub-output signal, a second output end of the second signal circuit is configured to output a fourth sub-output signal, the third sub-output signal and the fourth sub-output signal form the initial Q-path signal, and the third sub-output signal is further transmitted to the injection locking module as the second injection signal;

and a first receiving end of a first signal circuit in the Q-path generation module receives a fifth sub-bias signal, and the second receiving end stops working when receiving the seventh sub-bias signal.

Optionally, the I-path generating module and the Q-path generating module include: a second signal circuit;

the second signal circuit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twentieth transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor; wherein the content of the first and second substances,

the control end of the fifteenth transistor is electrically connected with the control end of the eighteenth transistor, the second end of the twenty-third transistor, the second end of the twenty-fourth transistor, the control end of the twenty-fifth transistor and the control end of the twenty-sixth transistor and serves as a fourth output end of the second signal circuit;

a first end of the fifteenth transistor is electrically connected with a first end of the nineteenth transistor, a first end of the twenty-third transistor and a first end of the twenty-fifth transistor; a second terminal of the fifteenth transistor is electrically connected to a first terminal of the sixteenth transistor;

a control end of the sixteenth transistor is electrically connected to both a first end of the fifth resistor and a first end of the fifth capacitor, a second end of the fifth resistor is used as a third receiving end of the second signal circuit, and a second end of the fifth capacitor is used as a third input end of the second signal circuit; a second end of the sixteenth transistor is electrically connected with a second end of the seventeenth transistor, a control end of the nineteenth transistor and a control end of the twenty-second transistor and serves as a second feedback end of the second signal circuit;

a control end of the seventeenth transistor is electrically connected with a first end of the eighth resistor and a first end of the eighth capacitor, a second end of the eighth resistor is used as a fourth receiving end of the second signal circuit, a second end of the eighth capacitor is used as the fourth input end, and a first end of the seventeenth transistor is electrically connected with a second end of the eighteenth transistor;

the first end of the eighteenth transistor is electrically connected with the first end of the twenty-second transistor, the first end of the twenty-fourth transistor and the first end of the twenty-sixth transistor; a second terminal of the nineteenth transistor is electrically connected to a first terminal of the twentieth transistor;

a control end of the twentieth transistor is electrically connected with a first end of the sixth resistor and a first end of the sixth capacitor, a second end of the sixth resistor is used as a third receiving end of the second signal circuit, and a second end of the sixth capacitor is used as the fourth input end; a second end of the twentieth transistor is electrically connected with a second end of the twenty-first transistor, a control end of the twenty-third transistor and a control end of the twenty-fourth transistor, and is used as a third output end of the second signal circuit;

a control end of the twenty-first transistor is electrically connected with a first end of the eighth resistor and a first end of the eighth capacitor, a second end of the eighth resistor is used as a fourth receiving end of the second signal circuit, and a second end of the eighth capacitor is used as a third input end of the second signal circuit; a first terminal of the twenty-first transistor is electrically connected to a second terminal of the twenty-second transistor;

a second terminal of the twenty-fifth transistor is electrically connected to a second terminal of the twenty-sixth transistor.

a third input end of a second signal circuit in the I-path generation module is configured to receive a first input signal, a fourth input end of the second signal circuit is configured to receive a second input signal, a third receiving end of the second signal circuit is configured to receive a first sub-bias signal, a fourth receiving end of the second signal circuit is configured to receive a second sub-bias signal, a second feedback end of the second signal circuit is configured to receive the first feedback signal, a third output end of the second signal circuit is configured to output a first sub-output signal, a fourth output end of the third signal circuit is configured to output a second sub-output signal, the first sub-output signal and the second sub-output signal form the initial I-path signal, and the first sub-output signal is further transmitted to the injection locking module as the first injection signal.

a third input end of a second signal circuit in the Q-path generation module is configured to receive the second input signal, a fourth input end of the second signal circuit is configured to receive the first input signal, a third receiving end of the second signal circuit is configured to receive a third sub-bias signal or a fifth sub-bias signal, a fourth receiving end of the second signal circuit is configured to receive the fourth sub-bias signal or the seventh sub-bias signal, a second feedback end of the second signal circuit is configured to receive the second feedback signal, a third output end of the second signal circuit is configured to output a third sub-output signal, a fourth output end of the fourth signal circuit is configured to output a fourth sub-output signal, the third sub-output signal and the fourth sub-output signal form the initial Q-path signal, and the third sub-output signal is further transmitted to the injection locking module as the second injection signal;

and a third receiving end of a second signal circuit in the Q-path generation module receives a fifth sub-bias signal, and the fourth receiving end stops working when receiving the seventh sub-bias signal.

Optionally, the driving module includes: two groups of driving units, wherein each group of driving units comprises two driving circuits;

the drive circuit includes: a twenty-seventh transistor, a twenty-eighth transistor, a ninth capacitor, a tenth capacitor, a ninth resistor, and a tenth resistor; wherein the content of the first and second substances,

a control end of the twenty-seventh transistor is electrically connected with a first end of the ninth resistor and a first end of the ninth capacitor, and the first end of the twenty-seventh transistor is used for receiving a first sub-driving signal; a second end of the twenty-seventh transistor is connected with a second end of the twenty-eighth transistor and serves as an output end of the driving circuit;

a second end of the ninth resistor is used for receiving a second sub-driving signal, and a second end of the ninth capacitor is electrically connected with a second end of the tenth capacitor and serves as a receiving end of the driving circuit;

a first end of the tenth capacitor is electrically connected with a first end of the tenth resistor and a control end of the twenty-eighth transistor, and a second end of the tenth resistor is used for receiving a third sub-driving signal;

a first terminal of the twenty-eighth transistor is grounded;

the first sub driving signal, the second sub driving signal and the third sub driving signal constitute the first driving signal or the second driving signal;

the two groups of driving units are used for respectively processing the I path of initial signals and the Q path of initial signals to obtain I path of output signals and Q path of output signals.

A bluetooth transceiver comprising a divide-by-two circuit as claimed in any preceding claim.

As can be seen from the above technical solutions, the present application provides a divide-by-two frequency dividing circuit and a bluetooth transceiver, and through further research, the inventor finds that the divide-by-two frequency dividing circuit is used in both signal receiving and transmitting processes of the bluetooth transceiver, but through further research, the bluetooth transceiver only needs the divide-by-two frequency dividing circuit to generate orthogonal I-path output signals and Q-path output signals in the signal receiving process, and does not need the orthogonal I-path output signals and Q-path output signals in the signal transmitting process, therefore, in the divide-by-two frequency dividing circuit provided by the present application, by controlling states (a first state and a second state) of a bias module, control of operating states of a Q-path generating module and an injection locking module can be achieved, when the divide-by-two frequency dividing circuit needs to perform signal receiving, the bias module can be placed in the first state, the driving I-path generation module, the driving Q-path generation module, the driving module and the injection locking module work together to generate orthogonal I-path output signals and Q-path output signals, when the divide-by-two frequency division circuit needs to transmit signals, the biasing module can be placed in the second state, the signal transmission requirements of the Bluetooth transceiver can be met only by driving the I-path generation module and the driving module to work, namely, the power consumption of the divide-by-two frequency division circuit is reduced in the signal transmission process, and therefore the power consumption of the Bluetooth transceiver is reduced.

Meanwhile, in the signal receiving process of the divide-by-two frequency dividing circuit, the I path generation module and the Q path generation module are subjected to injection locking through the injection locking module, and the phase of a signal generated by the I path generation module is enabled to be 90 degrees ahead of that of a signal generated by the Q path generation module.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a divide-by-two frequency divider according to an embodiment of the present application;

fig. 2 is a schematic circuit diagram of an injection locking module according to an embodiment of the present application;

fig. 3 is a schematic circuit diagram of an I-path generating module according to an embodiment of the present disclosure;

fig. 4 is a schematic circuit diagram of a Q-path generating module according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of an I-path generating module according to another embodiment of the present application;

fig. 6 is a schematic circuit diagram of a Q-path generating module according to another embodiment of the present disclosure;

fig. 7 is a schematic circuit structure diagram of a driving module according to an embodiment of the present application;

fig. 8 is a timing diagram of an input signal and an output signal according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

An embodiment of the present application provides a divide-by-two frequency dividing circuit, as shown in fig. 1, including: a bias module 10, an injection locking module 20, an I-path generation module 40, a Q-path generation module 30 and a driving module 50; wherein the content of the first and second substances,

the bias module 10 comprises a first state and a second state, and is configured to generate a first bias signal, a second bias signal and a first driving signal in the first state; generating a first bias signal, a third bias signal and a second drive signal when in the second state;

the I-path generating module 40 is configured to generate a first injection signal to transmit to the injection locking module 20 when receiving the first bias signal, and to generate an initial I-path signal to transmit to the driving module 50 when receiving the first bias signal;

the Q-path generating module 30 is configured to generate a second injection signal to transmit to the injection locking module 20 when receiving the second bias signal, and generate an initial Q-path signal to transmit to the driving module 50; and for stopping operation upon receipt of said third bias signal;

the driving module 50 is configured to process the initial I-path signal to generate an I-path output signal when receiving the initial I-path signal, and to process the initial Q-path signal to generate a Q-path output signal when receiving the initial Q-path signal;

the injection locking module 20 is configured to generate a first feedback signal to transmit to the I-path generating module 40 and generate a second feedback signal to transmit to the Q-path generating module 30 when receiving the first injection signal and the second injection signal at the same time, so as to perform injection locking on the I-path generating module 40 and the Q-path generating module 30.

Still referring to fig. 1, in general, the first bias signal generated by the bias module 10 includes a first sub-bias signal and a second sub-bias signal, the second bias signal includes a third sub-bias signal and a fourth sub-bias signal, and the first drive signal includes a first sub-drive signal and a second sub-drive signal. When the bias module 10 is in the second state, the generated third bias signal includes a fifth sub-bias signal and a sixth sub-bias signal, where the fifth sub-bias signal and the third sub-bias signal have different level states, and the sixth sub-bias signal and the fourth sub-bias signal have different level states, for example, when the fifth sub-bias signal is at a high level, the third sub-bias signal is at a low level, and when the sixth sub-bias signal is at a high level, the fourth sub-bias signal is at a low level. Similarly, when the bias module 10 is in the second state, the generated second sub driving signal may include a third sub driving signal and a fourth sub driving signal, the third sub driving signal is different from the first sub driving signal in level state, and the fourth sub driving signal is different from the second sub driving signal in level state.

In fig. 1, Va represents the first sub-bias signal, Vb represents the second sub-bias signal, outc _ Q and outb _ Q represent the initial Q-path signal output by the Q-path generation module 30, and outc _ Q also represents the second injection signal transmitted to the injection locking module; outb _ I and outb _ I represent the initial I-path signal output by the I-path generation module 30, while outb _ I also represents the first injection signal to be transmitted to the injection locking module; outa _ Q represents a second feedback signal injected into the lock module feedback 20, outa _ I represents a first feedback signal injected into the lock module feedback 20, qp and qn represent Q-path output signals with large capacitance driving capability obtained after the initial Q-path signals are processed by the driving module 50, and ip and in represent I-path output signals with large capacitance driving capability obtained after the initial I-path signals are processed by the driving module 50.

Since the second offset signal and the third offset signal are both generated by the same circuit unit, in this embodiment, the third sub-offset signal in the second offset signal and the fifth sub-offset signal in the third offset signal are both denoted by Vc, and the fourth sub-offset signal in the second offset signal and the sixth sub-offset signal in the third offset signal are both denoted by Vd.

In an actual application process, when the bias module is in the first state, outputting a first bias signal, a second bias signal and a first driving signal to drive the injection locking module 20, the I-path generation module 40, the Q-path generation module 30 and the driving module 50 to cooperatively work; and when the bias module is in the second state, a fifth sub-bias signal can be obtained by pulling up the third sub-bias signal to the first operating voltage VDD, a sixth bias signal can be obtained by pulling down the fourth sub-bias signal to the ground GND, and the second sub-drive signal can be pulled up to VDD and the third sub-drive signal can be pulled down to the ground by pulling down the first sub-drive signal to the ground, so that the second drive signal can be obtained. The switching of the biasing module between the first state and the second state may be implemented by other controllers or control circuits.

A description is given below of a possible structure of each block included in the divide-by-two circuit provided in the embodiment of the present application.

Referring to fig. 2, the injection locking module 20 includes: a first transistor M1 and a second transistor M2; wherein the content of the first and second substances,

the control terminal of the first transistor M1 is used for receiving the first injection signal, the first terminal of the first transistor M1 is grounded, and the second terminal of the first transistor M1 is used for outputting the second feedback signal;

the control terminal of the second transistor M2 is configured to receive the second injection signal, the first terminal of the second transistor M2 is grounded, and the second terminal of the second transistor M2 is configured to output the first feedback signal.

In fig. 2, GND denotes ground.

Referring to fig. 3 and 4, the I-way generation module 40 and the Q-way generation module 30 include: a first signal circuit;

The first bias signal comprises a first sub-bias signal and a second sub-bias signal;

a first input end of a first signal circuit in the I-path generating module 40 is configured to receive a first input signal, a second input end is configured to receive a second input signal, a first receiving end is configured to receive a first sub-bias signal, a second receiving end is configured to receive a second sub-bias signal, a first feedback end is configured to receive the first feedback signal, a first output end is configured to output a first sub-output signal, a second output end is configured to output a second sub-output signal, the first sub-output signal and the second sub-output signal form the initial I-path signal, and the first sub-output signal is further transmitted to the injection locking module 20 as the first injection signal.

The second bias signal comprises a third sub-bias signal and a fourth sub-bias signal;

a first input end of a first signal circuit in the Q-path generating module 30 is configured to receive the second input signal, a second input end of the first signal circuit is configured to receive the first input signal, a first receiving end of the first signal circuit is configured to receive a third sub-bias signal or a fifth sub-bias signal, a second receiving end of the second signal circuit is configured to receive the fourth sub-bias signal or the seventh sub-bias signal, a first feedback end of the first signal circuit is configured to receive the second feedback signal, a first output end of the first signal circuit is configured to output a third sub-output signal, a second output end of the second signal circuit is configured to output a fourth sub-output signal, the third sub-output signal and the fourth sub-output signal form the initial Q-path signal, and the third sub-output signal is further transmitted to the injection locking module 20 as the second injection signal;

the first receiving end of the first signal circuit in the Q-path generating module 30 receives the fifth sub-bias signal, and the second receiving end stops working when receiving the seventh sub-bias signal.

In this embodiment, the control terminal of the transistor may refer to a gate of the MOS transistor, the first terminal of the transistor may refer to a source of the MOS transistor, and the second terminal of the transistor may refer to a drain of the MOS transistor.

In fig. 3, a schematic diagram of a structure when the first signal circuit is used as the I-circuit generating module 40 is shown, and accordingly, the first resistor, the second resistor, the third resistor and the fourth resistor are respectively represented by R1, R2, R3 and R4, and the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are respectively represented by C1, C2, C3 and C4; the first to twelfth transistors are denoted by MI1 and MI2 … … MI12, respectively.

In fig. 4, a schematic diagram of a structure when the first signal circuit is used as the Q-path generation module 30 is shown, and accordingly, the first resistor, the second resistor, the third resistor and the fourth resistor are respectively represented by R5, R6, R7 and R8, and the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are respectively represented by C5, C6, C7 and C8; the first to twelfth transistors are denoted by MQ1, MQ2 … … MQ12, respectively.

In fig. 3 and 4, VDD denotes the first operating voltage, GND denotes ground, out _ loop denotes a third output terminal of the first signal circuit, inp denotes a first input signal, and inn denotes a second input signal. In the circuit structures shown in fig. 3 and 4, the first end of the P-type transistor related to the inp and inn input is connected to VDD, the first end of the N-type transistor is connected to GND, and only the second end of the transistor related to the input is dynamically changed, so that the possibility that inp and inn are influenced is reduced.

The devices in fig. 3 and 4 are connected in the same manner, but the signals received at the respective ports are different.

In an embodiment of the present application, another possible circuit structure diagram of the I-path generating module 40 and the Q-path generating module 30 is further provided, and referring to fig. 5 and 6, the I-path generating module 40 and the Q-path generating module 30 include: a second signal circuit;

a third input end of the second signal circuit in the I-path generating module 40 is configured to receive a first input signal, a fourth input end is configured to receive a second input signal, a third receiving end is configured to receive a first sub-bias signal, a fourth receiving end is configured to receive a second sub-bias signal, the second feedback end is configured to receive the first feedback signal, the third output end is configured to output a first sub-output signal, the fourth output end is configured to output a second sub-output signal, the first sub-output signal and the second sub-output signal form the initial I-path signal, and the first sub-output signal is further transmitted to the injection locking module 20 as the first injection signal.

a third input end of the second signal circuit in the Q-path generating module 30 is configured to receive the second input signal, a fourth input end of the second signal circuit is configured to receive the first input signal, a third receiving end of the second signal circuit is configured to receive a third sub-bias signal or the fifth sub-bias signal, a fourth receiving end of the second signal circuit is configured to receive the fourth sub-bias signal or the seventh sub-bias signal, a second feedback end of the second signal circuit is configured to receive the second feedback signal, a third output end of the second signal circuit is configured to output a third sub-output signal, a fourth output end of the fourth signal circuit is configured to output a fourth sub-output signal, the third sub-output signal and the fourth sub-output signal form the initial Q-path signal, and the third sub-output signal is further transmitted to the injection locking module 20 as the second injection signal;

the third receiving end of the second signal circuit in the Q-path generating module 30 receives the fifth sub-bias signal, and the fourth receiving end stops working when receiving the seventh sub-bias signal.

Similarly, in fig. 5, a schematic diagram of the structure when the second signal circuit is used as the I-circuit generating module 40 is shown, and accordingly, the first resistor, the second resistor, the third resistor and the fourth resistor are respectively represented by R1 ', R2', R3 'and R4', and the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are respectively represented by C1 ', C2', C3 'and C4'; the first to twelfth transistors are denoted by MI1 ', MI2 ' … … MI12 ', respectively.

In fig. 6, a schematic diagram of a structure when the second signal circuit is used as the Q-path generating module 30 is shown, and a schematic diagram of a structure when the first signal circuit is used as the Q-path generating module 30 is shown, and accordingly, the first resistor, the second resistor, the third resistor, and the fourth resistor are respectively represented by R5 ', R6', R7 ', and R8', and the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are respectively represented by C5 ', C6', C7 ', and C8'; the first to twelfth transistors are denoted by MQ1 ', MQ2 ', … … MQ12 ', respectively.

The devices of fig. 5 and 6 are connected in the same manner, but the signals received at the respective ports are different.

Alternatively, referring to fig. 7, the driving module 50 includes: two groups of driving units, wherein each group of driving units comprises two driving circuits;

a first terminal of the twenty-eighth transistor is grounded;

In fig. 7, four driving circuits are respectively shown, and each driving circuit processes one of the initial I-path signals or the initial Q-path signals to obtain final I-path output signals and Q-path output signals.

In fig. 7, of the four driving circuits, twenty-seventh transistors in the different driving circuits are denoted by M3, M5, M7, and M9, respectively, and twenty-eighth transistors in the different driving circuits are denoted by M4, M6, M8, and M10, respectively. Ninth capacitances in the different driving circuits are denoted by C9, C11, C13, and C15, tenth capacitances in the different driving circuits are denoted by C10, C12, C14, and C16, ninth resistances in the different driving circuits are denoted by R9, R11, R13, and R15, and tenth resistances in the different driving circuits are denoted by R10, R12, R14, and R16.

The operation of the divide-by-two frequency dividing circuit will be described with reference to the I-path driving module and the Q-path driving module shown in fig. 3 and 4 as an example.

In the I-path generation module, it is assumed that the initial state of the I-path generation module is outa _ I ═ 0, outb _ I ═ 1, and outc _ I ═ 0.

And a state A: when inp is 0 and inn is 1, MI1 and MI4 are turned on to act as resistors, MI3 and MI2 form inverters, outa _ i is 1, MI5 and MI8 are turned off, MI6 and MI7 are maintained in the original state, outb _ i is 1, MI9 and MI10 form inverters, and outc _ i is 0.

And in the state B, when inp is equal to 1 and inn is equal to 0, MI1 and MI4 are cut off, MI2 and MI3 are maintained in the original state, outa _ i is equal to 1, MI5 and MI8 are turned on, MI6 and MI7 form an inverter, outb _ i is equal to 0, MI9 and MI10 form an inverter, and outc _ i is equal to 1.

And C, state C: when inp is 0 and inn is 1, MI1 and MI4 are turned on, MI2 and MI3 form an inverter, outa _ i is 0, MI5 and MI8 are turned off, MI6 and MI7 are maintained in the original state, outb _ i is 0, MI9 and MI10 form an inverter, and outc _ i is 1.

And in the state D, when inp is equal to 1 and inn is equal to 0, MI1 and MI4 are cut off, MI2 and MI3 are maintained in the original state, outa _ i is equal to 0, MI5 and MI8 are switched on, MI6 and MI7 form an inverter, outb _ i is equal to 1, MI9 and MI10 form an inverter, outc _ i is equal to 0

In state E, when inp is 0 and inn is 1, MI1, MI4 are turned on, MI2 and MI3 form an inverter, outa _ i is 1, MI5 and MI8 are turned off, MI6 and MI7 are maintained in the original state, outb _ i is 1, MI9 and MI10 form an inverter, outc _ i is 0

Looking at the values of inp, inn, outa _ I, outb _ I, out _ I, state E is actually state A, and the I-way generation module continues in the order ABCDABCCDABCD … …. The four states ABCD are plotted as the waveform of fig. 8 and the truth table of table 1. As can be seen from the waveforms in fig. 8, outb _ i and outc _ i implement a divide-by-two function for the inputs inp and inn, and outb _ i and outc _ i are differential outputs. In the same way, the waveform and truth table of the output of the Q-path can be obtained, as shown in fig. 8 and table 1.

TABLE 1

Due to the disparity between the I-path generation module and the Q-path generation module in the initial state, it may cause the phase difference between the I-path and the Q-path to be not 90 ° but 270 °, which requires an injection locking module to help ensure that the phase difference is 90 °. As shown in fig. 8, outb _ I and outa _ Q are 180 ° out of phase, outc _ Q and outa _ I are 180 ° out of phase, and simple phase inversion of outb _ I and outa _ Q (180 ° out of phase) and outc _ Q and outa _ I (180 ° out of phase) is achieved by using the injection locking module structure in fig. 2, and by this way of signal injection, 90 ° lead of the I-path phase to the Q-path phase is ensured.

In an RX state, the bias module generates Va, Vb, Vc and Vd and sends the Va, Vb, Vc and Vd to the I-path generation module and the Q-path generation module, the injection locking module ensures that the I path leads the Q path by 90 degrees and outputs outc _ Q, outb _ Q, outc _ I and outb _ I of 2-frequency division to the driving module, the bias module generates VDD2, Vbp and Vbn and sends the VDD2, Vbp and Vbn to the driving module, and the driving module outputs qp, qn, ip and in quadrature signals capable of driving a large-capacitance load.

In the TX state, the bias module normally provides Va, Vb to the I-way generating module, which operates normally to generate the frequency-divided-by-2 signal outc _ I to be output via the inverter formed by MI11 and MI12 in fig. 3. The bias module controls Vc to VDD and Vd to GND, the MOS tube is guaranteed to be cut off, the Q-path generation module does not work, and the injection locking module which takes the output outc _ Q of the Q-path generation module as input does not work. The bias module controls VDD2 to ground, Vbp to VDD, and Vbn to GND, ensuring that the driving module does not operate. Only the bias module and the I-path generation module work, so that the power consumption is greatly reduced, and only a simple frequency division by 2 function is realized.

Correspondingly, the embodiment of the present application further provides a bluetooth transceiver, which includes the divide-by-two frequency division circuit according to any of the above embodiments.

In summary, the present invention provides a divide-by-two frequency divider circuit and a bluetooth transceiver, and the inventor finds through research that the divide-by-two frequency divider circuit is used in both signal receiving and transmitting processes of the bluetooth transceiver, but further researches find that the bluetooth transceiver only needs the divide-by-two frequency divider circuit to generate orthogonal I-path output signals and Q-path output signals in the signal receiving process, and does not need the orthogonal I-path output signals and Q-path output signals in the signal transmitting process, so that in the divide-by-two frequency divider circuit provided in the present invention, the control of the operating states of the Q-path generating module and the injection locking module can be realized by controlling the states (the first state and the second state) of the bias module, and when the divide-by-two frequency divider circuit needs to perform signal receiving, the bias module can be placed in the first state, the driving I-path generation module, the driving Q-path generation module, the driving module and the injection locking module work together to generate orthogonal I-path output signals and Q-path output signals, when the divide-by-two frequency division circuit needs to transmit signals, the biasing module can be placed in the second state, the signal transmission requirements of the Bluetooth transceiver can be met only by driving the I-path generation module and the driving module to work, namely, the power consumption of the divide-by-two frequency division circuit is reduced in the signal transmission process, and therefore the power consumption of the Bluetooth transceiver is reduced.

Features described in the embodiments in the present specification may be replaced with or combined with each other, each embodiment is described with a focus on differences from other embodiments, and the same and similar portions among the embodiments may be referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A divide-by-two circuit, comprising: the device comprises a bias module, an injection locking module, an I path generation module, a Q path generation module and a driving module; wherein the content of the first and second substances,

2. The divide-by-two frequency divider circuit of claim 1, wherein the injection locking module comprises: a first transistor and a second transistor; wherein the content of the first and second substances,

3. The divide-by-two frequency divider circuit of claim 1, wherein the I-path generating module and the Q-path generating module comprise: a first signal circuit;

4. The divide-by-two circuit of claim 3, wherein the first bias signal comprises a first sub-bias signal and a second sub-bias signal;

5. The divide-by-two circuit of claim 3, wherein the second bias signal comprises a third sub-bias signal and a fourth sub-bias signal;

6. The divide-by-two frequency divider circuit of claim 1, wherein the I-path generating module and the Q-path generating module comprise: a second signal circuit;

7. The divide-by-two circuit of claim 6, wherein the first bias signal comprises a first sub-bias signal and a second sub-bias signal;

8. The divide-by-two circuit of claim 6, wherein the second bias signal comprises a third sub-bias signal and a fourth sub-bias signal;

9. The divide-by-two circuit of claim 1, wherein the driving module comprises: two groups of driving units, wherein each group of driving units comprises two driving circuits;

a first terminal of the twenty-eighth transistor is grounded;

10. A bluetooth transceiver comprising the divide-by-two circuit of any one of claims 1-9.