CN111725325A - Novel thin-layer molybdenum disulfide field effect transistor - Google Patents
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- 229910052982 molybdenum disulfide Inorganic materials 0.000 title claims abstract description 22
- 230000005669 field effect Effects 0.000 title claims abstract description 21
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 title abstract description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 67
- 239000010409 thin film Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052961 molybdenite Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 34
- 239000010408 film Substances 0.000 claims description 22
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 17
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000012546 transfer Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000009987 spinning Methods 0.000 claims description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000011888 foil Substances 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 238000004021 metal welding Methods 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000007769 metal material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 26
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
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- 238000005411 Van der Waals force Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
The invention belongs to the field of semiconductor electronic devices, and particularly relates to a molybdenum disulfide (MoS) based thin layer2) A novel field effect transistor with a conductive channel. The field effect transistor includes a source, a drain, a gate dielectric, a conductive channel, and a metal pad. The source electrode and the drain electrode are made of graphene, the grid electrode is a heavily doped silicon substrate, the grid medium is an AlN thin film, and the conducting channel is a thin filmLayer MoS2. Compared with the prior similar devices, the invention has the following advantages: compared with the conventional SiO2The thin film gate dielectric and the AlN thin film have larger dielectric constant and thermal conductivity, so that the regulation and control capability of the field effect transistor gate on the carrier transport in the conducting channel can be obviously improved, the heat generated in the conducting channel can be quickly dissipated, and the self-heating effect of the field effect transistor is inhibited. Compared with a metal material, the graphene serving as the source electrode and the drain electrode can effectively reduce the source electrode and the drain electrode and the thin-layer MoS2The contact resistance therebetween.
Description
Technical Field
The invention belongs to the field of semiconductor electronic devices, and particularly relates to a novel thin molybdenum disulfide (MoS)2) A field effect transistor and a method of fabricating the same.
Background
Field Effect Transistors (FETs) are an important building block for building modern integrated circuits. The most common metal-oxide-semiconductor field effect transistor (MOSFET) is mainly composed of a source, a drain, a conductive channel, a gate dielectric and the like, and the magnitude of channel current between the source and the drain is regulated and controlled by gate voltage so as to realize logic operation. Under moore's law drive, increasing the density of integrated circuit transistors by shrinking device dimensions has been an effective method for the past few decades. However, in the context of current device feature sizes approaching 5nm, continuation of moore's law faces some significant technical challenges, such as short channel effects of FETs, power consumption and heat dissipation, and gate dielectric leakage. Among them, the problem of heat dissipation is one of the main reasons that currently limit further improvement of the integration level of FETs. FETs produce significant self-heating effects at high currents. Self-heating effects increase device power consumption, and the temperature rise caused by heat buildup can have a number of adverse effects on device performance and reliability.
Thin layer of molybdenum disulfide (MoS)2) Is an emerging two-dimensional nano material. Using a thin layer of MoS2As a FET conduction channel, ① has the advantage that its large forbidden bandwidth (about 1.85eV for a single layer and about 1.2eV for a bulk material) makes the MoS thin layer thinner than zero band gap graphene2FETs exhibit large current-to-switching ratios, ② thin layer MoS compared to silicon2Has larger electron effective mass and forbidden bandwidth and lower in-plane dielectric constant, so that the MoS is thin in a sub-5 nm scale2The FET is less susceptible to short channel effects, ③ MoS2The layers are combined by Van der Waals force, so that the uniform thickness control at an atomic level can be realized, and the thickness can be reduced to a single layer. A.Kis et al [ Nature Nanotechnology 6,147(2011)]Reported to be based on SiO2And HfO2Thin film gate dielectric, thin layer MoS of Au source and drain2FET, current switching ratio of about 108The subthreshold swing is 74 mV/dec. Bao et al [ Applied Physics letters 102,042104(2013)]Reported to be based on SiO2And thin layer MoS of PMMA film gate dielectric, Ti/Al source electrode and drain electrode2FET and its electric transport characteristics are characterized. Following thin layer MoS2Reduction of FET characteristic size and its use in SiO2、HfO2And the application of the flexible low-heat-conductivity substrate, the self-heating effect has more obvious influence on the electrical performance of the device. Y.wu and l.liao et al [ Advanced Materials 27,1547 (2015); advanced Materials 28,8302(2016)]Experiments have demonstrated that the self-heating effect results in SiO-based2Thin layer MoS of thin film gate dielectric2The FET exhibits a negative resistance phenomenon. Pop et al [ NanoLetters 17,3429(2017)]Found to be based on SiO2Thin layer MoS of gate dielectric2FETs operating at high current for several minutes are prone to device failure due to the temperature rise caused by the self-heating effect. Therefore, how to weaken the self-heating effect on the thin layer MoS2The impact of FET performance is a problem that is currently in need of resolution.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a gate dielectric based on an AlN thin film, a graphene source electrode, a graphene drain electrode and a thin MoS layer2A novel field effect transistor with a conductive channel and a method for manufacturing the same. Compared with the previous thin layer MoS2FET, the present invention has the following advantages of ① compared with conventional SiO2② compares the metal material, graphene is used as a source electrode and a drain electrode, and can effectively reduce the electrode and the thin-layer MoS2The contact resistance therebetween.
The invention is realized by the following technical scheme: a novel thin-layer molybdenum disulfide field effect transistor mainly comprises a source electrode, a drain electrode, a grid medium, a conducting channel and a metal bonding pad. The source electrode and the drain electrode are made of graphene (the thickness is less than 10nm), the gate electrode is a silicon substrate, the gate medium is an AlN thin film, and the conducting channel is a thin MoS layer2(thickness less than 25 nm). The field effect transistor is in a back gate structure.
The specific preparation process of the novel field effect transistor provided by the invention is as follows:
(1) preparing an AlN thin film with a certain thickness (less than 300nm) on the surface of a silicon substrate (with the resistivity less than 0.001 omega-cm, the crystal orientation of 100 and the doping type of n-type or p-type) by a thin film deposition process (magnetron sputtering or atomic layer deposition process), wherein the silicon substrate is used as a grid electrode, and the AlN thin film is used as a grid medium;
(2) preparing a metal pad (for example, Cr/Au of 10/70 nm) with a certain thickness on the surface of the AlN thin film through photoetching and metallization processes; the metal bonding pad is used for subsequent wire bonding (wire bonding) so as to test the electrical characteristics of the device;
(3) preparing graphene on a metal substrate (Cu or Ni foil) by adopting a chemical vapor deposition process; transferring the graphene on the metal substrate to the surface of the AlN thin film through a graphene transfer process; patterning the graphene on the surface of the AlN thin film by a graphene patterning process to be used as a source electrode and a drain electrode; covering the edge part of the metal welding disc by graphene;
(4) the graphene transfer process specifically comprises the following steps: firstly, a layer of polymethyl methacrylate (PMMA) film is coated on the surface of graphene in a spin mode, and then the film is soaked in FeCl3Or (NH)4)2S2O8Corroding the metal substrate in the solution to obtain a graphene/PMMA film suspended on the surface of the solution; fishing up the graphene/PMMA film suspended on the surface of the solution by using the AlN film, and carrying out proper heat treatment; the heat treatment temperature is 60-200 ℃, and the time is 40 minutes; and removing PMMA on the surface of the graphene by using acetone to finally obtain the AlN film with the surface covered with the graphene.
(5) The graphene patterning process specifically comprises the following steps: firstly, a layer of photoresist is coated on the surface of graphene in a spinning mode, the photoresist is patterned by utilizing a photoetching process, the photoresist is used as a mask, and the graphene with the required pattern is prepared by combining an etching process.
(6) Prepared on SiO by adopting a chemical vapor deposition or mechanical stripping process2Thin layer MoS of/Si substrate surface2And transferring the graphene to the surface of the AlN thin film through a fixed-point transfer process, and covering two ends of the graphene source electrode and the graphene drain electrode to be used as a conductive channel.
Drawings
Fig. 1 is a schematic view of the overall structure of the present invention. 1, a silicon substrate grid; 2, AlN thin film gate dielectric; 3,a graphene source electrode; 4, a graphene drain electrode; 5, thin layer MoS2A conductive channel; 6 and 7, metal pads.
Detailed Description
In order that the contents of the invention will be more clearly understood, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
A novel thin-layer molybdenum disulfide field effect transistor mainly comprises a grid electrode 1, a grid medium 2, a source electrode 3, a drain electrode 4, a conducting channel 5 and metal bonding pads 6 and 7. Wherein, the grid 1 is a silicon substrate, the grid medium 2 is an AlN thin film, the source electrode 3 and the drain electrode 4 are graphene, and the conducting channel is a thin MoS layer2. The specific preparation process comprises the following steps:
(1) preparing an AlN thin film with the thickness of 20nm on the surface of a silicon substrate (the resistivity is less than 0.001 omega cm, the crystal orientation is (100), the doping type is p-type) by an atomic layer deposition process to be used as a gate medium 2, and using the silicon substrate as a gate 1;
(2) preparing a Cr/Au laminated structure with the thickness of 10/70nm on the surface of the AlN thin film through photoetching and metallization processes to be used as metal bonding pads 6 and 7; the metal pads 6 and 7 are used for subsequent wire bonding so as to facilitate the electrical property test of the device;
(3) preparing graphene on the surface of the Cu foil by adopting a chemical vapor deposition process; transferring the graphene on the surface of the Cu foil to the surface of the AlN thin film through a graphene transfer process; patterning the graphene on the surface of the AlN thin film by a graphene patterning process to form a source electrode 3 and a drain electrode 4; graphene covers the edge portions of the metal pads 6 and 7;
(4) the graphene transfer process specifically comprises the following steps: firstly, spin-coating a layer of polymethyl methacrylate (PMMA) film on the surface of graphene, and then soaking the PMMA film in FeCl with the concentration of 1mol/L3Corroding the Cu foil in the solution to obtain a graphene/PMMA film suspended on the surface of the solution; suspending in FeCl by AlN film3Taking out the graphene/PMMA film on the surface of the solution, and carrying out appropriate heat treatment (the temperature is 110 ℃, and the time is 40 minutes); and removing PMMA on the surface of the graphene by using acetone to finally obtain the AlN film with the surface covered with the graphene.
(5) The graphene patterning process specifically comprises the following steps: firstly, a layer of photoresist is coated on the surface of graphene in a spinning mode, the photoresist is patterned by utilizing a photoetching process, the photoresist is used as a mask, and the graphene with the required pattern is prepared by combining an etching process.
(6) Will be prepared on SiO by chemical vapor deposition2Thin layer MoS of/Si substrate surface2And transferring the graphene to the surface of the AlN thin film through a fixed-point transfer process to cover two ends of the graphene source electrode 3 and the graphene drain electrode 4 to serve as a conductive channel 5.
It should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications, substitutions, combinations, and the like can be made without departing from the spirit and scope of the invention.
Claims (8)
1. Novel thin-layer MoS2The field effect transistor mainly comprises a source electrode, a drain electrode, a grid medium, a conductive channel and a metal bonding pad. The preparation method is characterized by comprising the following preparation steps:
a) preparing an AlN film with a certain thickness on the surface of the silicon substrate by a film deposition process, wherein the silicon substrate is used as a grid electrode, and the AlN film is used as a grid medium; the film deposition process is a magnetron sputtering or atomic layer deposition process;
b) preparing a metal pad on the surface of the AlN thin film through photoetching and metallization processes;
c) preparing graphene on a metal substrate by adopting a chemical vapor deposition process; the metal substrate is Cu or Ni foil; transferring the graphene on the metal substrate to the surface of the AlN thin film through a graphene transfer process; patterning the graphene on the surface of the AlN thin film by a graphene patterning process to be used as a source electrode and a drain electrode; covering the edge part of the metal welding disc by graphene;
d) prepared on SiO by adopting a chemical vapor deposition or mechanical stripping process2Thin layer MoS of/Si substrate surface2And transferring the graphene to the surface of the AlN thin film through a fixed-point transfer process, and covering two ends of the graphene source electrode and the graphene drain electrode to be used as a conductive channel.
2. According to claim1A novel thin layer MoS2The field effect transistor is characterized in that the resistivity of the silicon substrate is less than 0.001 omega cm, the crystal orientation is (100), and the doping type is n-type or p-type.
3. A novel thin-layered MoS according to claim 12The field effect transistor is characterized in that a source electrode and a drain electrode are made of graphene, and a conducting channel is a thin layer MoS2The gate dielectric is an AlN thin film, and the gate is a silicon substrate.
4. A novel thin-layered MoS according to claim 12A field effect transistor, wherein the graphene has a thickness of less than 10nm and a thin MoS layer2Is less than 25 nm.
5. A novel thin-layered MoS according to claim 12A field effect transistor, wherein the AlN thin film has a thickness of less than 300 nm.
6. A novel thin-layered MoS according to claim 12Field-effect transistor, characterized in that the device is of back-gate structure, i.e. thin MoS2The graphene source electrode and the graphene drain electrode are respectively positioned on the thin layer MoS2On both sides and in contact therewith.
7. A novel thin-layered MoS according to claim 12The field effect transistor is characterized in that the step of transferring the graphene to the surface of the AlN thin film specifically comprises the following steps: firstly, a layer of polymethyl methacrylate (PMMA) film is coated on the surface of a metal substrate/graphene in a spin mode, and then the PMMA film is soaked in FeCl3Or (NH)4)2S2O8Corroding the metal substrate in the solution to obtain a graphene/PMMA film suspended on the surface of the solution; fishing up the graphene/PMMA film suspended on the surface of the solution by using the AlN film, and carrying out proper heat treatment; the heat treatment temperature is 60-200 ℃, and the time is 40 minutes; removing graphene surface with acetoneFinally obtaining the AlN thin film with the surface covered with the graphene.
8. A novel thin-layered MoS according to claim 12The field effect transistor is characterized in that the graphene patterning process specifically comprises the following steps: firstly, a layer of photoresist is coated on the surface of graphene in a spinning mode, the photoresist is patterned by utilizing a photoetching process, the photoresist is used as a mask, and the graphene with the required pattern is prepared by combining an etching process.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113725360A (en) * | 2021-09-02 | 2021-11-30 | 中国人民解放军国防科技大学 | Thermal field transistor based on tantalum disulfide charge density wave phase change and preparation method thereof |
| CN114724956A (en) * | 2022-03-31 | 2022-07-08 | 浙江大学 | Chemical vapor deposition preparation method of monolayer molybdenum disulfide and application of monolayer molybdenum disulfide in thin film transistor |
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| CN107342345A (en) * | 2017-06-27 | 2017-11-10 | 重庆大学 | A kind of phototransistor based on ferroelectricity gate medium and thin layer molybdenum disulfide raceway groove |
| US20190131410A1 (en) * | 2017-10-27 | 2019-05-02 | Boe Technology Group Co., Ltd. | Thin film transistor, production method thereof, and electronic apparatus |
| CN110061063A (en) * | 2019-04-24 | 2019-07-26 | 中国科学院微电子研究所 | Field effect transistor tube preparation method and field effect transistor |
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| CN113725360A (en) * | 2021-09-02 | 2021-11-30 | 中国人民解放军国防科技大学 | Thermal field transistor based on tantalum disulfide charge density wave phase change and preparation method thereof |
| CN114724956A (en) * | 2022-03-31 | 2022-07-08 | 浙江大学 | Chemical vapor deposition preparation method of monolayer molybdenum disulfide and application of monolayer molybdenum disulfide in thin film transistor |
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