CN111725132A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN111725132A
CN111725132A CN202010619423.7A CN202010619423A CN111725132A CN 111725132 A CN111725132 A CN 111725132A CN 202010619423 A CN202010619423 A CN 202010619423A CN 111725132 A CN111725132 A CN 111725132A
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semiconductor device
semiconductor
package
manufacturing
device package
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侯新飞
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Ji Nannan Knows Information Technology Co ltd
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Ji Nannan Knows Information Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device is electrically connected to the active region of the chip by forming the through hole on the inclined side surface, so that the short path can be electrically connected to the substrate, the miniaturization packaging can be realized, and the transverse space is saved; and each chip has an encapsulating layer covering the active surface, which is formed by a thermoplastic material, can be made thinner, and can realize thermocompression bonding of a plurality of chips to form a package.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor device packaging, in particular to a semiconductor device and a manufacturing method thereof.
Background
As for semiconductor packages, multi-chip packages can be miniaturized, made multifunctional, and made low cost, but with increasing demands, thinning and multi-functionalization of multi-chip packages are required to be further improved, and it is a constant pursuit in the art how to realize a more compact package on the basis of a conventional silicon chip. US2011/079890a1 discloses a semiconductor package, which stacks a plurality of bare chips on a substrate in a staggered manner, and this arrangement saves a part of space in the transverse direction, but the staggered arrangement firstly brings instability of electrical connection, and the transverse direction still needs to occupy larger space, which is not beneficial for realizing a miniaturized package CN104332462A, which discloses a wafer level package unit with obliquely stacked chips, wherein a plurality of chips are obliquely placed on the substrate, and direct electrical connection is performed by using pads close to the substrate, the electrical connection path is shorter, but the lateral space utilization and the package stability are poorer.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, including the steps of:
(1) providing a wafer comprising a plurality of semiconductor dies, each of the semiconductor dies comprising an active region on an active side of the wafer and a peripheral region around the active region, the active region having at least one pad therein;
(2) forming a wiring layer on the active surface, the wiring layer extending from the active region to the peripheral region;
(3) forming an encapsulating layer covering the active surface by using a thermoplastic material;
(4) singulating along the cutting lines among the semiconductor bare chips to form a plurality of discrete semiconductor chips; the semiconductor chip comprises an upper surface, a lower surface, a first side surface and a second side surface which are opposite, wherein an included angle between the first side surface and the upper surface is an acute angle alpha, an included angle between the second side surface and the upper surface is an obtuse angle beta, and alpha + beta is 180 degrees;
(5) and drilling holes from the first side surface and filling conductive materials to form through holes electrically connected with the wiring layer, thereby forming the semiconductor device.
Wherein the thermoplastic material is EVA hot melt adhesive or modified epoxy resin.
Wherein alpha is more than or equal to 30 degrees and less than or equal to 45 degrees.
The present invention provides a semiconductor device formed by the above-described method of manufacturing a semiconductor device.
The invention also provides a manufacturing method of the semiconductor device packaging body, which comprises the following steps:
(1) providing a plurality of semiconductor devices, wherein the semiconductor devices are the semiconductor devices;
(2) sequentially attaching the first sides of the plurality of semiconductor devices to a carrier plate;
(3) utilizing a first mold and a second mold to carry out hot pressing on the plurality of semiconductor devices, so that the plurality of semiconductor devices are bonded together through the encapsulating layers between the plurality of semiconductor devices, and forming a semiconductor device packaging body;
the plurality of first sides of the plurality of semiconductor devices form a third side in a coplanar manner, and the plurality of second sides of the plurality of semiconductor devices form a fourth side in a coplanar manner.
The first die is provided with a first inclined surface, and the first inclined surface is attached to the lower surface of the semiconductor device at the tail end; the second die is provided with a second inclined surface, and the second inclined surface is attached to the upper surface of the semiconductor device at the head end; and wherein the hot pressing of the plurality of semiconductor devices with the first mold and the second mold specifically comprises: applying a force toward the plurality of semiconductor devices through the first mold and the second mold, respectively, and heating so that the plurality of semiconductor devices are bonded together with the encapsulating layer therebetween.
The invention provides a semiconductor device package formed by the manufacturing method of the semiconductor device package, which further comprises a first main surface formed by the upper surface of the head-most semiconductor device and a second main surface formed by the lower surface of the tail-most semiconductor device.
The invention also provides a manufacturing method of the semiconductor packaging structure, which comprises the following steps:
(1) providing a plurality of semiconductor device packages, wherein the semiconductor device packages are the semiconductor device packages;
(2) welding a plurality of semiconductor packages in a mode that the third side face is opposite to the packaging substrate, and bonding the plurality of semiconductor packages through an encapsulating layer;
(3) and filling a gap between the third side surface and the packaging substrate with an underfill agent, wherein the underfill agent further fills at least a gap between the second main surface of the tail-most semiconductor package and the packaging substrate.
The plurality of semiconductor device packages include a first semiconductor device package and a second semiconductor device package, and the first semiconductor device package and the second semiconductor device package are the same in size.
Wherein the plurality of semiconductor device packages include a third semiconductor device package and a fourth semiconductor device package, the third semiconductor device package and the fourth semiconductor device package being different in size.
The invention has the following advantages:
the semiconductor device is electrically connected to the active region of the chip by forming the through hole on the inclined side surface, so that the short path can be electrically connected to the substrate, the miniaturization packaging can be realized, and the transverse space is saved; and each chip has an encapsulating layer covering the active surface, which is formed by a thermoplastic material, can be made thinner, and can realize thermocompression bonding of a plurality of chips to form a package.
Drawings
FIG. 1 is a cross-sectional view of a wafer before dicing;
FIG. 2 is a cross-sectional view of a single semiconductor device;
FIG. 3 is a schematic view of a plurality of semiconductor devices being thermocompressively bonded;
fig. 4 is a cross-sectional view of a semiconductor device package;
FIG. 5 is a cross-sectional view of a semiconductor package;
fig. 6 is a cross-sectional view of another semiconductor package structure.
Detailed Description
The present technology will be described with reference to the drawings in the embodiments, which relate to a semiconductor device having a sloped side face with an electrically connected via structure. And to a semiconductor device package including a plurality of the semiconductor devices, and inclined side surfaces of the plurality of semiconductor devices are coplanar, and further, mounted on a package substrate such as a Printed Circuit Board (PCB) with the inclined side surfaces thereof and at an angle. The semiconductor device package includes a plurality of semiconductor devices inclined side by side, inclined surfaces of the semiconductor devices being formed coplanar as the inclined surfaces of the package. Wherein the semiconductor device can be formed by obliquely cutting two side surfaces of the semiconductor chip thereof, the two side surfaces having an oblique angle of non-right angle with respect to the upper and lower surfaces of the semiconductor chip. Then, a via hole is drilled in one of the inclined side surfaces for connection to the conductive bump.
The present techniques provide several advantages. The method of directly aligning the through-holes with the electrical connection portions of the package substrate for connection to the package substrate via the conductive bumps provides improved electrical connections and increased yield relative to wire-bonded semiconductor devices or laterally misaligned semiconductor devices. The semiconductor device is electrically connected to the active region of the chip by forming the through hole on the inclined side surface, so that the short path can be electrically connected to the substrate, the miniaturization packaging can be realized, and the transverse space is saved; and each chip has an encapsulating layer covering the active surface, which is formed by a thermoplastic material, can be made thinner, and can realize thermocompression bonding of a plurality of chips to form a package.
It will be understood that the present technology may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technology to those skilled in the art. Indeed, the technology is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the technology as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. It will be apparent, however, to one skilled in the art that the present technology may be practiced without these specific details.
The terms "top" and "bottom," upper "and" lower, "and" vertical "and" horizontal, "and their various forms, as used herein, are for purposes of illustration and description only and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Also, as used herein, the terms "substantially" and/or "about" mean that the specified dimensions or parameters may vary within acceptable manufacturing tolerances for a given application.
Referring first to fig. 1, a semiconductor wafer 1 may initially be an ingot of wafer material. In one example, the ingot forming the wafer 1 may be single crystal silicon grown according to a Czochralski (CZ) or Floating Zone (FZ) process. However, in other embodiments, the wafer 1 may be formed of other materials or by other processes.
The semiconductor wafer 1 may be diced from an ingot, may include a plurality of semiconductor die, and polished on both the active side and the back side opposite the active side to provide a smooth surface. The active surface may undergo different processing steps for forming a corresponding integrated circuit of the active area 2 on the active surface. These various processing steps may include metallization steps that deposit metal contacts for transferring signals to and from the integrated circuit. The electrical contacts may include die bond pads 3 exposed on the active surface. The number of bond pads 3 is shown simplified and each die may contain more die bond pads 3 than shown.
In embodiments, each die bond pad 3 may be rectangular, circular, or other shape, and may be equal or different in length and width. In an embodiment, die bond pads 3 may be formed of aluminum or alloys thereof, but in other embodiments bond pads 3 may be formed of other materials. In an embodiment, the integrated circuit may be implemented as a non-volatile NAND flash semiconductor die, although other types of integrated circuits are contemplated.
The die bond pads 3 may be spaced inward from the edges, which are disposed within the active region 2, away from the scribe street locations. In this embodiment, die bond pads 3 extend to the edge using routing layer 4, which routing layer 4 forms electrical traces that extend from die bond pads 3 to the edge. The wiring layer 4 electrically leads out the plurality of die bond pads 3 of each die onto the first side of the die.
And forming an encapsulating layer 5 covering the active surface by adopting a thermoplastic material, wherein the thermoplastic material is EVA hot melt adhesive or modified epoxy resin, the EVA hot melt adhesive or the modified epoxy resin has viscosity when being heated, and is solidified at normal temperature.
The back side of the wafer 1 is then subjected to a thinning process to thin the die from, for example, 700 microns to a range of about 100 to 500 microns. It is understood that in other embodiments, wafer 1 may be thinner or thicker than this range after the thinning step. In this embodiment, a layer of Die Attach Film (DAF) may be applied to the back side of the wafer 1.
Next, the semiconductor die (hereinafter referred to as a semiconductor chip) having the wiring layer 4 and the encapsulating layer 5 may be diced from the wafer 1. In one embodiment, the wafer 1 may be diced using a stealth laser process. The wafer 1 may be supported on a chuck or other support surface (not shown) with the back side facing the support surface and the active side facing away from the support surface. In other embodiments, the semiconductor chip can be cut by blade cutting or water jet cutting, see fig. 1, the cutting blade 7 is inclined at a certain angle and is along the cutting line 6, and the cutting line 6 also has a certain non-right angle with the active surface of the semiconductor bare chip.
Referring to fig. 2, the singulated and formed semiconductor chip 10 includes an upper surface 11 and a lower surface 12 which are opposite to each other, and a first side surface 13 and a second side surface 14 which are opposite to each other, wherein the first side surface 13 forms an acute angle α with the upper surface 11, the second side surface 14 forms an obtuse angle β with the upper surface 11, and α + β is 180 °, that is, the first side surface 13 and the second side surface 14 are parallel. Of course, the semiconductor chip 10 further includes two other opposite side surfaces, which may be side surfaces having a non-right angle, or vertical side surfaces having a right angle, and will not be described herein.
Referring again to fig. 2, the wiring layer 4 leads out both the die bond pads 3 to the outside of the active region 2, and neither the first side 13 nor the second side 14 passes through the active region 2. The included angle alpha between the first side surface 14 and the upper surface 11 is more than or equal to 30 degrees and less than or equal to 45 degrees, and the angle arrangement can facilitate the formation of the through hole 8 to be electrically connected to the wiring layer 4 without affecting the active region. Furthermore, in order to ensure that the formation of the through-holes 8 does not affect the active area, the substrate portion (i.e., the semiconductor die portion) of the semiconductor chip should at least have a thickness greater than 100 microns.
The through hole 8 is formed by drilling and filling a conductive material from the first side. The via 8 may be substantially perpendicular to the first side 13 and its bottom should separate the active region 2. The through holes 8 are arranged in an array on the first side 13. The semiconductor chip on which the through hole 8 is formed is the semiconductor device of the present invention.
Referring to fig. 3, a plurality of semiconductor devices formed by the above-described method are provided, which have the same structure and size, and although fig. 3 shows only 4 semiconductor devices, they may be more or 2, 3. A plurality of semiconductor devices are then arranged side by side in sequence on a carrier plate 100, which carrier plate 100 has a flat temporary bonding surface.
The carrier plate 100 is provided with a first mold 101 and a second mold 102 which are arranged oppositely, wherein the first mold 101 and the second mold 102 are both arranged on the temporary bonding surface of the carrier plate 100 and are provided with a first inclined surface and a second inclined surface which are arranged oppositely and are parallel. The first and second slopes match the upper and lower surfaces 11, 12.
Arranging a plurality of semiconductor devices on the carrier plate 100 side by side in sequence, including adhering a first side surface of a first semiconductor device 50 (the semiconductor device at the tail end) to a temporary bonding surface of the carrier plate 100, and leaning a lower surface of the first semiconductor device 50 on a first inclined surface; the first side of the second semiconductor device 40 is then attached to the temporary bonding surface of the carrier plate 100 and the lower surface of the second semiconductor device 40 is placed against the upper surface of the first semiconductor device 50. And so on until the last semiconductor device 20 (the first-most semiconductor device) rests on the second-to-last semiconductor device 30.
Then, the second bevel of the second mold 102 is press-fitted to the upper surface of the semiconductor device 20. A force toward the plurality of semiconductor devices is applied through the first mold 101 and the second mold 102, respectively, and heating is performed, so that the plurality of semiconductor devices are thermocompression bonded together with the encapsulating layer therebetween. Thereby forming a semiconductor device package 60, as can be seen in fig. 4.
Wherein the plurality of first sides of the plurality of semiconductor devices are coplanar to form a third side 63 and the plurality of second sides of the plurality of semiconductor devices are coplanar to form a fourth side 64. The semiconductor device package 60 further includes a first main surface 61 constituted by an upper surface of the head-most semiconductor device 20 and a second main surface 62 constituted by a lower surface of the tail-most semiconductor device 50.
Referring then to fig. 5, a semiconductor device package 60 may be soldered over the package substrate 15 by conductive bumps 16. Wherein the third side 63 of the semiconductor device package 60 faces the package substrate 15, and the plurality of through holes are electrically connected to the package substrate 15 through the conductive bumps 16, respectively.
The second main surface 62 of the semiconductor device package 60 and the package substrate 15 have a non-right angle of inclination, which is an acute angle.
Another semiconductor device package 70 may be additionally bonded for the necessity of integration. In this embodiment, the specific steps include: first irradiating the first main surface 61 of the semiconductor device package 70 with laser light to make the encapsulating layer on the first main surface 61 adhesive; the second major surface of the semiconductor device package 70 is then bonded to the first major surface 61 of the semiconductor device package 60 to form a common assembly of a plurality of semiconductor device packages.
In embodiments, the conductive bumps 16 may have a diameter of about 30 to 70 microns, and more particularly about 50 microns, while in other embodiments the diameter of the conductive bumps 120 may be greater or less than this value. In one embodiment, the conductive bumps may have a height between 20 and 35 microns, and more particularly about 25 microns, while in other embodiments the height of the conductive bumps 120 may be above or below this value. The conductive bumps 16 may be formed of gold or an alloy of gold, however in other embodiments they may be formed of other metals, such as copper or solder.
Referring to fig. 6, a semiconductor device package 80 of a different size from the semiconductor device package 60 may also be integrated. Although the semiconductor device package 80 is shown as having a height less than the semiconductor device package 60, it is understood that the semiconductor device package 80 may have a height greater than the semiconductor device package 60. Further, the width may be different in the lateral direction or the thickness may be different.
Finally, the method further includes filling a gap between the third side surface and the package substrate 15 with an underfill 17, and the underfill 17 further fills at least a gap between the second main surface of the rearmost semiconductor package and the package substrate 15 (i.e., the above-mentioned oblique angle position).
The underfill 17 prevents the semiconductor device package from falling, i.e., ensures stability and ensures that the semiconductor device package is inclined and stands on the package substrate 15. The underfill 17 may be a resin material, polyimide, or the like.
The semiconductor device is electrically connected to the active region of the chip by forming the through hole on the inclined side surface, so that the short path can be electrically connected to the substrate, the miniaturization packaging can be realized, and the transverse space is saved; and each chip has an encapsulating layer covering the active surface, which is formed by a thermoplastic material, can be made thinner, and can realize thermocompression bonding of a plurality of chips to form a package.
The foregoing detailed description of the technology has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the present technology is defined by the appended claims.
The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to the other example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising the steps of:
(1) providing a wafer comprising a plurality of semiconductor dies, each of the semiconductor dies comprising an active region on an active side of the wafer and a peripheral region around the active region, the active region having at least one pad therein;
(2) forming a wiring layer on the active surface, the wiring layer extending from the active region to the peripheral region;
(3) forming an encapsulating layer covering the active surface by using a thermoplastic material;
(4) singulating along the cutting lines among the semiconductor bare chips to form a plurality of discrete semiconductor chips; the semiconductor chip comprises an upper surface, a lower surface, a first side surface and a second side surface which are opposite, wherein an included angle between the first side surface and the upper surface is an acute angle alpha, an included angle between the second side surface and the upper surface is an obtuse angle beta, and alpha + beta is 180 degrees;
(5) and drilling holes from the first side surface and filling conductive materials to form through holes electrically connected with the wiring layer, thereby forming the semiconductor device.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: wherein the thermoplastic material is EVA hot melt adhesive or modified epoxy resin.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: wherein alpha is more than or equal to 30 degrees and less than or equal to 45 degrees.
4. A semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 1 to 3.
5. A method of manufacturing a semiconductor device package, comprising the steps of:
(1) providing a plurality of semiconductor devices, the semiconductor devices being the semiconductor device of claim 4;
(2) sequentially attaching the first sides of the plurality of semiconductor devices to a carrier plate;
(3) utilizing a first mold and a second mold to carry out hot pressing on the plurality of semiconductor devices, so that the plurality of semiconductor devices are bonded together through the encapsulating layers between the plurality of semiconductor devices, and forming a semiconductor device packaging body;
the plurality of first sides of the plurality of semiconductor devices form a third side in a coplanar manner, and the plurality of second sides of the plurality of semiconductor devices form a fourth side in a coplanar manner.
6. The method of manufacturing a semiconductor device package according to claim 1, wherein: the first die is provided with a first inclined surface, and the first inclined surface is attached to the lower surface of the semiconductor device at the tail end; the second die is provided with a second inclined surface, and the second inclined surface is attached to the upper surface of the semiconductor device at the head end; and wherein the hot pressing of the plurality of semiconductor devices with the first mold and the second mold specifically comprises: applying a force toward the plurality of semiconductor devices through the first mold and the second mold, respectively, and heating so that the plurality of semiconductor devices are bonded together with the encapsulating layer therebetween.
7. A semiconductor device package formed by the method of manufacturing a semiconductor device package according to claim 5 or 6, further comprising a first main face constituted by an upper face of a head-most semiconductor device and a second main face constituted by a lower face of a tail-most semiconductor device.
8. A manufacturing method of a semiconductor packaging structure comprises the following steps:
(1) providing a plurality of semiconductor device packages, the semiconductor device packages being the semiconductor device package of claim 7;
(2) welding a plurality of semiconductor packages in a mode that the third side face is opposite to the packaging substrate, and bonding the plurality of semiconductor packages through an encapsulating layer;
(3) and filling a gap between the third side surface and the packaging substrate with an underfill agent, wherein the underfill agent further fills at least a gap between the second main surface of the tail-most semiconductor package and the packaging substrate.
9. The semiconductor device according to claim 8, wherein: the plurality of semiconductor device packages include a first semiconductor device package and a second semiconductor device package, and the first semiconductor device package and the second semiconductor device package are the same in size.
10. The semiconductor device according to claim 8, wherein: the plurality of semiconductor device packages include a third semiconductor device package and a fourth semiconductor device package, which are different in size.
CN202010619423.7A 2020-07-01 2020-07-01 Semiconductor device and manufacturing method thereof Withdrawn CN111725132A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112435932A (en) * 2020-12-03 2021-03-02 山东砚鼎电子科技有限公司 Semiconductor packaging structure and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112435932A (en) * 2020-12-03 2021-03-02 山东砚鼎电子科技有限公司 Semiconductor packaging structure and manufacturing method thereof
CN112435932B (en) * 2020-12-03 2022-08-09 深圳卓斌电子有限公司 Semiconductor packaging structure and manufacturing method thereof

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Application publication date: 20200929