CN111725140B - Multi-chip package and manufacturing method thereof - Google Patents
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- CN111725140B CN111725140B CN202010616944.7A CN202010616944A CN111725140B CN 111725140 B CN111725140 B CN 111725140B CN 202010616944 A CN202010616944 A CN 202010616944A CN 111725140 B CN111725140 B CN 111725140B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
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Abstract
The invention provides a multi-chip package and a manufacturing method thereof. The multi-chip package is electrically connected to the active area of the chip by forming the through hole on the inclined side surface, so that the short path can be electrically connected to the substrate, the small package can be realized, and the transverse space is saved; and the other side surface of each chip can realize flexible interconnection between the chips, thereby ensuring the flexibility and high integration of multi-chip packaging.
Description
Technical Field
The invention relates to the field of semiconductor chip packaging, in particular to a multi-chip package and a manufacturing method thereof.
Background
As for semiconductor packages, multi-chip packages can be miniaturized, made multifunctional, and made low cost, but with increasing demands, thinning and multi-functionalization of multi-chip packages are required to be further improved, and it is a constant pursuit in the art how to realize a more compact package on the basis of a conventional silicon chip. US2011/079890a1 discloses a semiconductor package, which stacks a plurality of bare chips on a substrate in a staggered manner, and this arrangement saves a part of space in the transverse direction, but the staggered arrangement firstly brings instability of electrical connection, and the transverse direction still needs to occupy larger space, so that the miniaturization package is not realized, and CN104332462A discloses a wafer level packaging unit with obliquely stacked chips, which places a plurality of chips on the substrate in an inclined manner, and uses pads close to the substrate for direct electrical connection, and the electrical connection path is shorter, but the lateral space utilization and the packaging stability are poorer.
Disclosure of Invention
Based on solving the above problems, the present invention provides a method for manufacturing a multi-chip package, comprising the steps of:
(1) providing a plurality of identical semiconductor chips, wherein the cross section of each semiconductor chip is in an isosceles trapezoid shape and comprises an upper surface and a lower surface which are opposite, and a first side surface and a second side surface which are opposite and arranged between the upper surface and the lower surface, wherein the first side surface is provided with a first through hole, and the second side surface is provided with a second through hole; the upper surface is provided with a thermoplastic material layer, and the thermoplastic material layer is provided with an opening at the upper surface close to the second side;
(2) sequentially attaching the first side surfaces of the plurality of semiconductor chips to a carrier plate;
(3) hot-pressing the plurality of semiconductor chips by using the first die and the second die so that the plurality of semiconductor chips are bonded together through the thermoplastic material layer between the plurality of semiconductor chips to form a chip assembly;
the plurality of first side surfaces of the plurality of semiconductor chips form a third side surface in a coplanar manner, and the plurality of second side surfaces of the plurality of semiconductor chips and a part of the upper surfaces of the plurality of semiconductor chips form a saw-toothed structure.
Wherein, step (1) specifically includes: providing a wafer comprising a plurality of semiconductor die, each semiconductor die comprising an active area on an active side of the wafer and a peripheral area around the active area, the active area having at least two pads therein; forming a wiring layer on the active surface, the wiring layer extending from the active region to the peripheral region, the wiring layer including a first portion extending to the first side surface and a second portion extending to the second side surface, wherein the opening exposes at least a portion of the second portion; depositing a layer of thermoplastic material on the active surface; singulating along the cutting lines among the semiconductor bare cores to form a plurality of discrete semiconductor chips; wherein the included angles between the first side surface and the upper surface and the included angles between the second side surface and the upper surface are both acute angles A, and A is more than or equal to 30 degrees and less than or equal to 45 degrees.
Wherein, after the performing of the monomerization, further comprising: a first via and a second via electrically connecting the first portion and the second portion, respectively, are formed by drilling holes from the first side and the second side and filling with a conductive material.
In the step (3), the first mold has a first inclined surface, and the first inclined surface is attached to the lower surface of the semiconductor chip at the tail end; the second die is provided with a second inclined surface, and the second inclined surface is attached to the upper surface of the head-most semiconductor chip; and wherein the hot-pressing of the plurality of semiconductor chips with the first mold and the second mold specifically comprises: applying a force toward the plurality of semiconductor chips through the first mold and the second mold, respectively, and heating so that the plurality of semiconductor chips are bonded together with the thermoplastic material layer therebetween.
Wherein the saw-tooth like structure comprises a plurality of triangular recesses, the manufacturing method further comprising the step (4): filling a conductive material in the recess so that the second via of the adjacent semiconductor chip is electrically connected with the second portion.
Wherein, still include step (5): welding the multi-chip assembly in a manner that the third side face is opposite to the packaging substrate; and then filling a gap between the third side surface and the packaging substrate with an underfill agent, wherein the underfill agent also fills at least between the lower surface of the tail-most semiconductor chip and the packaging substrate.
And the other chips are arranged between the lower surface of the tail-most semiconductor chip and the packaging substrate, and the chip is wrapped by the underfill.
Wherein, still including providing two the multi-chip assembly makes up: firstly, filling a conductive material in the openings of the two multi-chip assemblies to form a third through hole; then, arranging the two multi-chip assemblies in a centrosymmetric manner, and arranging the sawtooth structures of the two multi-chip assemblies in opposite directions; and finally, mutually clamping the sawtooth structures of the two multi-chip assemblies, so that the second through holes of the two multi-chip assemblies are mutually in physical and electrical contact, and the third through holes are mutually in physical and electrical contact.
The invention also provides a multi-chip package which is formed by the manufacturing method of the multi-chip package.
The invention has the following advantages:
the multi-chip package is electrically connected to the active area of the chip by forming the through hole on the inclined side surface, so that the short path can be electrically connected to the substrate, the small package can be realized, and the transverse space is saved; and the other side surface of each chip can realize flexible interconnection between the chips, thereby ensuring the flexibility and high integration of multi-chip packaging.
Drawings
FIG. 1 is a cross-sectional view of a wafer before dicing;
FIG. 2 is a cross-sectional view of a single semiconductor chip;
FIG. 3 is a schematic view of a plurality of semiconductor chips being thermocompression bonded;
FIG. 4 is a cross-sectional view of a multi-chip assembly;
FIG. 5 is a cross-sectional view of a multi-chip package;
FIG. 6 is a schematic process diagram of another multi-chip package;
fig. 7 is a cross-sectional view of another multi-chip package.
Detailed Description
The present technology will be described with reference to the drawings in the embodiments, which relate to a multi-chip package including a plurality of semiconductor chips having an inverted trapezoidal shape with both inclined side surfaces thereof having externally connected through-holes, and the inclined side surfaces of the plurality of semiconductor chips being coplanar, and further, mounted on a package substrate such as a Printed Circuit Board (PCB) with the inclined side surfaces thereof and at an angle.
The present techniques provide several advantages. The method of directly aligning the through-holes to the electrical connection portions of the package substrate for connection to the package substrate through the conductive bumps provides improved electrical connections and increased yield relative to wire-bonded semiconductor chips or laterally misaligned semiconductor chips. The multi-chip package is electrically connected to the active area of the chip by forming the through hole on the inclined side surface, so that the short path can be electrically connected to the substrate, the small package can be realized, and the transverse space is saved; and each chip has a thermoplastic material layer covering the active surface, can be made thinner, and can realize the hot-press bonding of a plurality of chips to form a package. In addition, the other side surface of each semiconductor chip can realize flexible interconnection of the chips, and the flexibility and high integration of multi-chip packaging are ensured.
It will be understood that the present technology may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technology to those skilled in the art. Indeed, the technology is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the technology as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. It will be apparent, however, to one skilled in the art that the present technology may be practiced without these specific details.
The terms "top" and "bottom," upper "and" lower, "and" vertical "and" horizontal, "and their various forms, as used herein, are for purposes of illustration and description only and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Also, as used herein, the terms "substantially" and/or "about" mean that the specified dimensions or parameters may vary within acceptable manufacturing tolerances for a given application.
Referring first to fig. 1, a semiconductor wafer 1 may initially be an ingot of wafer material. In one example, the ingot forming the wafer 1 may be single crystal silicon grown according to a Czochralski (CZ) or Floating Zone (FZ) process. However, in other embodiments, the wafer 1 may be formed of other materials or by other processes, such as silicon germanium, GaN, and the like.
The semiconductor wafer 1 may be diced from an ingot, may include a plurality of semiconductor die, and is polished on both an active surface and a back surface opposite the active surface to provide a smooth surface. The active surface may undergo different processing steps to form a corresponding integrated circuit of the active area 2 on the active surface. These various processing steps may include metallization steps that deposit metal contacts for transferring signals to and from the integrated circuit. The electrical contacts may include die bond pads 3 exposed on the active surface. The number of bond pads 3 is shown simplified and each die may contain more die bond pads 3 than shown.
In embodiments, each die bond pad 3 may be rectangular, circular, or other shape, and may be equal or different in length and width. In an embodiment, die bond pads 3 may be formed of aluminum or alloys thereof, but in other embodiments bond pads 3 may be formed of other materials. In an embodiment, the integrated circuit may be implemented as a non-volatile NAND flash semiconductor die, although other types of integrated circuits are contemplated.
The die bond pads 3 may be spaced inward from the edges, which are disposed within the active region 2, away from the scribe street locations. In the present embodiment, die bond pad 3 extends to the edge using a routing layer that includes a first portion 4 and a second portion 5, wherein the routing layer is formed as an electrical trace that extends from die bond pad 3 to the edge. The first portion 4 electrically leads a portion of the plurality of die bond pads 3 of each die to a first side 23 of the die, and the second portion 5 electrically leads the remainder of the plurality of die bond pads 3 of each die to a first side 24 of the die.
A layer 6 of thermoplastic material is deposited overlying the active surface, this layer being an EVA hot melt adhesive, a modified epoxy resin, which is tacky when heated and cures at ambient temperature. The layer 6 of thermoplastic material has an opening 7, said opening 7 exposing the second portion 5, the opening 7 being arranged to facilitate subsequent electrical connection.
The back side of the wafer 1 is then subjected to a thinning process to thin the die from, for example, 700 microns to a range of about 100 to 500 microns. It is understood that in other embodiments, wafer 1 may be thinner or thicker than this range after the thinning step. In this embodiment, a layer of Die Attach Film (DAF) may be applied to the back side of the wafer 1.
Next, the semiconductor die (hereinafter referred to as semiconductor chip) with the wiring layer and the thermoplastic material layer 6 may be diced from the wafer 1. In one embodiment, the wafer 1 may be diced using a stealth laser process. The wafer 1 may be supported on a chuck or other support surface (not shown) with the back side facing the support surface and the active side facing away from the support surface. In other embodiments, the semiconductor chip can be cut by blade cutting or water jet cutting, see fig. 1, the cutting blade is inclined at a certain angle and is along a cutting line 8, and the cutting line 8 also has a certain non-right angle a with the active surface of the semiconductor bare chip.
Referring to fig. 2, the discrete semiconductor chips formed after dicing include opposing upper and lower surfaces 21 and 22 and opposing first and second sides 23 and 24, the cross-section of which has the shape of an inverted isosceles trapezoid. Wherein the first side surface 23 and the second side surface 24 both form an acute angle a with the upper surface 21. Of course, the semiconductor chip further includes two other opposite side surfaces, which may also be side surfaces having a non-right angle included angle, or vertical side surfaces having a right angle, and will not be described herein too much.
Referring again to fig. 2, the first portion 4 of the routing layer leads a portion of the die bond pads 3 out of the active area 2 to a side near the first side 23, the second portion 5 leads the remaining portion of the die bond pads 3 out of the active area 2 to a side near the second side 24, and neither the first side 23 nor the second side 24 passes through the active area 2. Wherein the included angle a between the first side 23 and the second side 24 and the upper surface 21 is 30 ° ≦ a ≦ 45 °, and the angle arrangement may facilitate forming the first via 13 and the second via 14 to be electrically connected to the first portion 4 and the second portion 5 of the wiring layer, respectively, without affecting the active region 2. In addition, in order to ensure that the formation of the first via 13 and the second via 14 does not affect the active region 2, the substrate portion (i.e., the semiconductor die portion) of the semiconductor chip should have a thickness of at least greater than 100 microns.
The first and second through holes 13 and 14 are formed by drilling holes from the first and second side surfaces 23 and 24 and filling them with a conductive material. The first and second through holes 13 and 14 may be substantially perpendicular to the first and second lateral surfaces 23 and 24, or may not be perpendicular to the first and second lateral surfaces 23 and 24, and the bottom thereof should be spaced from the active region 2. The first through holes 13 and the second through holes 14 are plural and arranged in an array on the first side surfaces 23 and 24.
Referring to fig. 3, a plurality of semiconductor chips formed by the above-described method are provided, which have the same structure and size, and although fig. 3 shows only 4 semiconductor chips, they may be more or 2, 3. A plurality of semiconductor chips are then arranged side by side in sequence on a carrier board 100, which carrier board 100 has a flat temporary bonding surface.
The carrier plate 100 is provided with a first mold 101 and a second mold 102 which are arranged oppositely, wherein the first mold 101 and the second mold 102 are both arranged on the temporary bonding surface of the carrier plate 100 and are provided with a first inclined surface and a second inclined surface which are arranged oppositely and are parallel. The first and second slopes match the upper and lower surfaces 11, 12.
Arranging a plurality of semiconductor chips on the carrier plate 100 side by side in sequence, wherein a first side surface of a first semiconductor chip (the semiconductor chip at the tail end) is attached to the temporary bonding surface of the carrier plate 100, and the lower surface of the first semiconductor chip is leaned against a first inclined surface; then, the first side of the second semiconductor chip is attached to the temporary bonding surface of the carrier 100, and the lower surface of the second semiconductor chip is leaned against the upper surface of the first semiconductor chip. And so on until the last semiconductor chip (the first semiconductor chip) leans on the second to last semiconductor chip.
Then, the second bevel of the second mold 102 is pressed onto the upper surface of the last semiconductor chip. A force is applied to the plurality of semiconductor chips by the first mold 101 and the second mold 102, respectively, and heating is performed so that the plurality of semiconductor chips are thermocompression bonded together with the thermoplastic material layer therebetween. Thereby forming a multi-chip package 30, see fig. 4.
The first sides of the semiconductor chips are coplanar to form a third side 33, and the second sides of the semiconductor chips and a part of the upper surfaces of the semiconductor chips form a saw-tooth structure. The multi-chip package further comprises a first main face 31 constituted by the upper surface of the foremost semiconductor chip and a second main face 32 constituted by the lower surface of the rearmost semiconductor chip. And the included angle between the first main surface 31 and the third side surface of the multi-chip package is a.
Referring then to fig. 5, the multi-chip package 30 may be soldered over the package substrate 40 by conductive bumps 41. Wherein the third side 33 of the multi-chip package faces the package substrate 40, and the first and second vias are electrically connected to the package substrate 40 through the conductive bumps 41, respectively.
The second main surface 32 of the multi-chip package 30 and the package substrate 40 have a non-right angle of inclination, which is an acute angle a.
The saw-toothed structure includes a plurality of triangular notches S, each of which exposes the second through-holes and the openings of the adjacent two semiconductor chips. The recess S has a triangular cross-section defined by second side surfaces of the semiconductor chips and a portion of an upper surface of the semiconductor chips.
Next, the recess S is filled with a conductive material 44 so that the second through hole of the adjacent semiconductor chip is electrically connected to the second portion. The leftmost semiconductor chip is led out to the package substrate 40 through the solder balls 47 and the bonding wires 48, respectively, and the rightmost semiconductor chip is led out to the package substrate 40 through the solder balls 45 and the bonding wires 48, respectively. In the present embodiment, the conductive material 44 may be solder.
In addition, other chips, such as chip 42, may also be integrated on the package substrate 40. The chip 42 is flip-chip mounted on the package substrate 40 via solder balls 43, but may be wire bonded. The chip 42 is disposed between the second main surface 32 of the chip assembly 30 and the package substrate 40, so that the lateral space size can be reduced.
Finally, the method further includes filling a gap between the third side surface and the package substrate 40 with an underfill 49, where the underfill 49 further fills at least a gap between the second main surface 32 of the tail-most semiconductor package and the package substrate 40, and completely encapsulates the chip 42.
The underfill 49 prevents the multi-chip assembly from falling, ensures stability, and ensures that the multi-chip assembly is obliquely erected on the package substrate 40. The underfill 49 may be a resin material, polyimide, or the like.
Two multichip assemblies may be combined for integration purposes, see fig. 6-7 in particular. First and second multi-chip assemblies 60 and 70 are formed by the above-described method and have the same structure and size. Wherein the opening of the first multi-chip assembly 60 is filled with a conductive material to form a third via 61 and the opening of the second multi-chip assembly 70 is filled with a conductive material to form a fourth via 71.
Then, the first multi-chip assembly 60 and the second multi-chip assembly 70 are arranged in a centrosymmetric manner, and the sawtooth structures of the first multi-chip assembly and the second multi-chip assembly are arranged in an opposite manner; finally, the saw-tooth structures of the two multi-chip assemblies are engaged with each other, wherein the notches S1 of the first multi-chip assembly 60 and the notches S2 of the second multi-chip assembly 70 are respectively inserted by the acute angles a of the plurality of semiconductor chips, so that the second through holes 62 and 72 of the two multi-chip assemblies 60 and 70 are in physical and electrical contact with each other and the third through hole 61 and the fourth through hole 71 are in physical and electrical contact with each other.
In this embodiment, the positions of the third through hole 61 and the fourth through hole 71 should be corresponding, and a solder layer (not shown) should be disposed therebetween to ensure the reliability of the bonding. And the layers of thermoplastic material of first multi-chip assembly 60 and second multi-chip assembly 70 may ensure the reliability of the bonding. The chip packaging structure has the advantages that the longitudinal space is greatly utilized, the flexible electric connection characteristic is realized, gaps are hardly formed between the chips, the structure is compact, and the chip packaging structure is favorable for small-size packaging.
According to the above method, the invention further provides a multi-chip package structure manufactured by the above method, which can be specifically referred to fig. 4, 5 and 7, and details are not repeated herein.
In conclusion, the multi-chip package of the invention is electrically connected to the active area of the chip by forming the through hole on the inclined side surface, so that the short path is electrically connected to the substrate, the miniaturization package is realized, and the transverse space is saved; and the other side surface of each chip can realize flexible interconnection between the chips, thereby ensuring the flexibility and high integration of multi-chip packaging.
The foregoing detailed description of the technology has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the present technology is defined by the appended claims.
The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to the other example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.
Claims (7)
1. A method of manufacturing a multi-chip package, comprising the steps of:
(1) providing a plurality of identical semiconductor chips, wherein the cross section of each semiconductor chip is in an isosceles trapezoid shape and comprises an upper surface and a lower surface which are opposite, and a first side surface and a second side surface which are opposite and arranged between the upper surface and the lower surface, wherein the first side surface is provided with a first through hole, and the second side surface is provided with a second through hole; the upper surface is provided with a thermoplastic material layer, and the thermoplastic material layer is provided with an opening at the upper surface close to the second side;
(2) sequentially attaching the first side surfaces of the plurality of semiconductor chips to a carrier plate;
(3) hot-pressing the plurality of semiconductor devices with a first mold and a second mold so that the plurality of semiconductor devices are bonded together with the thermoplastic material layer therebetween to form a multi-chip assembly; the plurality of first side surfaces of the plurality of semiconductor chips form a third side surface in a coplanar manner, and the plurality of second side surfaces of the plurality of semiconductor chips and a part of the upper surfaces of the plurality of semiconductor chips form a saw-toothed structure;
wherein, the step (1) specifically comprises the following steps: providing a wafer comprising a plurality of semiconductor die, each semiconductor die comprising an active area on an active side of the wafer and a peripheral area around the active area, the active area having at least two pads therein; forming a wiring layer on the active surface, the wiring layer extending from the active region to the peripheral region, the wiring layer including a first portion extending to the first side surface and a second portion extending to the second side surface, wherein the opening exposes at least a portion of the second portion; depositing a layer of thermoplastic material on the active surface; singulating along the cutting lines among the semiconductor bare cores to form a plurality of discrete semiconductor chips; wherein the included angles between the first side surface and the upper surface and the included angles between the second side surface and the upper surface are acute angles A, and A is more than or equal to 30 degrees and less than or equal to 45 degrees;
and, after the performing of the monomerization, further comprising: a first via and a second via electrically connecting the first portion and the second portion, respectively, are formed by drilling holes from the first side and the second side and filling with a conductive material.
2. The method of manufacturing a multi-chip package of claim 1, wherein:
in the step (3), the first die has a first inclined surface, and the first inclined surface is attached to the lower surface of the semiconductor chip at the tail end; the second die is provided with a second inclined surface, and the second inclined surface is attached to the upper surface of the head-most semiconductor chip; and wherein the hot pressing of the plurality of semiconductor devices with the first mold and the second mold specifically comprises: applying a force toward the plurality of semiconductor chips through the first mold and the second mold, respectively, and heating so that the plurality of semiconductor chips are bonded together with the thermoplastic material layer therebetween.
3. The method of manufacturing a multi-chip package according to claim 2, wherein:
the saw-tooth structure comprises a plurality of triangular recesses, and the manufacturing method further comprises the step (4): filling a conductive material in the recess so that the second via of the adjacent semiconductor chip is electrically connected with the second portion.
4. The method of manufacturing a multi-chip package of claim 3, wherein:
further comprising the step (5): welding the multi-chip assembly in a manner that the third side face is opposite to the packaging substrate; and then filling a gap between the third side surface and the packaging substrate with an underfill agent, wherein the underfill agent also fills at least between the lower surface of the tail-most semiconductor chip and the packaging substrate.
5. The method of manufacturing a multi-chip package according to claim 4, wherein:
and other chips are arranged between the lower surface of the semiconductor chip at the tail end and the packaging substrate, and the other chips are wrapped by the underfill.
6. The method of manufacturing a multi-chip package according to claim 2, wherein:
further comprising providing two of said multi-chip assemblies in combination: firstly, filling a conductive material in the openings of the two multi-chip assemblies to form a third through hole; then, arranging the two multi-chip assemblies in a centrosymmetric manner, and arranging the sawtooth structures of the two multi-chip assemblies in opposite directions; and finally, mutually clamping the sawtooth structures of the two multi-chip assemblies so as to enable the second through holes of the two multi-chip assemblies to be mutually in physical and electrical contact and the third through holes to be mutually in physical and electrical contact.
7. A multi-chip package formed by the method of manufacturing a multi-chip package of any of claims 1-6.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990066529A (en) * | 1998-01-30 | 1999-08-16 | 구본준 | Chip size package and its manufacturing method |
| CN1913149A (en) * | 2005-05-11 | 2007-02-14 | 英飞凌科技股份公司 | Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device |
| CN101553923A (en) * | 2006-10-10 | 2009-10-07 | 泰塞拉公司 | Edge connect wafer level stacking |
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| US8513789B2 (en) * | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
| KR100997787B1 (en) * | 2008-06-30 | 2010-12-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package and method of manufacturing the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990066529A (en) * | 1998-01-30 | 1999-08-16 | 구본준 | Chip size package and its manufacturing method |
| CN1913149A (en) * | 2005-05-11 | 2007-02-14 | 英飞凌科技股份公司 | Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device |
| CN101553923A (en) * | 2006-10-10 | 2009-10-07 | 泰塞拉公司 | Edge connect wafer level stacking |
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