CN111723041A - Redundancy computer interface unit, redundancy control computer and data transmission method - Google Patents
Redundancy computer interface unit, redundancy control computer and data transmission method Download PDFInfo
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- CN111723041A CN111723041A CN202010590892.0A CN202010590892A CN111723041A CN 111723041 A CN111723041 A CN 111723041A CN 202010590892 A CN202010590892 A CN 202010590892A CN 111723041 A CN111723041 A CN 111723041A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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Abstract
The embodiment of the invention provides a redundancy computer interface unit, a redundancy control computer and a data transmission method, wherein the redundancy computer interface unit comprises an FPGA chip and a driving circuit, and the FPGA chip comprises an SPI (serial peripheral interface) sending controller and an SPI receiving controller; the SPI sending controller is used for sending the first clock signal and the first data signal to the driving circuit; the driving circuit is used for converting the first clock signal into a first clock differential signal, converting the first data signal into a first data differential signal, and sending the first clock differential signal and the first data differential signal to other redundancy computer interface units; and receiving a second clock differential signal and a second data differential signal sent by other redundancy computer interface units, converting the second clock differential signal into a second clock signal, and converting the second data differential signal into a second data signal. The embodiment of the invention can improve the data transmission speed among a plurality of redundant computer interface units.
Description
Technical Field
The invention relates to the technical field of computer science, in particular to a redundancy computer interface unit, a redundancy control computer and a data transmission method.
Background
The redundancy control computer can be used in the unmanned aerial vehicle to control the start and stop, the flying speed and the like of the unmanned aerial vehicle. The redundancy control computer may include a plurality of redundancy computer interface units, and the redundancy computer interface units are in communication connection with each other.
In order to improve the control accuracy of the unmanned aerial vehicle, after the flight data and the calculation result data of the unmanned aerial vehicle are acquired, the acquired data of each redundancy computer interface unit in the redundancy control computer are generally required to be transmitted to other redundancy computer interface units, so that monitoring and voting algorithms are performed. In the prior art, a data transmission method between every two redundant computer interface units is usually an asynchronous serial port transmission mode.
Although the data transmission method adopted in the prior art is simple and easy to implement, the transmission speed of the data transmission method is usually not more than 1Mbps (Million bits per second), while the redundancy control computer needs to transmit a large amount of acquired flight data and calculation result data in each period, the data amount is usually several hundred bytes, the processing period is usually 10-20 ms, and in each processing period, besides the transmission data, a large amount of calculation and control tasks are provided, that is, the time for transmitting the data is less than 10-20 ms in each processing period. However, in the prior art, the transmission speed of data among the interface units of the redundancy computer is low, so that the data transmission delay is large, and the control performance of the redundancy control computer is further influenced.
Disclosure of Invention
An embodiment of the invention provides a redundancy computer interface unit, a redundancy control computer and a data transmission method, so as to improve the data transmission speed among a plurality of redundancy computer interface units.
The specific technical scheme is as follows:
in a first aspect, an embodiment of the present invention provides a redundancy computer interface unit, where the redundancy computer interface unit includes: an FPGA (Field Programmable Gate Array) chip and a driving circuit, wherein the FPGA chip includes: an SPI (Serial Peripheral Interface) transmission controller and an SPI reception controller;
the redundancy computer interface unit includes: the FPGA chip comprises: a serial peripheral interface SPI sending controller and an SPI receiving controller;
the SPI transmission controller is used for generating a first clock signal, acquiring first data to be transmitted, converting the first data to be transmitted into a first data signal, and transmitting the first clock signal and the first data signal to the driving circuit;
the driving circuit is configured to receive the first clock signal and the first data signal, convert the first clock signal into a first clock differential signal, convert the first data signal into a first data differential signal, and send the first clock differential signal and the first data differential signal to other redundancy computer interface units; receiving a second clock differential signal and a second data differential signal sent by a driving circuit of other redundancy computer interface units, converting the second clock differential signal into a second clock signal, converting the second data differential signal into a second data signal, and sending the second clock signal and the second data signal to the SPI receiving controller;
the SPI receiving controller is configured to receive the second clock signal and the second data signal.
Optionally, the driving circuit comprises: a driver.
Optionally, the driving circuit comprises: a transmission driver and a reception driver;
the transmission driver is configured to receive the first clock signal and the first data signal, convert the first clock signal into a first clock differential signal, convert the first data signal into a first data differential signal, and transmit the first clock differential signal and the first data differential signal to other redundancy computer interface units;
the receiving driver is used for receiving a second clock differential signal and a second data differential signal which are sent by sending drivers of other redundancy computer interface units, converting the second clock differential signal into a second clock signal, converting the second data differential signal into a second data signal, and sending the second clock signal and the second data signal to the SPI receiving controller.
Optionally, the number of the sending drivers is the same as the number of the other redundancy computer interface units, and the number of the receiving drivers is the same as the number of the other redundancy computer interface units.
Optionally, the driving circuit is a low voltage differential signaling LVDS driver, converts the first clock signal into a first clock differential signal, and converts the first data signal into a first data differential signal, and includes:
converting the first clock signal into a first clock LVDS and the first data signal into a first data LVDS;
the converting the second clock differential signal into a second clock signal and the converting the second data differential signal into a second data signal, where the converting the second clock differential signal into the second clock signal is a second clock LVDS, and the converting the second clock differential signal into the second data signal includes:
the second clock LVDS is converted into the second clock signal, and the second data LVDS is converted into the second data signal.
In a second aspect, an embodiment of the present invention provides a redundancy control computer, including: a plurality of the redundancy computer interface units described in any of the above, the driving circuit of each of the redundancy computer interface units being in communication connection with the driving circuits of other redundancy computer interface units in the redundancy control computer, respectively.
In a third aspect, an embodiment of the present invention provides a data transmission method, which is applied to the redundancy control computer described above, where the method includes:
a first SPI (serial peripheral interface) sending controller in a first redundancy computer interface unit in a redundancy control computer generates a first clock signal, acquires first data to be sent, converts the first data to be sent into a first data signal, and sends the first clock signal and the first data signal to a first driving circuit of the first redundancy computer interface unit;
the first driving circuit receives the first clock signal and the first data signal, converts the first clock signal into a first clock differential signal, converts the first data signal into a first data differential signal, and sends the first clock differential signal and the first data differential signal to a second redundancy computer interface unit;
the first driving circuit of the first redundancy computer interface unit receives a second clock differential signal and a second data differential signal sent by a second driving circuit of the second redundancy computer interface unit, converts the second clock differential signal into a second clock signal, converts the second data differential signal into a second data signal, and sends the second clock signal and the second data signal to the first SPI receiving controller;
the first SPI receiving controller receives the second clock signal and the second data signal.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a redundancy computer interface unit, a redundancy control computer and a data transmission method, wherein the redundancy computer interface unit comprises: FPGA chip and drive circuit, include in the FPGA chip: an SPI sending controller and an SPI receiving controller; the redundancy computer interface unit can acquire first data to be transmitted through the SPI transmission controller, convert the first data to be transmitted into a first data signal, transmit a first clock signal and the first data signal to the driving circuit, the driving circuit can convert the first clock signal into a first clock differential signal, convert the first data signal into a first data differential signal, and transmit the first clock differential signal and the first data differential signal to other redundancy computer interface units. The redundancy computer interface unit can also receive a second clock differential signal and a second data differential signal sent by other redundancy computer interface units. The data transmission between the redundancy computer interface unit and other redundancy computer interface units provided by the embodiment of the invention adopts an SPI synchronous transmission method, and the redundancy computer interface unit can receive the second data differential signal according to the receiving frequency of the second clock differential signal.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a redundancy computer interface unit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another structure of an interface unit of a redundancy computer according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an exemplary configuration of a redundancy control computer according to an embodiment of the present invention;
FIG. 4 is an interaction diagram illustrating a data transmission method of the redundancy control computer shown in FIG. 3;
FIG. 5 is a diagram illustrating another exemplary configuration of a redundancy control computer according to an embodiment of the present invention;
fig. 6 is an interaction diagram illustrating a data transmission method of the redundancy control computer shown in fig. 5.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a redundancy computer interface unit, where the redundancy computer interface unit includes: FPGA chip 101 and drive circuit 102, FPGA chip 101 includes: SPI transmission controller 104 and SPI reception controller 105. The SPI sending controller 104 and the SPI receiving controller 105 in the FPGA chip 101 are respectively in communication connection with the driving circuit 102.
The FPGA chip 101 is a semi-custom circuit in an asic that is a programmable logic array. The SPI represents a serial peripheral interface, and is a synchronous communication bus, and the FPGA chip 101 includes an SPI sending controller 104 and an SPI receiving controller 105, so that synchronous transmission of data between the redundancy computer interface unit and other redundancy computer interface units can be realized.
The SPI transmission controller 104 is configured to generate a first clock signal, acquire first data to be transmitted, convert the first data to be transmitted into a first data signal, and transmit the first clock signal and the first data signal to the driving circuit 102.
The SPI transmission controller 104 may generate the first clock signal according to a certain frequency, and transmit the first clock signal, where the frequency may be a preset value, and the higher the generation and transmission frequency of the clock signal is, the faster the data transmission speed is. However, if the generation and transmission frequency of the clock exceeds a certain value, transmission delay and transmission jitter may be generated in the transmission process of the first data to be transmitted, and thus the quality of signals received by other redundancy computer interface units is low, that is, other redundancy computer interface units cannot receive correct signals, so that the preset value can be determined according to experiments and actual requirements, and on the premise of ensuring that the transmission speed is increased as much as possible, correct reception of signals by other redundancy computer interface units is not affected.
The SPI transmission controller 104 may acquire the first data to be transmitted, which may be the flight data of the target flight device, and the calculated result data. The flight data may include: flight speed, flight altitude, flight direction, flight acceleration and the like.
After the first data to be transmitted is obtained, the first data to be transmitted may be converted into a first data signal, and the first data signal and a first clock signal are transmitted to the driving circuit 102, and the SPI transmission controller 104 may transmit the first clock signal at the generation frequency of the first clock signal, that is, generate a first clock signal to transmit the first clock signal to the driving circuit 102. The SPI transmission controller 104 may transmit the first data signal to the driving circuit 102 a plurality of times according to a preset data amount when transmitting the first data signal, and transmit the first data signal of a preset data amount every time a first clock signal is transmitted.
The driving circuit 102 is configured to receive a first clock signal and a first data signal, convert the first clock signal into a first clock differential signal, convert the first data signal into a first data differential signal, and send the first clock differential signal and the first data differential signal to other redundancy computer interface units; receiving a second clock differential signal and a second data differential signal sent by the driving circuit 102 of the other redundancy computer interface unit, converting the second clock differential signal into a second clock signal, converting the second data differential signal into a second data signal, and sending the second clock signal and the second data signal to the SPI receiving controller 105.
The driving circuit 102 may convert the first clock signal into a first clock differential signal and the first data signal into a first data differential signal after receiving the first clock signal and the first data signal, and transmit the first clock differential signal and the first data differential signal to the other redundancy computer interface unit. It should be noted here that the redundancy computer interface unit may transmit the first clock differential signal and the first data differential signal to the redundancy control computer, and each of the other redundancy computer interface units except the redundancy computer interface unit. In the specific sending process, a method of randomly selecting a sending sequence may be adopted. For example, when the redundancy control computer includes 3 redundancy computer interface units, which are respectively the redundancy computer interface unit a, the redundancy computer interface unit B, and the redundancy computer interface unit C, the redundancy computer interface unit a may transmit the first clock differential signal and the first data differential signal to the redundancy computer interface units B and C, may select to transmit the first clock differential signal and the first data differential signal to the redundancy computer interface unit B first, and may select to transmit the first clock differential signal and the first data differential signal to the redundancy computer interface unit C first.
The driving circuit 102 in the redundancy computer interface unit may also receive the second clock differential signal and the second data differential signal sent by the SPI sending controllers 104 of other redundancy computer interface units, and the redundancy computer interface unit may receive the second clock differential signal and the second data differential signal sent by each redundancy computer interface unit in other redundancy computer interface units except the redundancy computer interface unit in the redundancy control computer. The second clock signal may be a clock signal sent by the SPI sending controller 104 in the other redundancy computer interface unit according to a preset frequency, and the second data differential signal may carry flight data and result data of the target flight device acquired by the other redundancy computer interface unit.
After receiving the second data differential signal of the second clock differential signal, the driving circuit 102 may convert the second clock differential signal into a second clock signal, convert the second data differential signal into a second data signal, and send the second clock signal and the second data signal to the SPI receiving controller 105, so that the SPI receiving controller 105 may forward the second clock signal and the second data signal.
The SPI receiving controller 105 is configured to receive the second clock signal and the second data signal.
The SPI receiving controller 105 may receive the second clock signal and the second data signal, and since the second clock signal may be a clock signal that the other redundancy computer interface units transmit according to a preset frequency, the SPI controller may receive the data signal according to a receiving frequency of the second clock signal, that is, receive one second data signal every time one second clock signal is received.
The redundancy computer interface unit provided by the embodiment of the invention comprises: FPGA chip 101 and drive circuit 102, FPGA chip 101 includes: SPI transmission controller 104 and SPI reception controller 105; the redundancy computer interface unit may obtain the first data to be transmitted through the SPI transmission controller 104, convert the first data to be transmitted into the first data signal, and transmit the first clock signal and the first data signal to the driving circuit 102, and the driving circuit 102 may convert the first clock signal into the first clock differential signal, convert the first data signal into the first data differential signal, and transmit the first clock differential signal and the first data differential signal to the other redundancy computer interface units. The redundancy computer interface unit can also receive a second clock differential signal and a second data differential signal sent by other redundancy computer interface units. The data transmission between the redundancy computer interface unit and other redundancy computer interface units provided by the embodiment of the invention adopts an SPI synchronous transmission method, and the redundancy computer interface unit can receive the second data differential signal according to the receiving frequency of the second clock differential signal.
As an optional implementation manner of the embodiment of the present invention, the driving circuit 102 may include: a driver. The driver may be communicatively connected to SPI transmit controller 104 and SPI receive controller 105, respectively. A plurality of different ports may be provided on the drive, including at least: a receiving port for receiving the second clock differential signal and the second data differential signal sent by other redundancy computer interface units; and a transmit port for transmitting the first clock differential signal and the first data differential signal.
As an alternative implementation manner of the embodiment of the present invention, as shown in fig. 2, the driving circuit 102 may include: a transmit driver 201 and a receive driver 202. The transmission driver 201 may be communicatively connected to the SPI transmission controller 104, and the reception driver 202 may be communicatively connected to the SPI reception controller 105.
The transmission driver 201 is configured to receive a first clock signal and a first data signal, convert the first clock signal into a first clock differential signal, convert the first data signal into a first data differential signal, and transmit the first clock differential signal and the first data differential signal to other redundancy computer interface units.
The receiving driver 202 is configured to receive the second clock differential signal and the second data differential signal sent by the sending driver 201 of the other redundancy computer interface unit, convert the second clock differential signal into a second clock signal, convert the second data differential signal into a second data signal, and send the second clock signal and the second data signal to the SPI receiving controller 105.
As an alternative implementation manner of the embodiment of the present invention, as shown in fig. 3, the number of the sending drivers 201 is the same as the number of the other redundancy computer interface units, and the number of the receiving drivers 202 is the same as the number of the other redundancy computer interface units. In the embodiment of the present invention, the other redundancy computer interface unit may refer to another redundancy computer interface unit that is in communication connection with the redundancy computer interface unit provided in the embodiment of the present invention. The same number of transmit drivers 201, and receive drivers 202, as the number of other redundancy computer interface units may be provided, with each transmit driver 201 being communicatively connected to a different other redundancy computer interface unit, and each receive driver 202 being communicatively connected to a different other redundancy computer interface unit. As shown in fig. 3, if the number of other redundancy computer interface units is 1, the number of the transmission driver 201 and the reception driver 202 in the redundancy computer interface unit is 1.
Because the number of the sending drivers 201 is the same as that of the other redundancy computer interface units, and the number of the receiving drivers 202 is the same as that of the other redundancy computer interface units, each sending driver only needs to be provided with a port in communication connection with one other redundancy computer interface unit, so that the structure of the sending driver 201 is simpler. Similarly, the structure of the receiving driver 202 is also simple.
As an optional implementation manner of the embodiment of the present invention, the driving circuit 102 is an LVDS driver, and a transceiver circuit in the LVDS driver may be a dual-channel transceiver driving circuit.
Converting a first clock signal into a first clock differential signal and converting a first data signal into a first data differential signal, comprising:
the first clock signal is converted into a first clock LVDS, and the first data signal is converted into a first data LVDS.
After receiving the first clock signal, the LVDS driver may convert the first clock signal into the first clock LVDS, which is a low voltage differential signal, and since the signal is in a transmission process, if the transmission speed is fast, the signal is easy to distort, by converting the first clock signal into the low voltage differential signal, the LVDS driver may enable the signal to be difficult to distort while the transmission speed of the data is increased, and the accuracy of the data transmission is increased.
The second clock differential signal is the second clock LVDS, and the second data differential signal is the second data LVDS, that is, before the other redundancy computer interface units transmit the second clock signal and the second data signal, the second clock signal may also be converted into the second clock LVDS, and the second data signal is converted into the second data LVDS, so that the signals received by the LVDS drivers in the redundancy computer interface units are the second clock LVDS and the second data LVDS.
Converting the second differential clock signal into a second clock signal and converting the second differential data signal into a second data signal, comprising:
the second clock LVDS is converted into a second clock signal, and the second data LVDS is converted into a second data signal. The LVDS driver may convert the second clock LVDS into a second clock signal after receiving the second clock LVDS transmitted by the other redundancy computer interface unit, and convert the second data LVDS into a second data signal after receiving the second data LVDS transmitted by the other redundancy computer interface unit.
As shown in fig. 3, an embodiment of the present invention provides a redundancy control computer, which may include a plurality of redundancy computer interface units shown in fig. 1 or fig. 2, where each redundancy computer interface unit includes: the FPGA chip 101 and the driving circuit 102 are respectively connected with the driving circuit 102 in the redundancy computer interface unit and the driving circuits 102 in other redundancy computer interface units in the redundancy control computer in a communication way.
The redundancy control computer provided by the embodiment of the invention can comprise two redundancy computer interface units, three redundancy computer interface units or more redundancy computer interface units. The redundancy control computer shown in fig. 3 includes two redundancy computer interface units, one of the redundancy computer interface units is connected to a driving circuit of the other redundancy computer interface unit through the driving circuit in a communication manner, and the redundancy computer interface unit can send a first data differential signal and a first clock differential signal to the other redundancy computer interface unit through the driving circuit, and the redundancy computer interface unit can also receive a second data differential signal and a second clock differential signal sent by the other redundancy computer interface unit through the driving circuit. In fig. 3, CLK denotes a first clock signal, DATA denotes first DATA to be transmitted, CS denotes a chip select signal, and controls whether the redundancy computer interface unit receiving the CS is selected, and when the signal is a predetermined enable signal, it indicates that the redundancy computer interface unit receiving the CS is selected, that is, the first DATA to be transmitted to the redundancy computer interface unit is valid. CLK + represents a high level in the first clock differential signal, CLK-represents a low level in the first clock differential signal, DATA + represents a high level in the first DATA differential signal, and DATA-represents a low level in the first DATA differential signal.
The redundancy control computer provided by the embodiment of the invention can be arranged in target flight equipment, such as an unmanned aerial vehicle, and can be used for carrying out flight control on the target flight equipment. Flight data for the target flight device may first be acquired, which may include: flight speed, flight altitude, flight direction, flight acceleration and the like. The method comprises the steps of obtaining an operation instruction input by an operator of the target flight device, and calculating result data of the target flight device based on the flight data and the operation instruction, wherein the result data can be flight parameters. In the process of calculating the result data, in order to improve the reliability of the calculation task of the redundancy control computer, a plurality of redundancy computer interface units in the redundancy control computer can calculate the flight data of the target flight equipment to obtain the result data, and then the flight data and the result data can be sent to other redundancy computer interface units so as to carry out monitoring and voting algorithms and carry out flight control on the target flight equipment according to the results obtained by the monitoring and voting algorithms.
In addition, the redundancy control computer provided in the embodiment of the present invention can achieve the purpose of extending the redundancy through the redundancy computer interface units, where the redundancy may refer to the number of the redundancy computer interface units in the redundancy control computer.
As an optional implementation manner of the embodiment of the present invention, the redundancy control computer may further include: a CPU. The SPI transmission controller 104 and the SPI reception controller 105 are respectively connected to the CPU in communication.
And the CPU is used for acquiring the flight data of the target flight equipment and calculating the flight data according to the operation instruction of the user to obtain result data. And transmits the flight data and the result data as the first data to be transmitted to the SPI transmission controller 104, the flight data may include: flight speed, flight altitude, flight direction, flight acceleration and the like.
As shown in fig. 4, an embodiment of the present invention further provides a data transmission method, which is applied to the redundancy control computer shown in fig. 3, and the method may include:
s401, a first SPI sending controller of a first redundancy computer interface unit in the redundancy control computer generates a first clock signal, acquires first data to be sent, and converts the first data to be sent into a first data signal.
S402, the first SPI sending controller sends the first clock signal and the first data signal to the first driving circuit of the first redundancy computer interface unit.
S403, the first driving circuit receives the first clock signal and the first data signal, converts the first clock signal into a first clock differential signal, and converts the first data signal into a first data differential signal.
S404, the first driving circuit sends the first clock differential signal and the first data differential signal to the second redundancy computer interface unit.
In the process of transmitting the first data differential signal and the first clock differential signal, the first data differential signal may be transmitted for a plurality of times according to a preset data amount transmitted in each clock cycle, and the first data differential signal of a preset data amount is transmitted every time one first clock differential signal is transmitted, where the first clock differential signal and the first data differential signal of the preset data amount may be transmitted synchronously.
S405, the second driving circuit in the second redundancy computer interface unit receives the first clock differential signal and the first data differential signal, converts the first clock differential signal into a first clock signal, and converts the first data differential signal into a first data signal.
S406, the second driving circuit sends the first clock signal and the first data signal to the second SPI receiving controller of the second redundancy computer interface unit.
The second redundancy computer interface unit may receive the first data differential signal and the first clock differential signal transmitted by the first redundancy computer interface unit, and receive the first data differential signal at a reception frequency of the first clock differential signal, that is, receive one first data differential signal every time one first clock differential signal is received.
S407, the second SPI receiving controller in the second redundancy computer interface unit receives the first clock signal and the first data signal.
And S408, generating a second clock signal by a second SPI (serial peripheral interface) sending controller in the second redundancy computer interface unit, acquiring second data to be sent, and converting the second data to be sent into a second data signal.
And S409, the second SPI transmission controller transmits a second clock signal and a second data signal to a second driving circuit of the second redundancy computer interface unit.
And S410, the second driving circuit receives the second clock signal and the second data signal, converts the second clock signal into a second clock differential signal, and converts the second data signal into a second data differential signal.
And S411, the second driving circuit sends the second clock differential signal and the second data differential signal to the first redundancy computer interface unit.
S412, the first driving circuit of the first redundancy computer interface unit receives the second clock differential signal and the second data differential signal sent by the second driving circuit of the second redundancy computer interface unit, converts the second clock differential signal into a second clock signal, and converts the second data differential signal into a second data signal.
S413, the first driving circuit sends the second clock signal and the second data signal to the first SPI receiving controller.
S414, the first SPI receiving controller receives the second clock signal and the second data signal.
In the embodiment of the present invention, the first redundancy computer interface unit may send the first clock differential signal and the first data differential signal to the second redundancy computer interface unit, where the first data differential signal carries the flight data of the target flight device acquired by the first redundancy computer interface unit, and the result data obtained through calculation. The second redundancy computer interface unit can receive the first clock differential signal and the first data differential signal sent by the first redundancy computer interface unit, and send the second clock differential signal and the second data differential signal of the second redundancy computer interface unit to the first redundancy computer interface unit, the first redundancy computer interface unit can receive the second clock differential signal and the second data differential signal, and the data between the first redundancy computer interface unit and the second redundancy computer interface unit can be synchronously transmitted by adopting SPI (serial peripheral interface), so that the speed of data transmission between the first redundancy computer interface unit and the second redundancy computer interface unit can be improved.
As shown in fig. 5, the redundancy control computer provided in the embodiment of the present invention may include three redundancy computer interface units, where each two redundancy computer interface units are communicatively connected through the driving circuit 102. Each of the driving circuits 102 includes a sending driver 201 and a receiving driver 202, and each of the redundancy computer interface units sends the first data differential signal and the first clock differential signal to the other two redundancy computer interface units, and may also receive the second data differential signal and the second clock differential signal sent by the other two redundancy computer interface units.
As shown in fig. 6, an embodiment of the present invention further provides a data transmission method, which is applied to the redundancy control computer shown in fig. 5, and the method may include:
s601, a first redundancy computer interface unit in the redundancy control computer converts a first data signal generated in advance into a first data differential signal, and converts a first clock signal generated in advance into a first clock differential signal.
S602, the first redundancy computer interface unit sends the first data differential signal and the first clock differential signal to a second redundancy computer interface unit and a third redundancy computer interface unit in the redundancy control computer.
S603, the second and third redundancy computer interface units in the redundancy control computer receive the first data differential signal and the first clock differential signal, convert the first clock differential signal into a first clock signal, and convert the first data differential signal into a first data signal.
S604, the second and third redundancy computer interface units convert the pre-generated second data signal into a second data differential signal, and convert the pre-generated second clock signal into a second clock differential signal.
S605, the second redundancy computer interface unit and the third redundancy computer interface unit send the second data differential signal and the second clock differential signal to the first redundancy computer interface unit.
S606, the first redundancy computer interface unit receives the second data differential signal and the second clock differential signal, converts the second clock differential signal into a second clock signal, and converts the second data differential signal into a second data signal.
In the data transmission method provided in the embodiment of the present invention, each redundancy computer interface unit in the redundancy control computer may convert a first data signal including flight data and result data into a first data differential signal, convert a first clock signal generated in advance into a first clock differential signal, and transmit the first data differential signal and the first clock differential signal to other redundancy computer interface units; and meanwhile, the second data differential signal and the second clock differential signal sent by other redundancy computer interface units can also be received. Therefore, in the data transmission method provided by the embodiment of the invention, the methods for transmitting data among the redundant computer interface units all adopt SPI synchronous transmission, so that the data transmission speed can be improved.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiment, since it is basically similar to the embodiment of the redundancy control computer, the description is simple, and the relevant points can be referred to the partial description of the method embodiment.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A redundancy computer interface unit, comprising: the FPGA chip comprises: a serial peripheral interface SPI sending controller and an SPI receiving controller;
the SPI transmission controller is used for generating a first clock signal, acquiring first data to be transmitted, converting the first data to be transmitted into a first data signal, and transmitting the first clock signal and the first data signal to the driving circuit;
the driving circuit is configured to receive the first clock signal and the first data signal, convert the first clock signal into a first clock differential signal, convert the first data signal into a first data differential signal, and send the first clock differential signal and the first data differential signal to other redundancy computer interface units; receiving a second clock differential signal and a second data differential signal sent by a driving circuit of other redundancy computer interface units, converting the second clock differential signal into a second clock signal, converting the second data differential signal into a second data signal, and sending the second clock signal and the second data signal to the SPI receiving controller;
the SPI receiving controller is configured to receive the second clock signal and the second data signal.
2. The redundancy computer interface unit of claim 1, wherein the driving circuit comprises: a driver.
3. The redundancy computer interface unit of claim 1, wherein the driving circuit comprises: a transmission driver and a reception driver;
the transmission driver is configured to receive the first clock signal and the first data signal, convert the first clock signal into a first clock differential signal, convert the first data signal into a first data differential signal, and transmit the first clock differential signal and the first data differential signal to other redundancy computer interface units;
the receiving driver is used for receiving a second clock differential signal and a second data differential signal which are sent by sending drivers of other redundancy computer interface units, converting the second clock differential signal into a second clock signal, converting the second data differential signal into a second data signal, and sending the second clock signal and the second data signal to the SPI receiving controller.
4. The redundancy computer interface unit of claim 3, wherein the number of the transmission drivers is the same as the number of the other redundancy computer interface units, and the number of the reception drivers is the same as the number of the other redundancy computer interface units.
5. The redundancy computer interface unit of claim 3, wherein the driving circuit is a Low Voltage Differential Signaling (LVDS) driver, converts the first clock signal into a first clock differential signal, and converts the first data signal into a first data differential signal, comprising:
converting the first clock signal into a first clock LVDS and the first data signal into a first data LVDS;
the converting the second clock differential signal into a second clock signal and the converting the second data differential signal into a second data signal, where the converting the second clock differential signal into the second clock signal is a second clock LVDS, and the converting the second clock differential signal into the second data signal includes:
the second clock LVDS is converted into the second clock signal, and the second data LVDS is converted into the second data signal.
6. A redundancy control computer, comprising: a plurality of the redundancy computer interface units of any of claims 1 to 5, the drive circuits of each of the redundancy computer interface units being in respective communicative connection with the drive circuits of other redundancy computer interface units in the redundancy control computer.
7. A data transmission method applied to the redundancy control computer according to claim 6, the method comprising:
a first SPI (serial peripheral interface) sending controller in a first redundancy computer interface unit in a redundancy control computer generates a first clock signal, acquires first data to be sent, converts the first data to be sent into a first data signal, and sends the first clock signal and the first data signal to a first driving circuit of the first redundancy computer interface unit;
the first driving circuit receives the first clock signal and the first data signal, converts the first clock signal into a first clock differential signal, converts the first data signal into a first data differential signal, and sends the first clock differential signal and the first data differential signal to a second redundancy computer interface unit;
the first driving circuit of the first redundancy computer interface unit receives a second clock differential signal and a second data differential signal sent by a second driving circuit of the second redundancy computer interface unit, converts the second clock differential signal into a second clock signal, converts the second data differential signal into a second data signal, and sends the second clock signal and the second data signal to the first SPI receiving controller;
the first SPI receiving controller receives the second clock signal and the second data signal.
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