CN111710673B - EP-LVTSCR device with latch-up immunity characteristics - Google Patents
EP-LVTSCR device with latch-up immunity characteristics Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The invention discloses an EP-LVTSCR device with latch-up immunity, comprising: the semiconductor device comprises a P-type substrate, wherein the P-type substrate comprises an N well and a P well which are adjacent to each other; a first N+ injection region, a first P+ injection region and a second P+ injection region are sequentially arranged in the N well from left to right, and a first gate oxide layer region is arranged on the surface between the first P+ injection region and the second P+ injection region; a second N+ injection region and a third P+ injection region are sequentially arranged in the P trap from left to right; a third N+ injection region is bridged between the N well and the P well, and an SAB layer is arranged on the surface of the third N+ injection region; a second gate oxide layer region is arranged on the surface between the third N+ injection region and the second N+ injection region; and a first shallow trench isolation region is arranged between the second P+ injection region and the third N+ injection region. The EP-LVTSCR device provided by the invention reduces trigger voltage, improves maintenance voltage, and overcomes the latch-up problem of the traditional LVTSCR device structure.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to an EP-LVTSCR device with latch-up immunity.
Background
With the continued development of semiconductor integrated circuit technology, the dimensions of semiconductor device features have been reduced, resulting in damage to the device from electrostatic discharge (ESD) in the integrated circuit. The use of advanced process technology also greatly increases the manufacturing cost of the ESD protection device. Therefore, the design of the ESD protection device with high performance, good robustness and low cost has important practical value. Because of the strong positive feedback effect of the parasitic bipolar transistor, the Silicon Controlled Rectifier (SCR) device can maintain higher ESD current in small-sized devices, but in nano-scale CMOS technology, the trigger voltage of the SCR is usually higher than the breakdown voltage of the gate oxide of the input terminal, and the voltage after the SCR is turned on is clamped at about 2V, so that latch-up effect is easy to occur in the application of the ESD protection circuit. Therefore, the device cannot be used independently as an ESD protection unit in an integrated circuit.
In order to effectively protect the CMOS output buffer, a Low Voltage Triggered SCR (LVTSCR) is generally used at present, that is, a NMOS structure with a gate connected to a low level or a PMOS structure with a gate connected to a high level is embedded in a conventional SCR, so as to realize a lower trigger voltage, that is, an avalanche breakdown trigger voltage of an insert NMOS/PMOS device. However, LVTSCR maintains a voltage similar to SCR, which also faces latch-up risks in applications.
In view of the above problems, the existing solutions are as follows:
in the paper PLDD/NHALO-assisted low-trigger SCR for high-voltage tolerant ESD protection in foundry CMOS process without extra mask (IEEE Electron Device Lett, 2009) of Y.Shan, an additional N-LDD/P-HALO layer is added to the conventional LVTSCR device, which effectively improves the sustain voltage of the LVTSCR device. However, the additional level added by this scheme does not belong to the general level of the CMOS process, so that the device can only be realized by a specific process, and thus cannot be widely put into the application of the product.
In the paper "High-holding voltage silicon-controlled rectifier for ESD applications" (IEEE Electron Device Lett, 2014) of the J.J. Liou team, a floating N-well region is inserted into the LVTSCR device, so that the conduction path of parasitic SCR inside the device is prolonged, and the LVTSCR improved structure with High maintenance voltage is realized. However, the on-resistance of the device is increased by the scheme, so that the effective ESD protection current value of the device is reduced, and the overall robustness is reduced.
In the paper An improved GGNMOS triggered SCR for high holding voltage ESD protection applications (chip. Phys. B, 2015) of the S. -R.Dong team, a method for connecting the drain electrode of the embedded NMOS tube in the LVTSCR with the power supply end is provided, the current split ratio of the embedded NMOS tube in the LVTSCR in the device operation is enhanced, the circuit size of an SCR path is weakened, and the maintenance voltage value of the device is improved. However, this approach involves the risk of a significant reduction in device robustness caused by parasitic SCR non-conduction.
Disclosure of Invention
In order to solve the above-mentioned problems in the prior art, the present invention provides an EP-LVTSCR device having latch-up immunity. The technical problems to be solved by the invention are realized by the following technical scheme:
an EP-LVTSCR device having latch-up immunity characteristics, comprising: the semiconductor device comprises a P-type substrate, wherein the P-type substrate comprises an N well and a P well which are adjacent to each other; wherein, the liquid crystal display device comprises a liquid crystal display device,
a first N+ injection region, a first P+ injection region and a second P+ injection region are sequentially arranged in the N well from left to right, and a first gate oxide layer region is arranged on the surface between the first P+ injection region and the second P+ injection region;
a second N+ injection region and a third P+ injection region are sequentially arranged in the P trap from left to right;
a third N+ injection region is bridged between the N well and the P well, and an SAB layer is arranged on the surface of the third N+ injection region;
a second gate oxide layer region is arranged on the surface between the third N+ injection region and the second N+ injection region; and a first shallow trench isolation region is arranged between the second P+ injection region and the third N+ injection region.
In one embodiment of the present invention, the first gate oxide region and the second p+ implant region are both connected to the third n+ implant region.
In one embodiment of the present invention, a central axis of the third n+ implant region is aligned with a junction of the N-well and the P-well.
In one embodiment of the present invention, the SAB layer is aligned with a right boundary of the third n+ implant region and a length of the SAB layer is less than a length of the third n+ implant region.
In one embodiment of the invention, the length of the SAB layer is adjustable to control the variation of the device sustain voltage.
In one embodiment of the present invention, the semiconductor device further includes a first p+ ring and a second p+ ring connected to the P-type substrate, the first p+ ring is disposed on the left side of the N-well, the second p+ ring is disposed on the right side of the P-well, and the first p+ ring and the second p+ ring are both grounded.
In one embodiment of the present invention, a second shallow trench isolation region is disposed on the left side of the first p+ ring, between the first p+ ring and the first n+ implantation region, between the first n+ implantation region and the first p+ implantation region, between the second n+ implantation region and the third p+ implantation region, between the third p+ implantation region and the second p+ ring, and on the right side of the second p+ ring.
In one embodiment of the present invention, the second n+ implantation region, the third p+ implantation region, and the second gate oxide region are all grounded and serve as a cathode of the device; the first N+ injection region is connected with the first P+ injection region and serves as an anode of the device.
In one embodiment of the invention, a buried layer is arranged between the P-type substrate and the N well and between the P well, and the N well is a deep N well.
The invention has the beneficial effects that:
1. according to the EP-LVTSCR device with the latch immunity characteristic, the P+ injection region is added in the N well region of the traditional device to form the novel LVTSCR device with the embedded PMOS transistor structure, so that the trigger mechanism and the branch conduction effect of the device are improved, the trigger voltage and the on resistance of the device are reduced, the maintenance voltage of the device is improved, and the latch problem of the traditional LVTSCR type structure is solved;
2. the EP-LVTSCR device with latch-up immunity characteristics provided by the invention has low design cost and high performance, and is suitable for ESD protection in CMOS process technology.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of an EP-LVTSCR device with latch-up immunity according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of an EP-LVTSCR device provided by an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of an EP-LVTSCR device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another EP-LVTSCR device according to an embodiment of the present invention;
FIG. 5 is a graph comparing TLP I-V characteristics and leakage current measured in the same region of a conventional LVTSCR device and an EP-LVTSCR device provided by an embodiment of the present invention;
FIG. 6 is a graph showing TLP I-V characteristics and leakage current measurements for various D1 devices of EP-LVTSCR devices provided in accordance with an embodiment of the present invention;
FIG. 7 is a graph showing TLP I-V characteristics and leakage current measurements at different D2 of an EP-LVTSCR device provided by an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of an EP-LVTSCR device with latch-up immunity according to an embodiment of the present invention, including:
a P-type substrate 10, wherein the P-type substrate 10 includes an N-well 20 and a P-well 30 adjacent to each other; wherein, the liquid crystal display device comprises a liquid crystal display device,
a first n+ injection region 21, a first p+ injection region 22 and a second p+ injection region 24 are sequentially arranged in the N well 20 from left to right, and a first gate oxide region 23 is arranged on the surface between the first p+ injection region 22 and the second p+ injection region 24;
a second n+ injection region 31 and a third p+ injection region 32 are sequentially arranged in the P well 30 from left to right;
a third n+ injection region 41 is bridged between the N well 20 and the P well 30, and an SAB layer 42 is arranged on the surface of the third n+ injection region 41;
a second gate oxide region 33 is disposed on the surface between the third n+ implantation region 41 and the second n+ implantation region 31; a first shallow trench isolation region S1 (STI) is disposed between the second p+ implant region 24 and the third n+ implant region 41.
Further, the first gate oxide region 23 and the second p+ implantation region 24 are connected to the third n+ implantation region 41.
In this embodiment, the central axis of the third n+ implant region 41 is aligned with the junction of the N-well 20 and the P-well 30. The SAB layer 42 is aligned with the right boundary of the third n+ implant region 41, and the SAB layer 42 has a length less than the length of the third n+ implant region 41.
In this embodiment, a silicide blocking layer (SAB) 42 is disposed on the surface of the third n+ implantation region 41, and is mainly used to prevent silicide from forming on the surface layer of the implantation region below the silicide blocking layer to induce a ballast resistor.
Further, the lengths of the third n+ implantation region 41 and the SAB layer 42 in the present embodiment can be adjusted according to the actual requirements at the time of design to control the variation of the device sustain voltage. As shown in fig. 1, where D1 represents half the length of the third n+ implant region 41 and D2 represents the length of the SAB layer 42.
With continued reference to fig. 1, the EP-LVTSCR device further includes a first p+ ring 11 and a second p+ ring 12 connected to the P-type substrate 10, the first p+ ring 11 is disposed on the left side of the N-well 20, the second p+ ring 12 is disposed on the right side of the P-well 30, and both the first p+ ring 11 and the second p+ ring 12 are grounded.
The embodiment adopts a p-type protection ring (PGR) structure, and each PGR is connected to the Ground (GND), so that parasitic effects generated by the device and related to the substrate are avoided.
Further, a second shallow trench isolation region S2 (STI) is disposed on the left side of the first p+ ring 11, between the first p+ ring 11 and the first n+ implantation region 21, between the first n+ implantation region 21 and the first p+ implantation region 22, between the second n+ implantation region 31 and the third p+ implantation region 32, between the third p+ implantation region 32 and the second p+ ring 12, and on the right side of the second p+ ring 12.
The shallow trench isolation structure is adopted to realize isolation between active regions of devices, and the shallow trench isolation technology has the advantages of small-size isolation line width, clear active region division, uniform isolation region depth, adjustable size, excellent isolation region flat structure and the like, and has super latch-up resistance, so that the shallow trench isolation technology is very suitable for integrated circuits.
Further, the second n+ implantation region 31, the third p+ implantation region 32, and the second gate oxide region 33 are all grounded and serve as a cathode of the device; the first n+ implant region 21 is connected to the first p+ implant region 22 and serves as the anode of the device.
Referring to fig. 2, fig. 2 is an equivalent circuit diagram of an EP-LVTSCR device according to an embodiment of the present invention. According to the description of FIG. 2, the EP-LVTSCR device provided in this embodiment includes a first N-type parasitic transistor Q N1 Second N-type parasitic triode Q N2 First P-type parasitic triode Q P1 Second P-type parasitic triode Q P2 P-type MOS tube T1 and first N-well resistor R NW1 Second N-well resistor R NW2 First P-well resistor R PW1 Second P-wellResistor R PW2 。
In order to further explain the characteristics of the EP-LVTSCR device provided in this embodiment, the structure and the operation mechanism of the EP-LVTSCR device provided in this embodiment will be described in detail with reference to fig. 1 and 2. Referring to FIG. 3, FIG. 3 is a schematic circuit diagram of an EP-LVTSCR device according to an embodiment of the present invention, wherein a first N+ injection region 21 in an N-well 20 is connected to an anode and forms a first N-well resistor R with the N-well 20 NW1 And a second N-well resistor R NW2 First N-well resistor R NW1 And a second N-well resistor R NW2 The resistance of the N-well region below the left side of the first P+ implant region 22 is described as R, with the first P+ implant region 22 in the N-well as a boundary NW1 The resistance of the N-well region below the first P+ implant region 22 and its right side is described as R NW2 。
Correspondingly, a third P+ injection region 32 in the P-well 30 is connected with the cathode and forms a first P-well resistor R with the P-well 30 PW1 And a second P-well resistor R PW2 First P-well resistor R PW1 And a second P-well resistor R PW2 The resistance of the P-well region below the right side of the second N+ implantation region 31 is described as R by taking the second N+ implantation region 31 in the P-well as a boundary PW1 The resistance of the P-well region below the second n+ implant region 31 and its left side is described as R PW2 。
Further, the first p+ implant region 22 in the N-well 20, the P-well 30, and the third p+ implant region 32 in the P-well 30 form a first P-type parasitic transistor Q P1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the first P+ implant region 22 in the N-well 20 serves as Q P1 The emitter of the tube is connected to the anode, and the third P+ implant region 32 in the P-well 30 serves as Q P1 The collector of the tube is connected to the cathode, and the N-well 20 serves as Q P1 And a base of the tube.
The first N+ injection region 21 in the N well 20, the P well 30, and the second N+ injection region 31 in the P well 30 constitute a first N-type parasitic triode Q N1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the first N+ implant region 21 in the N-well 20 serves as Q N1 The collector of the tube is connected to the anode, the second N+ injection region 31 in the P-well 30 is connected as the emitter to the cathode of the Q2 tube, and the P-well 30 is Q N1 And a base of the tube.
Further, a third N crossing the N-well 20 and the P-well 30The +implantation region 41, the P-well 30 and the second N+ implantation region 31 in the P-well 30 form a second N-type parasitic triode Q N2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein a third N+ implant region 41 spanning N-well 20 and P-well 30 acts as Q N2 The collector of the tube, the second n+ implant region 31 in the P-well 30 acts as Q N2 Emitter of tube, P-well 30 as Q N2 Is formed on the base of the substrate. Please refer to the equivalent circuit diagram 2, Q N2 Collector and second N-well resistor R of tube NW2 Connected to and pass through a first N-well resistor R NW1 Is connected to the anode.
First p+ implant region 22 in N-well 20, second p+ implant region 24 in N-well 20, and second P-type parasitic transistor Q P2 Wherein the first P+ implantation region 22 and the second P+ implantation region 24 in the N-well 20 are respectively used as Q P2 Emitter and collector of tube, N-well 20 as Q P2 And a base of the tube.
The first p+ injection region 22 in the N-well 20, the second p+ injection region 24 in the N-well 20, and the first gate oxide region 23 located on the surface between the first p+ injection region 22 and the second p+ injection region 24 together form the MOS T1, wherein the first p+ injection region 22 in the N-well 20 serves as the source of the MOS T1, the second p+ injection region 24 in the N-well 20 serves as the drain of the MOS T1, and the first gate oxide region 23 serves as the gate of the T1.
Further, please continue to refer to fig. 2 and 3, wherein the first P-type parasitic transistor Q P1 And a second P-type parasitic triode Q P2 Common emitter, first N-type parasitic triode Q N1 And a second N-type parasitic triode Q N2 A common emitter; first P-type parasitic triode Q P1 Is used as the base electrode of the first N-type parasitic triode Q N1 Collector of the first P-type parasitic triode Q P1 Is taken as the collector electrode of the first N-type parasitic triode Q N1 Is formed on the base of the substrate.
Wherein, the first P-type parasitic triode Q P1 And a first N-type parasitic triode Q N1 The SCR path (thyristor channel) is constructed as shown by the right-hand dashed line in fig. 2. Second P-type parasitic triode Q P2 Parallel to the MOS transistor T1 and connected to the second N-type parasitic transistor Q N2 Together forming a shunt path as indicated by the left dashed line in fig. 2.
Specifically, the EP-LVTSCR device provided in this example operates as follows:
when ESD current is applied to the anode of the EP-LVTSCR device, a reverse bias diode formed by the first N+ injection region, the N well, the P well and the second P+ injection region is conducted; meanwhile, the voltage between the source and the gate of the P-type MOS transistor T1 exceeds the threshold voltage (about 0.9V) of the T1 transistor, so that the T1 transistor is turned on. As the current applied to the anode of the EP-LVTSCR device continues to increase, the first P-well resistance R PW1 The voltage drop across the first N-type triode Q exceeds the forward turn-on voltage of the diode formed by the P-well 30 and the second N+ implant region 31 N1 And a second N-type triode Q N2 Conducting. It is noted that the on-resistance of the T1 tube is lower than the first N-well resistance RNW1, so that the first N-type triode Q N1 And a second N-type triode Q N2 Can be triggered at a lower voltage. Finally, a first N-well resistor R NW1 The voltage drop across the first P-type triode Q exceeds the forward turn-on voltage of the diode formed by the first P+ implant region and N-well 20 P1 And a second P-type triode Q P2 Conducting. At this time, please refer to fig. 2 and 3, the first N-type transistor Q N1 And a first P-type triode Q P1 The SCR path is formed and serves as a main current path; second P-type triode Q P2 And T1 tube connected in parallel with second N-type triode Q N2 The series connection forms a shunt path. Due to the second P-type triode Q in the shunt path P2 And a first P-type triode Q in the SCR path P1 Shares an emitter (i.e., the first P+ implant region 22), so the first P-type transistor Q P1 The emitter implantation efficiency of (c) is relatively reduced. Likewise, a second N-type triode Q in the shunt path N2 And a first N-type triode Q in the SCR path N1 One emitter is shared (i.e., the second N+ implantation region 31), so that the first N-type transistor Q N1 The emitter implantation efficiency of (c) is relatively reduced. Further, the current gain of the SCR path is due to its internal parasitic transistor Q N1 And Q P1 The emitter implantation efficiency of (c) decreases, resulting in an increase in the sustain voltage of the device as a whole.
According to the EP-LVTSCR device provided by the invention, the P+ injection region is added in the N well region of the traditional device to form the novel LVTSCR device with the embedded PMOS transistor structure, so that the trigger mechanism and the branch conduction effect of the device are improved, the trigger voltage and the on-resistance of the device are reduced, the maintenance voltage of the device is improved, and the latch-up problem of the traditional LVTSCR type structure is solved.
Furthermore, the EP-LVTSCR device provided by this embodiment is suitable for design and fabrication in 28nm CMOS technology.
Example two
On the basis of the first embodiment, the present embodiment further provides an EP-LVTSCR device, please refer to fig. 4, fig. 4 is a schematic structural diagram of another EP-LVTSCR device provided in the embodiment of the present invention, wherein a buried layer 50 is disposed between the P-type substrate 10 and the N-well 20 and the P-well 30, and the N-well 20 is a deep N-well.
As in the first embodiment, the EP-LVTSCR device provided in this embodiment adds the p+ injection region in the deep N-well region to form a novel LVTSCR device with an embedded PMOS transistor structure, which improves the trigger mechanism and the branch conduction effect of the device, reduces the trigger voltage and the on-resistance of the device, improves the maintenance voltage of the device, and overcomes the latch-up problem of the conventional LVTSCR structure.
Example III
To further illustrate the benefits of the present invention, the EP-LVTSCR device provided by the present invention is tested and transmission line pulse tested in a 28nm CMOS process environment to verify the EP-LVTSCR device provided by the first embodiment.
Verification experiment 1: a measurement Transmission Line Pulse (TLP) test was performed in a 28nm CMOS process environment to verify the electrical characteristics of the EP-LVTSCR device.
The EP-LVTSCR and conventional LVTSCR for TLP test comparison provided in this example were both implemented in 28nm CMOS process, and the device widths were 40 μm.
Specifically, referring to fig. 5, fig. 5 is a graph showing TLP I-V characteristics and leakage current measured in the same region of a conventional LVTSCR device and an EP-LVTSCR device according to an embodiment of the present invention.
The ESD characteristics of conventional LVTSCR devices and EP-LVTSCR devices were measured using a Hanwa TED-T5000 TLP tester with a rise time of 10ns and a pulse width of 100ns, while the leakage test passed a 3.63V (1.1 x vdd) dc voltage sweep. The TLP I-V and leakage characteristics of the EP-LVTSCR devices and LVTSCR devices are shown in fig. 5, where the horizontal axis represents the voltage across the anode to cathode and the vertical axis represents the total anode to cathode current; the minimum voltage value on the horizontal axis is described as the maintenance voltage of the device, the leakage current is increased by more than two orders of magnitude and is defined as the failure point of the device, and the current value from the anode to the cathode is recorded as the secondary failure current value. As can be seen from fig. 5, the sustain voltage of the EP-LVTSCR device provided by the present invention is 5.49V, whereas the sustain voltage of the conventional LVTSCR device is only 2.18V, and it is apparent that the EP-LVTSCR device provided by the present invention has a higher sustain voltage than the conventional LVTSCR device. In addition, the trigger voltage of the EP-LVTSCR device provided by the invention is also reduced from 6.49V to 6.18V of the traditional LVTSCR device. In a 28nm CMOS process, the design window of the protection device is between 3.63V and 9.4V for ESD protection at the input/output end of a 2.5V or 3.3V power supply circuit.
Therefore, the EP-LVTSCR device provided by the invention overcomes the latch-up problem of the traditional LVTSCR type structure and can be used as an effective ESD protection scheme of the input/output port of a 2.5V/3.3V power supply circuit.
Verification experiment 2: the third N + implant region length (i.e., D1) and SAB layer length D2 across the N-well and P-well are tuned in a 28nm CMOS process environment and TLP measurements are performed to verify the electrical characteristics of the EP-LVTSCR device.
First, the TLP test was performed with d2=0.75 μm unchanged and D1 adjusted from 1.25 μm to 0.5 μm. Referring to fig. 6, fig. 6 is a graph showing TLP I-V characteristics and leakage current measurement results at different D1 according to an embodiment of the present invention, wherein the horizontal axis represents the voltage across the anode to the cathode and the vertical axis represents the total current from the anode to the cathode. As can be seen from fig. 6, the I-V curve of the EP-LVTSCR device exhibits two voltage hysteresis regions due to the multiple triggering effects when the device is turned on. The first hysteresis region I is the conduction of the trigger path, and the second hysteresis region II is the conduction of the SCR path. When D1 is reduced from 1.25 μm to 0.5 μm, the fault current I t2 Decreasing by about 0.1A and increasing the holding current for the second hysteresis by about 0.17A. This is because R NW2 And R is PW2 As D1 decreases, more current is required to trigger and maintain SCR conduction. It follows that the greater the length of D1, the more advantageous it is to improve the performance of the device.
Then, the TLP test was performed with D1=1.25 μm unchanged and D2 adjusted from 0.75 μm to 2.25 μm. Referring to FIG. 7, FIG. 7 is a graph showing TLP I-V characteristics and leakage current measurements at different D2 of an EP-LVTSCR device according to an embodiment of the present invention, wherein the horizontal axis represents the voltage across the anode-to-cathode and the vertical axis represents the total anode-to-cathode current. As can be seen from FIG. 7, when D2 is increased from 0.75 μm to 2.25. Mu.m, the ballasting resistance of the third N+ injection region gradually increases, resulting in an increase in the resistance of the branch path, further increasing the on-resistance R on This is seen in the slope change of the I-V characteristic in fig. 7. The results show that as D2 increases, the sustain voltage increases from 5.5V to 5.8V, and the fault current does not change significantly. It follows that the greater the length of D2, the more advantageous the sustain voltage characteristics of the device.
As shown by the experiment, the EP-LVTSCR device structure provided by the invention has lower on-resistance, reliable leakage current is about 2nA under the voltage of 3.63V, and is very suitable for protecting the input/output ports of a 2.5V/3.3V power supply circuit.
Furthermore, the EP-LVTSCR device and the ESD protection structure provided by the invention are expected to provide ESD protection for a 5V power supply circuit due to the adjustable maintaining voltage characteristic.
In addition, the EP-LVTSCR device provided by the invention is suitable for different processes and different layers of applications, and can achieve the effects of increasing the maintaining voltage and reducing the trigger voltage.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (8)
1. An EP-LVTSCR device having latch-up immunity, comprising: a P-type substrate (10), wherein the P-type substrate (10) comprises an N well (20) and a P well (30) which are adjacent to each other; wherein, the liquid crystal display device comprises a liquid crystal display device,
a first N+ injection region (21), a first P+ injection region (22) and a second P+ injection region (24) are sequentially arranged in the N well (20) from left to right, and a first gate oxide layer region (23) is arranged on the surface between the first P+ injection region (22) and the second P+ injection region (24);
a second N+ injection region (31) and a third P+ injection region (32) are sequentially arranged in the P well (30) from left to right;
a third N+ injection region (41) is bridged between the N well (20) and the P well (30), and an SAB layer (42) is arranged on the surface of the third N+ injection region (41);
a second gate oxide layer region (33) is arranged on the surface between the third N+ injection region (41) and the second N+ injection region (31); a first shallow trench isolation region (S1) is arranged between the second P+ injection region (24) and the third N+ injection region (41);
wherein the first gate oxide region (23) and the second p+ implantation region (24) are both connected to the third n+ implantation region (41) to form a shunt path.
2. EP-LVTSCR device according to claim 1, characterized in that the central axis of the third n+ implant region (41) is aligned with the junction of the N-well (20) and the P-well (30).
3. EP-LVTSCR device according to claim 1, characterized in that the SAB layer (42) is aligned with the right boundary of the third n+ implant region (41) and in that the SAB layer (42) has a length smaller than the length of the third n+ implant region (41).
4. EP-LVTSCR device according to claim 1, wherein the length of the SAB layer (42) is adjustable to control the variation of the device sustain voltage.
5. EP-LVTSCR device according to claim 1, characterized in that it further comprises a first p+ ring (11) and a second p+ ring (12) connected to the P-type substrate (10), the first p+ ring (11) being arranged on the left side of the N-well (20), the second p+ ring (12) being arranged on the right side of the P-well (30), and the first p+ ring (11) and the second p+ ring (12) being grounded.
6. EP-LVTSCR device according to claim 1, characterized in that a second shallow trench isolation region (S2) is provided on the left side of the first p+ ring (11), between the first p+ ring (11) and the first n+ implant region (21), between the first n+ implant region (21) and the first p+ implant region (22), between the second n+ implant region (31) and the third p+ implant region (32), between the third p+ implant region (32) and the second p+ ring (12) and on the right side of the second p+ ring (12).
7. EP-LVTSCR device according to claim 1, characterized in that the second n+ implant region (31), the third p+ implant region (32), the second gate oxide region (33) are all grounded and act as the cathode of the device; the first N+ injection region (21) is connected with the first P+ injection region (22) and serves as an anode of the device.
8. EP-LVTSCR device according to claim 1, characterized in that a buried layer (50) is provided between the P-type substrate (10) and the N-well (20) and the P-well (30), and in that the N-well (20) is a deep N-well.
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| US6521952B1 (en) * | 2001-10-22 | 2003-02-18 | United Microelectronics Corp. | Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection |
| CN105006476A (en) * | 2015-07-09 | 2015-10-28 | 武汉新芯集成电路制造有限公司 | Static protection circuit and SCR device |
| CN110875302A (en) * | 2018-08-31 | 2020-03-10 | 无锡华润上华科技有限公司 | Transient voltage suppression device and method of manufacturing the same |
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| TW473977B (en) * | 2000-10-27 | 2002-01-21 | Vanguard Int Semiconduct Corp | Low-voltage triggering electrostatic discharge protection device and the associated circuit |
| US7285828B2 (en) * | 2005-01-12 | 2007-10-23 | Intersail Americas Inc. | Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply |
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| US6521952B1 (en) * | 2001-10-22 | 2003-02-18 | United Microelectronics Corp. | Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection |
| CN105006476A (en) * | 2015-07-09 | 2015-10-28 | 武汉新芯集成电路制造有限公司 | Static protection circuit and SCR device |
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