CN111710673A - EP-LVTSCR device with latch-up immunity characteristic - Google Patents

EP-LVTSCR device with latch-up immunity characteristic Download PDF

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CN111710673A
CN111710673A CN202010469914.8A CN202010469914A CN111710673A CN 111710673 A CN111710673 A CN 111710673A CN 202010469914 A CN202010469914 A CN 202010469914A CN 111710673 A CN111710673 A CN 111710673A
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well
injection region
lvtscr
injection
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CN111710673B (en
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刘红侠
陈瑞博
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

The invention discloses an EP-LVTSCR device with latch-up immunity characteristic, which comprises: the device comprises a P-type substrate, a P-type substrate and a P-type substrate, wherein the P-type substrate comprises an N well and a P well which are adjacent; the N well is internally provided with a first N + injection region, a first P + injection region and a second P + injection region from left to right in sequence, and a first gate oxide region is arranged on the surface between the first P + injection region and the second P + injection region; a second N + injection region and a third P + injection region are sequentially arranged in the P well from left to right; a third N + injection region is bridged between the N well and the P well, and an SAB layer is arranged on the surface of the third N + injection region; a second gate oxide layer region is arranged on the surface between the third N + injection region and the second N + injection region; and a first shallow trench isolation region is arranged between the second P + injection region and the third N + injection region. The EP-LVTSCR device provided by the invention reduces the trigger voltage, improves the holding voltage and overcomes the latch-up problem of the traditional LVTSCR device structure.

Description

EP-LVTSCR device with latch-up immunity characteristic
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to an EP-LVTSCR device with latch-up immunity characteristic.
Background
With the continuous development of semiconductor integrated circuit technology, the feature size of semiconductor devices is continuously reduced, resulting in damage to the devices caused by electrostatic discharge (ESD) in the integrated circuits. In addition, the use of advanced process technology also greatly increases the manufacturing cost of the ESD protection device. Therefore, the ESD protection device with high performance, good robustness and low cost has important practical value. A Silicon Controlled Rectifier (SCR) device can maintain a high ESD current in a small-sized device due to a strong positive feedback effect of a parasitic bipolar transistor, but in a nano-scale CMOS technology, a trigger voltage of the SCR is usually higher than a breakdown voltage of a gate oxide of an input terminal, and a voltage of the SCR after being turned on is clamped to about 2V, so that a latch-up effect is easily generated in an application of an ESD protection circuit. Therefore, the device cannot be used independently as an ESD protection unit in an integrated circuit.
In order to effectively protect the CMOS output buffer, a low voltage trigger SCR (lvtscr) is currently used, that is, an NMOS structure with a gate connected to a low level or a PMOS structure with a gate connected to a high level is embedded in the conventional SCR to realize a lower trigger voltage, that is, an avalanche breakdown trigger voltage of an NMOS/PMOS device is inserted. However, the LVTSCR has a similar holding voltage as the SCR and is also at risk of latch-up in applications.
In view of the above problems, the existing solutions have the following three types:
in the article "PLDD/NHALO-associated low-trigger SCR for high-voltage transistor ESD protection in foundry CMOS process with out extra mask" (ieee electron Device let, 2009) of y.shan, an additional N-LDD/P-HALO layer is added to the conventional LVTSCR Device, which effectively improves the holding voltage of the LVTSCR Device. However, the added layer of the scheme is not a common layer of the CMOS process, so the device can only be realized by a specific process, and thus the scheme cannot be widely applied to products.
In a paper "High-holding voltage silicon-controller for ESD applications" (IEEE Electron Device Lett, 2014) in j.j.liou team, a floating N well region is inserted into an LVTSCR Device, a conduction path of a parasitic SCR inside the Device is extended, and an improved structure of the LVTSCR with a High holding voltage is realized. But the scheme increases the on-resistance of the device, thereby reducing the effective ESD protection current value of the device and causing the integral robustness to be poor.
In a paper "An improved GGNMOS triggered SCR for high holding voltage ESD protection applications" (chip.phys.b., 2015) of the r.dong team, a method for connecting the drain of An NMOS transistor embedded in the LVTSCR with a power supply terminal is provided, so that the current flow proportion of the NMOS transistor embedded in the LVTSCR in the device operation is enhanced, the circuit size of An SCR path is weakened, and the holding voltage value of the device is improved. But this solution has the risk of a significant reduction in device robustness due to the parasitic SCR not conducting.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an EP-lvdsr device having latch-up immunity characteristics. The technical problem to be solved by the invention is realized by the following technical scheme:
an EP-LVTSCR device having latch-up immunity properties, comprising: the device comprises a P-type substrate, a P-type substrate and a P-type substrate, wherein the P-type substrate comprises an N well and a P well which are adjacent; wherein the content of the first and second substances,
a first N + injection region, a first P + injection region and a second P + injection region are sequentially arranged in the N well from left to right, and a first gate oxide region is arranged on the surface between the first P + injection region and the second P + injection region;
a second N + injection region and a third P + injection region are sequentially arranged in the P well from left to right;
a third N + injection region is bridged between the N well and the P well, and an SAB layer is arranged on the surface of the third N + injection region;
a second gate oxide layer region is arranged on the surface between the third N + injection region and the second N + injection region; and a first shallow trench isolation region is arranged between the second P + injection region and the third N + injection region.
In one embodiment of the present invention, said first gate oxide region and said second P + implant region are both connected to said third N + implant region.
In one embodiment of the present invention, a central axis of the third N + implant region is aligned with a junction of the N-well and the P-well.
In one embodiment of the present invention, the SAB layer is aligned with a right side boundary of the third N + implant region, and a length of the SAB layer is smaller than a length of the third N + implant region.
In one embodiment of the present invention, the length of the SAB layer is adjustable to control the variation of the device sustain voltage.
In an embodiment of the present invention, the semiconductor device further includes a first P + ring and a second P + ring connected to the P-type substrate, the first P + ring is disposed on the left side of the N-well, the second P + ring is disposed on the right side of the P-well, and both the first P + ring and the second P + ring are grounded.
In an embodiment of the present invention, second shallow trench isolation regions are disposed on the left side of the first P + ring, between the first P + ring and the first N + implantation region, between the first N + implantation region and the first P + implantation region, between the second N + implantation region and the third P + implantation region, between the third P + implantation region and the second P + ring, and on the right side of the second P + ring.
In one embodiment of the present invention, the second N + injection region, the third P + injection region and the second gate oxide region are all grounded and serve as the cathode of the device; the first N + injection region is connected with the first P + injection region and serves as an anode of the device.
In one embodiment of the present invention, a buried layer is disposed between the P-type substrate and the N-well and the P-well, and the N-well is a deep N-well.
The invention has the beneficial effects that:
1. according to the EP-LVTSCR device with the latch-up immunity characteristic, the P + injection region is added in the N well region of the traditional device to form the novel LVTSCR device with the embedded PMOS transistor structure, so that the trigger mechanism and the branch conduction effect of the device are improved, the trigger voltage and the on-resistance of the device are reduced, the holding voltage of the device is improved, and the latch-up problem of the traditional LVTSCR type structure is solved;
2. the EP-LVTSCR device with the latch-up immunity characteristic provided by the invention has low design cost and high performance, and is suitable for ESD protection in a CMOS process technology.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic structural diagram of an EP-LVTSCR device with latch-up immunity provided by an embodiment of the invention;
FIG. 2 is an equivalent circuit diagram of an EP-LVTSCR device provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram of a circuit structure of an EP-LVTSCR device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another EP-LVTSCR device according to an embodiment of the present invention;
FIG. 5 is a graph comparing TLPI-V characteristics and leakage current measured in the same region for a conventional LVTSCR device and an EP-LVTSCR device provided by an embodiment of the present invention;
FIG. 6 is a graph showing the TLP I-V characteristics and leakage current measurements for different D1 for an EP-LVTSCR device according to an embodiment of the present invention;
FIG. 7 is a graph showing the TLP I-V characteristics and leakage current measurements for different D2 for EP-LVTSCR devices provided by embodiments of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of an EP-LVTSCR device with latch-up immunity provided by an embodiment of the present invention, including:
the structure comprises a P-type substrate 10, wherein the P-type substrate 10 comprises an N well 20 and a P well 30 which are adjacent; wherein the content of the first and second substances,
a first N + injection region 21, a first P + injection region 22 and a second P + injection region 24 are sequentially arranged in the N well 20 from left to right, and a first gate oxide region 23 is arranged on the surface between the first P + injection region 22 and the second P + injection region 24;
a second N + injection region 31 and a third P + injection region 32 are sequentially arranged in the P-well 30 from left to right;
a third N + injection region 41 is bridged between the N-well 20 and the P-well 30, and an SAB layer 42 is arranged on the surface of the third N + injection region 41;
a second gate oxide region 33 is arranged on the surface between the third N + injection region 41 and the second N + injection region 31; a first shallow trench isolation region S1(STI) is disposed between the second P + implantation region 24 and the third N + implantation region 41.
Further, the first gate oxide region 23 and the second P + implantation region 24 are both connected to the third N + implantation region 41.
In this embodiment, the central axis of the third N + implantation region 41 is aligned with the junction of the N-well 20 and the P-well 30. The SAB layer 42 is aligned with the right boundary of the third N + implant region 41, and the length of the SAB layer 42 is smaller than the length of the third N + implant region 41.
In the present embodiment, a silicide blocking layer (SAB)42 is disposed on the surface of the third N + implantation region 41, which is mainly used to prevent silicide formation on the surface of the implantation region therebelow to induce ballast resistance.
Further, the lengths of the third N + implantation region 41 and the SAB layer 42 in this embodiment may be adjusted during design according to actual requirements to control the variation of the device sustain voltage. As shown in fig. 1, wherein D1 represents half the length of the third N + implant region 41, and D2 represents the length of the SAB layer 42.
With continued reference to fig. 1, the EP-LVTSCR device further includes a first P + ring 11 and a second P + ring 12 connected to the P-type substrate 10, the first P + ring 11 is disposed on the left side of the N-well 20, the second P + ring 12 is disposed on the right side of the P-well 30, and both the first P + ring 11 and the second P + ring 12 are grounded.
The embodiment adopts a p-type guard ring (PGR) structure, and each PGR is connected to the Ground (GND), so that the parasitic effect related to the substrate generated by the device is avoided.
Further, second shallow trench isolation regions S2(STI) are disposed on the left side of the first P + ring 11, between the first P + ring 11 and the first N + implantation region 21, between the first N + implantation region 21 and the first P + implantation region 22, between the second N + implantation region 31 and the third P + implantation region 32, between the third P + implantation region 32 and the second P + ring 12, and on the right side of the second P + ring 12.
The shallow trench isolation structure is adopted to realize the isolation between the active regions of the devices in the embodiment, because the shallow trench isolation technology has the advantages of small-size isolation line width, definite active region division, uniform isolation region depth, adjustable size, excellent isolation region flat framework and the like, and has super-strong latch-up resistance capability, thereby being very suitable for integrated circuits.
Further, the second N + implantation region 31, the third P + implantation region 32, and the second gate oxide region 33 are all grounded and serve as the cathode of the device; the first N + implant region 21 is connected to the first P + implant region 22 and serves as the anode of the device.
Referring to fig. 2, fig. 2 is an equivalent circuit diagram of an EP-LVTSCR device according to an embodiment of the present invention. According to the description of fig. 2, the present embodiment provides an EP-LVTSCR device comprising a first N-type parasitic transistor QN1A second N-type parasitic triode QN2A first P-type parasitic triode QP1A second P-type parasitic triode QP2P-type MOS transistor T1, first N-well resistor RNW1A second N well resistor RNW2A first P well resistor RPW1And a second P-well resistor RPW2。
To further illustrate the features of the EP-LVTSCR device provided in this embodiment, the structure and the operation mechanism of the EP-LVTSCR device provided in this embodiment will be described in detail below with reference to fig. 1 and fig. 2. Referring to fig. 3, fig. 3 is a schematic circuit structure diagram of an EP-LVTSCR device according to an embodiment of the present invention, wherein a first N + injection region 21 in an N well 20 is connected to an anode and forms a first N well resistor R with the N well 20NW1And a second N-well resistor RNW2First N well resistor RNW1And a second N-well resistor RNW2With the first P + implant region 22 in the N-well as the boundary, the resistance of the N-well region below the left side of the first P + implant region 22 is described as RNW1The first P + implant region 22 and the N well region resistance under the right side thereof are described as RNW2。
Correspondingly, the third P + injection region 32 in the P well 30 is connected to the cathode and forms a first P well resistor R with the P well 30PW1And a second P-well resistor RPW2First P well resistor RPW1And a second P-well resistor RPW2With the second N + implant region 31 in the P-well as the boundary, the resistance of the P-well region under the right side of the second N + implant region 31 is described as RPW1The second N + implant region 31 and the P well region resistance under the left side thereof are described as RPW2。
Further, the first P + injection region 22 in the N-well 20, the P-well 30, and the third P + injection region 32 in the P-well 30 form a first P-type parasitic transistor QP1(ii) a Wherein the first P + in the N well 20Entry region 22 as QP1The emitter of the tube is connected to the anode, and the third P + implant region 32 in the P-well 30 acts as QP1The collector of the tube is connected to the cathode, and the N-well 20 is used as QP1The base of the tube.
The first N + injection region 21 in the N well 20, the P well 30 and the second N + injection region 31 in the P well 30 form a first N-type parasitic triode QN1(ii) a Wherein the first N + implantation region 21 in the N well 20 is used as QN1The collector of the tube is connected to the anode, the second N + implant 31 in P-well 30 is connected to the cathode as the emitter of Q2 tube, and P-well 30 is connected as QN1The base of the tube.
Further, the third N + injection region 41 crossing the N-well 20 and the P-well 30, and the second N + injection region 31 in the P-well 30 form a second N-type parasitic transistor QN2(ii) a Wherein the third N + implantation region 41 crossing the N well 20 and the P well 30 is used as QN2The collector of the tube, the second N + implant 31 in the P-well 30, serves as QN2Emitter of the tube, P-well 30 as QN2The base of (1). Please refer to the equivalent circuit diagram 2, QN2Collector of the tube and a second N-well resistor RNW2Connected and passed through a first N-well resistor RNW1Is connected to the anode.
A first P + injection region 22 in the N-well 20, a second P + injection region 24 in the N-well 20, and a second P-type parasitic transistor QP2Wherein the first P + implantation region 22 and the second P + implantation region 24 in the N well 20 are respectively used as QP2Emitter and collector of the tube, N-well 20 as QP2The base of the tube.
The first P + injection region 22 in the N-well 20, the second P + injection region 24 in the N-well 20, and the first gate oxide region 23 located on the surface between the first P + injection region 22 and the second P + injection region 24 together form a MOS transistor T1, wherein the first P + injection region 22 in the N-well 20 serves as the source of the MOS transistor T1, the second P + injection region 24 in the N-well 20 serves as the drain of the MOS transistor T1, and the first gate oxide region 23 serves as the gate of the transistor T1.
Further, please refer to fig. 2 and fig. 3, wherein the first P-type parasitic transistor QP1And a second P-type parasitic triode QP2A first N-type parasitic triode Q with a common emitterN1And a second N-type parasitic transistor QN2A common emitter; first P type parasitic triode QP1The base electrode of the first N-type parasitic triode QN1The first P-type parasitic triode QP1The collector of which is used as a first N-type parasitic triode QN1The base of (1).
Wherein the first P-type parasitic triode QP1And a first N-type parasitic triode QN1An SCR path (thyristor channel) is formed as indicated by the broken line on the right side in fig. 2. Second P-type parasitic triode QP2Is connected with the MOS transistor T1 in parallel and is connected with a second N-type parasitic triode QN2Together forming a shunt path, as shown by the left-hand dashed line in fig. 2.
Specifically, the working mechanism of the EP-LVTSCR device provided by this embodiment is as follows:
when ESD current is applied to the anode of the EP-LVTSCR device, a reverse bias diode formed by the first N + injection region, the N well, the P well and the second P + injection region is conducted; meanwhile, the voltage between the source and the gate of the P-type MOS transistor T1 exceeds the threshold voltage of the T1 transistor (about 0.9V), which causes the T1 transistor to be turned on. As the current applied to the anode of the EP-LVTSCR device continues to increase, the first P-well resistance RPW1The voltage drop at both ends exceeds the forward conduction voltage of the diode composed of the P trap 30 and the second N + injection region 31, and the first N-type triode QN1And a second N-type triode QN2And conducting. It is noted that the on-resistance of the T1 transistor is lower than the first N-well resistor RNW1, so the first N-type transistor QN1And a second N-type triode QN2Can be triggered at a lower voltage. Finally, a first N-well resistor RNW1The voltage drop at both ends exceeds the forward conduction voltage of the diode formed by the first P + injection region and the N trap 20, and the first P-type triode QP1And a second P-type triode QP2And conducting. At this time, referring to fig. 2 and 3, the first N-type transistor QN1And a first P-type triode QP1An SCR path is formed and is used as a main current path; second P-type triode QP2And a T1 tube connected in parallel with the second N-type triode QN2The series connection forms a shunt path. Because the second P-type triode Q in the shunt pathP2And a first P-type triode in the SCR pathQP1Share an emitter (i.e., the first P + implant region 22), so the first P-type transistor QP1The emitter injection efficiency is relatively reduced. Similarly, a second N-type triode Q in the shunt pathN2And a first N-type triode Q in the SCR pathN1Share an emitter (i.e., the second N + implant region 31), so that the first N-type transistor QN1The emitter injection efficiency is relatively reduced. Further, the current gain of the SCR path is due to its internal parasitic triode QN1And QP1The reduction in the emitter injection efficiency of (2) leads to an increase in the holding voltage of the device as a whole.
According to the EP-LVTSCR device provided by the invention, the P + injection region is added in the N well region of the traditional device to form the novel LVTSCR device with the embedded PMOS transistor structure, so that the trigger mechanism and the branch conduction effect of the device are improved, the trigger voltage and the on-resistance of the device are reduced, the holding voltage of the device is improved, and the latch problem of the traditional LVTSCR type structure is overcome.
Furthermore, the present embodiment provides an EP-LVTSCR device suitable for design and fabrication in 28nm CMOS technology.
Example two
On the basis of the first embodiment, the present embodiment further provides an EP-LVTSCR device, please refer to fig. 4, where fig. 4 is a schematic structural diagram of another EP-LVTSCR device according to an embodiment of the present invention, wherein a buried layer 50 is disposed between the P-type substrate 10 and the N-well 20 and the P-well 30, and the N-well 20 is a deep N-well.
Like the first embodiment, in the EP-lvdsr device provided in this embodiment, the P + implantation region is added in the deep N well region to form a novel lvdsr device having an embedded PMOS transistor structure, so that the trigger mechanism and the branch conduction effect of the device are improved, the trigger voltage and the on-resistance of the device are reduced, the sustain voltage of the device is improved, and the latch-up problem of the conventional lvdsr type structure is overcome.
EXAMPLE III
To further illustrate the beneficial effects of the present invention, experiments and transmission line pulse tests were performed on the EP-LVTSCR device provided by the present invention in a 28nm CMOS process environment to verify the EP-LVTSCR device provided by the first embodiment described above.
Verification experiment 1: a measured Transmission Line Pulse (TLP) test was performed in a 28nm CMOS process environment to verify the electrical characteristics of the EP-LVTSCR device.
Both the EP-LVTSCR for TLP test comparison provided in this example and the conventional LVTSCR were implemented in a 28nm CMOS process, with device widths of 40 μm.
Specifically, referring to FIG. 5, FIG. 5 is a graph comparing TLP I-V characteristics and leakage current measured in the same region for conventional LVTSCR devices and EP-LVTSCR devices provided by embodiments of the present invention.
The ESD characteristics of the conventional LVTSCR devices and EP-LVTSCR devices were measured using a Hanwa TED-T5000 TLP tester with a rise time of 10ns and a pulse width of 100ns, while the leakage test passed a dc voltage sweep of 3.63V (1.1 x VDD). The observed TLP I-V and leakage characteristics of the EP-LVTSCR and LVTSCR devices are shown in FIG. 5, where the horizontal axis represents the voltage across the anode to cathode and the vertical axis represents the total anode to cathode current; the minimum voltage value on the horizontal axis is described as the holding voltage of the device, the moment when the magnitude of the leakage current increases by more than two orders of magnitude is defined as the failure point of the device, and the current value from the anode to the cathode at the moment is recorded as the secondary failure current value. As can be seen from fig. 5, the holding voltage of the EP-LVTSCR device provided by the present invention is 5.49V, while the holding voltage of the conventional LVTSCR device is only 2.18V, and it is evident that the EP-LVTSCR device provided by the present invention has a higher holding voltage than the conventional LVTSCR device. In addition, the trigger voltage of the EP-LVTSCR device provided by the invention is also reduced to 6.18V from 6.49V of the traditional LVTSCR device. In a 28nm CMOS process, the design window of the protection device is between 3.63V and 9.4V for ESD protection of the input/output end of a 2.5V or 3.3V power supply circuit.
Therefore, the EP-LVTSCR device provided by the invention overcomes the latch-up problem of the traditional LVTSCR type structure and can be used as an effective ESD protection scheme for the input/output port of a 2.5V/3.3V power supply circuit.
Verification experiment 2: the third N + implant length (i.e., D1) and the SAB layer length D2 across the N-wells and P-wells were adjusted in a 28nm CMOS process environment and TLP measurements were performed to verify the electrical properties of the EP-LVTSCR devices.
First, the TLP test was performed by adjusting D1 from 1.25 μm to 0.5 μm while keeping D2 constant at 0.75 μm. Referring to fig. 6, fig. 6 is a graph of TLP I-V characteristics and leakage current measurement results under different conditions D1 according to the embodiment of the invention, wherein the horizontal axis represents the voltage across the anode and the cathode, and the vertical axis represents the total current from the anode to the cathode. It can be seen from fig. 6 that the I-V curve of the EP-LVTSCR device exhibits two voltage hysteresis regions due to the multiple triggering effect when the device is turned on. The first hysteresis zone I is caused by the conduction of the trigger path, and the second hysteresis zone II is caused by the conduction of the SCR path. When D1 decreased from 1.25 μm to 0.5 μm, the fault current It2The decrease is about 0.1A and the holding current for the second hysteresis is increased by about 0.17A. This is because RNW2And RPW2As D1 decreases, more current is required to trigger and maintain conduction of the SCR. It can be seen that the larger the length of D1, the more beneficial the device performance.
Then, the TLP test was performed by adjusting D2 from 0.75 μm to 2.25 μm while keeping D1 constant at 1.25 μm. Referring to fig. 7, fig. 7 is a graph showing TLP I-V characteristics and leakage current measurement results of different D2 for EP-LVTSCR devices provided by the embodiments of the present invention, wherein the horizontal axis represents voltage across the anode and the cathode, and the vertical axis represents total anode-to-cathode current. As can be seen from FIG. 7, as D2 increases from 0.75 μm to 2.25 μm, the ballast resistance of the third N + implant region gradually increases, resulting in an increase in the resistance of the branch path, further increasing the on-resistance RonThis can be seen from the change in slope of the I-V characteristic in fig. 7. The results show that as D2 increases, the holding voltage increases from 5.5V to 5.8V, and the fault current does not change significantly. It can be seen that the larger the length of D2 is, the more favorable the sustain voltage characteristics of the device are.
The experiment proves that the EP-LVTSCR device structure provided by the invention has lower on-resistance, the reliable leakage current is about 2nA under the voltage of 3.63V, and the EP-LVTSCR device structure is very suitable for protecting the input/output port of a 2.5V/3.3V power supply circuit.
Furthermore, the EP-LVTSCR device and the ESD protection structure provided by the invention have adjustable holding voltage characteristics, and are expected to provide ESD protection for a 5V power supply circuit.
In addition, the EP-LVTSCR device provided by the invention is suitable for different processes and different levels of application, and can play a role in improving the holding voltage and reducing the trigger voltage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (9)

1. An EP-LVTSCR device having latch-up immunity properties, comprising: the device comprises a P-type substrate (10), wherein the P-type substrate (10) comprises an N well (20) and a P well (30) which are adjacent; wherein the content of the first and second substances,
a first N + injection region (21), a first P + injection region (22) and a second P + injection region (24) are sequentially arranged in the N well (20) from left to right, and a first gate oxide region (23) is arranged on the surface between the first P + injection region (22) and the second P + injection region (24);
a second N + injection region (31) and a third P + injection region (32) are sequentially arranged in the P well (30) from left to right;
a third N + injection region (41) is bridged between the N well (20) and the P well (30), and an SAB layer (42) is arranged on the surface of the third N + injection region (41);
a second gate oxide layer (33) is arranged on the surface between the third N + injection region (41) and the second N + injection region (31); a first shallow trench isolation region (S1) is arranged between the second P + injection region (24) and the third N + injection region (41).
2. An EP-LVTSCR device according to claim 1, wherein the first gate oxide region (23) and the second P + implant region (24) are both connected to the third N + implant region (41).
3. EP-LVTSCR device according to claim 1, wherein the central axis of the third N + implant region (41) is aligned with the junction of the N-well (20) and the P-well (30).
4. The new EP-LVTSCR device according to claim 1, wherein the SAB layer (42) is aligned with the right boundary of the third N + implant region (41), and wherein the length of the SAB layer (42) is less than the length of the third N + implant region (41).
5. EP-LVTSCR device according to claim 1, wherein the length of the SAB layer (42) is adjustable to control the variation of the device sustain voltage.
6. The EP-LVTSCR device according to claim 1, further comprising a first P + ring (11) and a second P + ring (12) connected to the P-type substrate (10), wherein the first P + ring (11) is disposed to the left of the N-well (20), the second P + ring (12) is disposed to the right of the P-well (30), and wherein the first P + ring (11) and the second P + ring (12) are both grounded.
7. The new EP-LVTSCR device according to claim 1, wherein a second shallow trench isolation region (S2) is provided on the left side of the first P + ring (11), between the first P + ring (11) and the first N + implant region (21), between the first N + implant region (21) and the first P + implant region (22), between the second N + implant region (31) and the third P + implant region (32), between the third P + implant region (32) and the second P + ring (12), and on the right side of the second P + ring (12).
8. An EP-LVTSCR device according to claim 1, wherein the second N + implant region (31), the third P + implant region (32), the second gate oxide region (33) are all connected to ground and serve as the cathode of the device; the first N + implant region (21) is connected to the first P + implant region (22) and serves as the anode of the device.
9. An EP-LVTSCR device according to claim 1, wherein a buried layer (50) is provided between the P-type substrate (10) and the N-well (20) and the P-well (30), and wherein the N-well (20) is a deep N-well.
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