CN111709645A - System and method for generating assembly process flow of multi-chip assembly - Google Patents
System and method for generating assembly process flow of multi-chip assembly Download PDFInfo
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- CN111709645A CN111709645A CN202010551999.4A CN202010551999A CN111709645A CN 111709645 A CN111709645 A CN 111709645A CN 202010551999 A CN202010551999 A CN 202010551999A CN 111709645 A CN111709645 A CN 111709645A
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Abstract
The invention discloses a system and a method for generating an assembly process flow of a multi-chip assembly. The invention is generated by the computer-aided multi-chip assembly process flow, can obviously improve the generation efficiency and accuracy of the process flow, and reduces the requirements of the process flow programming on the experience of process personnel.
Description
Technical Field
The invention belongs to the field of integrated circuit packaging, and particularly relates to a system and a method for generating an assembly process flow of a multi-chip assembly.
Background
A Multi-Chip Module (MCM) is a high-density microelectronic assembly in which components such as a bare Chip and a discrete component are mounted on a high-density interconnection substrate and then interconnected and packaged to implement a certain function, typical mounting elements include the bare Chip, the discrete component, the substrate, a bonding wire, a package case, and the like, and typical mounting processes include reflow soldering, Chip bonding, Chip eutectic, Chip flip-Chip, wire bonding, and the like. With the increasing integration level of the multi-chip module, the difficulty of compiling the multi-chip module assembly process flow is also increased, and the process flow compiling means which is carried out by means of manual means and process experience has the problems of low efficiency and low accuracy, and can not meet the current requirements. In the prior art, the process condition information of a production order can be matched with a pre-established sorting algorithm, the process flow of processing the printed circuit board is automatically generated, and the efficiency of formulating the process flow of the printed circuit board and the product percent of pass are obviously improved; or merging the initial process flow of the combined imposition master plate through the process flow of traversing the combined imposition master plate, and selecting the shortest path from the initial process flow of the combined imposition master plate as the final process flow of the combined imposition master plate, thereby solving the problems of low manufacturing efficiency, high cost and unqualified product quality caused by manually compiling the process flow; or the welding process is determined according to the installation form of the components on the electronic product, and the assembly process flow of the electronic product is determined by combining the pretreatment and other flows, so that the process flow establishing efficiency of the surface mounting production line and the wave soldering production line is improved. The technical route of the process flow generated by a computer has obvious advantages in the aspects of improving the efficiency and the accuracy in the industries of printed circuit board production and printed circuit assembly; however, in the multi-chip module industry, there is no related art for the assembly process flow generation.
Disclosure of Invention
Aiming at the defects in the prior art, the system and the method for generating the assembly process flow of the multi-chip assembly solve the problems that the assembly process flow of the multi-chip assembly depends on manpower, and the efficiency and the accuracy are low.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a multi-chip assembly process flow generation system, comprising:
the design information extraction module is used for extracting design information related to the assembly process flow from the input design file;
the process information assignment module is used for assigning process information which is not contained in the design file but is necessary for generating the assembly process flow;
the process global mapping module is used for completing process global mapping according to the design information and the process information through a process global mapping rule to generate process information;
the process judgment module is used for judging the processes according to the design information, the process information and the process judgment rule, realizing process screening and generating the processes required by actual assembly;
the procedure ordering module is used for ordering the procedures required by actual assembly according to procedure ordering rules;
the manual confirmation module is used for manually screening, sequencing and confirming the sequenced procedures required by actual assembly to generate all procedures;
the step mapping module is used for finishing step mapping according to the step mapping rule, adding auxiliary steps and generating all the steps;
the assembly process flow generation module is used for generating the assembly process flow from all the working procedures and the working steps according to the preset content;
the design information extraction module, the process information assignment module, the process global mapping module, the process judgment module, the process sequencing module, the manual confirmation module, the process step mapping module and the assembly process flow generation module are sequentially connected.
Further: the design information comprises substrate type information, cavity groove information, component information and assembling consumable material information.
Further: the process information comprises the electrical interconnection requirement of the components, the power consumption of the components, the packaging requirement and the electrical interconnection requirement of the enclosure frame.
Further: the process judgment rule comprises substrate type rule judgment, component rule judgment in the cavity groove, component characteristic judgment and enclosure frame characteristic judgment.
Further: the preset content comprises a serial number, a work number name, a work step name and a work step content description.
A method for generating an assembly process flow of a multi-chip assembly comprises the following steps:
s1, inputting a design file;
s2, extracting design information related to the assembly process flow from the design file through a design information extraction module;
s3, assigning process information which is not contained in the design file but is necessary for generating the assembly process flow through a process information assignment module;
s4, according to the design information and the process information, the process global mapping module completes the process global mapping by using the process global mapping rule to generate process information;
s5, process judgment is carried out through the process judgment module according to the design information, the process information and the process judgment rule, process screening is achieved, and processes required by actual assembly are generated;
s6, sorting the procedures required by actual assembly through the procedure sorting module according to the procedure sorting rule;
s7, when the sorted procedure required by the actual assembly is normally generated, the step S8 is executed, otherwise, the step S3 is executed;
s8, manually screening, sorting and confirming the sorted procedures required by actual assembly through a manual confirmation module to generate all procedures;
s9, finishing the step mapping according to the step mapping rule through the step mapping module, adding auxiliary steps and generating all the steps;
and S10, generating an assembly process flow by the assembly process flow generation module according to all the procedures and the working steps according to preset contents.
Further: the process global mapping rule in the step S4 includes a bare chip mapping procedure, a discrete component mapping procedure, a bonding wire mapping procedure, a bonding tape mapping procedure, and a bounding box mapping procedure;
the mapping procedure of the bare chip comprises the following steps: eutectic welding, conductive adhesive bonding and non-conductive adhesive bonding;
the mapping procedure of the discrete components comprises the following steps: reflow soldering and conductive adhesive bonding;
the bonding wire mapping procedure is ultrasonic thermocompression bonding;
the bonding belt mapping procedure is micro-gap welding;
the bounding box mapping procedure is as follows: reflow soldering, conductive adhesive bonding and non-conductive adhesive bonding.
Further: the process ordering rule in step S6 includes:
sorting the reflow soldering, the eutectic soldering, the conductive adhesive bonding, the non-conductive adhesive bonding, the micro-gap soldering and the ultrasonic hot-press soldering from high to low according to the operation temperature;
carrying out micro-gap welding or ultrasonic hot-press welding after reflow welding, eutectic welding, conductive adhesive bonding and non-conductive adhesive bonding;
carrying out ultrasonic thermocompression bonding after the micro gap bonding;
performing frame welding before component welding;
and conducting adhesive bonding or non-conducting adhesive bonding of the surrounding frame is carried out after the micro-gap welding and the ultrasonic thermocompression welding.
Further: the step mapping rule in the step S9 comprises a step of automatic reflow soldering mapping, a step of manual reflow soldering mapping, a step of eutectic soldering mapping, a step of conductive adhesive bonding mapping, a step of non-conductive adhesive bonding mapping, a step of ultrasonic thermocompression soldering mapping, a step of micro-space soldering mapping and an auxiliary step;
the automatic reflow soldering mapping process comprises the steps of solder paste printing, automatic surface mounting, reflow soldering and process inspection in sequence;
the manual reflow soldering mapping process sequentially comprises manual coating of soldering paste, manual patching, reflow soldering and process inspection;
the eutectic welding mapping process comprises the steps of loading, programming/calling, running a program and process inspection in sequence;
the steps of the conductive adhesive bonding mapping are loading, dispensing, pasting, curing and process inspection in sequence;
the non-conductive adhesive bonding mapping process comprises the steps of feeding, dispensing, pasting, curing and process inspection in sequence;
the ultrasonic hot-press welding mapping process comprises the steps of feeding, programming/calling, bonding operation and process inspection in sequence;
the step of the micro-welding mapping comprises the steps of feeding, spot welding and process inspection in sequence;
the auxiliary steps comprise incoming material inspection, material identification and cleaning before assembly is started, and final inspection after assembly is completed.
The invention has the beneficial effects that: the invention is generated by the computer-aided multi-chip assembly process flow, can obviously improve the generation efficiency and accuracy of the process flow, and reduces the requirements of the process flow programming on the experience of process personnel.
Drawings
FIG. 1 is a block diagram of a multi-chip module assembly process flow generation system of the present invention;
FIG. 2 is a flow chart of a method for generating a multi-chip assembly process flow according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, a system for generating an assembly process flow of a multi-chip module includes:
the design information extraction module is used for extracting design information related to the assembly process flow from the input design file;
the process information assignment module is used for assigning process information which is not contained in the design file but is necessary for generating the assembly process flow;
the process global mapping module is used for completing process global mapping according to the design information and the process information through a process global mapping rule to generate process information;
the process judgment module is used for judging the processes according to the design information, the process information and the process judgment rule, realizing process screening and generating the processes required by actual assembly;
the procedure ordering module is used for ordering the procedures required by actual assembly according to procedure ordering rules;
the manual confirmation module is used for manually screening, sequencing and confirming the sequenced procedures required by actual assembly to generate all procedures;
the step mapping module is used for finishing step mapping according to the step mapping rule, adding auxiliary steps and generating all the steps;
the assembly process flow generation module is used for generating the assembly process flow from all the working procedures and the working steps according to the preset content;
the design information extraction module, the process information assignment module, the process global mapping module, the process judgment module, the process sequencing module, the manual confirmation module, the process step mapping module and the assembly process flow generation module are sequentially connected.
As shown in fig. 2, a method for generating an assembly process flow of a multi-chip module includes the following steps:
s1, inputting a design file;
the design file is a multi-chip component design data packet based on EDA software, and the EDA software for designing the multi-chip component comprises Cadence SiP Layout, Mentor Xpedition, Sigrity Unified packageDesigner and the like. The design file data packet contains necessary design information such as a substrate, components, a cascading mode, a packaging form and the like. The Design files have completed manufacturability Checks including Design Rule Checks (Design Rule Checks) for placement, routing, assembly in EDA software, and manual review by process personnel.
S2, extracting design information related to the assembly process flow from the design file through a design information extraction module;
the design information includes: extracting substrate material information contained in a multi-chip assembly design file, wherein the substrate types comprise a substrate based on a lamination process (such as a microwave printed substrate), a substrate based on a co-firing process (such as a low-temperature co-fired ceramic substrate and a high-temperature co-fired ceramic substrate), and a substrate based on a deposition process (such as a thin film ceramic substrate); extracting cavity and groove information contained in the multi-chip assembly design file, wherein the cavity and groove information comprises a through cavity, a blind cavity, a step cavity and the like; extracting component information contained in the multi-chip component design file, wherein the components comprise discrete components (such as chip capacitors and chip resistors), film components (such as transmission lines, power dividers and filters manufactured based on a film technology), bare chips and the like; and extracting the information of assembly consumables in the multi-chip component design file, wherein the assembly consumables comprise but are not limited to bonding wires (such as gold wires and aluminum wires), bonding belts (such as gold belts and copper belts) and enclosure frames (such as metal enclosure frames for realizing the air-tight packaging of the multi-chip component).
S3, assigning process information which is not contained in the design file but is necessary for generating the assembly process flow through a process information assignment module;
steps S2 and S3 may be performed in series, and process information that is not included in the design file but is necessary for generating the assembly process flow is assigned, including but not limited to: assigning values to the electrical interconnection requirements of bare chip mounting, wherein the assignment contents comprise electrical interconnection and non-electrical interconnection; assigning the power consumption of the bare chip, wherein the assignment content comprises the power consumption of the chip; assigning values to the packaging requirements of the multi-chip assembly, wherein the assignment content comprises air tightness packaging and non-air tightness packaging; and assigning values to the electrical interconnection requirements of the enclosure frame, wherein the assignment contents comprise electrical interconnection and non-electrical interconnection.
S4, according to the design information and the process information, the process global mapping module completes the process global mapping by using the process global mapping rule to generate process information;
process global mapping rules include, but are not limited to: the mapping procedure of the bare chip comprises eutectic welding, conductive adhesive bonding and non-conductive adhesive bonding; the discrete component mapping procedure comprises reflow soldering and conductive adhesive bonding; the bonding wire mapping procedure is ultrasonic thermocompression bonding; the bonding belt mapping procedure is micro-gap welding; the surrounding frame mapping procedure comprises reflow soldering, conductive adhesive bonding and non-conductive adhesive bonding.
S5, process judgment is carried out through the process judgment module according to the design information, the process information and the process judgment rule, process screening is achieved, and processes required by actual assembly are generated;
process decision rules include, but are not limited to: (1) and judging the substrate type rule. The allowable process is determined according to the substrate type rule. Substrate type rules include, but are not limited to: the laminate type substrate allows a process not involving eutectic soldering. (2) And regularly judging the components in the cavity groove. And judging an allowable process according to the rule of the components in the cavity. The component rules in the cavity slot include, but are not limited to: the cavity groove allows the working procedure not to contain eutectic welding; the cavity allows processes that do not involve solder paste printing of discrete components. (3) And judging the characteristics of the components. And judging the allowable process according to the component characteristic judgment principle. The component characteristic determination principle includes but is not limited to: electrically connected bare chips allow processes that do not involve non-conductive glue bonding; the non-electrically connected bare chip allows the process to be non-conductive glue bonding only; the bare chip with the power consumption larger than 1W only allows eutectic welding; when a bare chip with power consumption of more than 1W is mounted on a laminated substrate, manual confirmation is required. (4) And judging the characteristics of the surrounding frame. Reflow soldering is used for the enclosure frame which is packaged in an airtight manner and has the electrical interconnection requirement; the enclosing frames which are packaged in a non-airtight way and have the electrical interconnection requirement are bonded by using conductive adhesive; the enclosing frames which are packaged in a non-airtight mode and have no electrical interconnection requirement are bonded by using non-conductive glue; and if the enclosure frame assembly requirements of the airtight package and the non-electrical interconnection requirements appear, screening the process and reporting errors, and re-confirming the design drawing or re-assigning the process information.
S6, sorting the procedures required by actual assembly through the procedure sorting module according to the procedure sorting rule;
order ordering rules include, but are not limited to: the sequence of the procedures of reflow soldering, eutectic soldering, conductive adhesive bonding, non-conductive adhesive bonding, micro-gap soldering and ultrasonic hot-press soldering is determined according to the operating temperature of the procedures from high to low; carrying out micro-gap welding or ultrasonic hot-press welding after the processes of reflow welding, eutectic welding, conductive adhesive bonding and non-conductive adhesive bonding; carrying out ultrasonic hot-press welding after micro-gap welding; the surrounding frame welding process is carried out before the component welding process, and the surrounding frame conductive adhesive bonding and non-conductive adhesive bonding processes are carried out after the micro-gap welding and ultrasonic hot-press welding processes.
S7, when the sorted procedure required by the actual assembly is normally generated, the step S8 is executed, otherwise, the step S3 is executed;
and if the sorted required actual assembly process cannot be generated, the prompt fails, S3 is returned to carry out assignment of the process information, and S4-S7 is carried out again after the missing or wrong process information is completed until the sorted required actual assembly process is normally generated.
S8, manually screening, sorting and confirming the sorted procedures required by actual assembly through a manual confirmation module, and adjusting according to process requirements and actual conditions of a production line to generate all procedures;
s9, finishing the step mapping according to the step mapping rule through the step mapping module, adding auxiliary steps and generating all the steps;
step mapping rules include, but are not limited to: the automatic reflow soldering mapping process comprises the steps of solder paste printing, automatic surface mounting, reflow soldering and process inspection in sequence; the manual reflow soldering mapping process comprises the steps of manual coating of soldering paste, manual patching, reflow soldering and process inspection in sequence; the eutectic welding mapping process comprises the steps of loading, programming/calling, running a program and process inspection in sequence; the steps of the conductive adhesive bonding mapping are material loading, adhesive dispensing, surface mounting, curing and process inspection in sequence; the non-conductive adhesive bonding mapping process comprises the steps of feeding, dispensing, pasting, curing and process inspection in sequence; the ultrasonic hot-press welding mapping process comprises the steps of feeding, programming/calling, bonding operation and process inspection in sequence; the micro-gap welding mapping process sequentially comprises the steps of feeding, spot welding and process inspection; the auxiliary steps are incoming material inspection, material identification, cleaning before assembly begins, and final inspection after assembly is completed.
And S10, generating an assembly process flow by the assembly process flow generation module according to all the procedures and the working steps according to preset contents. The predetermined content includes, but is not limited to, a serial number, a process name, a process step name, and a process step content description.
Claims (9)
1. A multi-chip assembly process flow generation system, comprising:
the design information extraction module is used for extracting design information related to the assembly process flow from the input design file;
the process information assignment module is used for assigning process information which is not contained in the design file but is necessary for generating the assembly process flow;
the process global mapping module is used for completing process global mapping according to the design information and the process information through a process global mapping rule to generate process information;
the process judgment module is used for judging the processes according to the design information, the process information and the process judgment rule, realizing process screening and generating the processes required by actual assembly;
the procedure ordering module is used for ordering the procedures required by actual assembly according to procedure ordering rules;
the manual confirmation module is used for manually screening, sequencing and confirming the sequenced procedures required by actual assembly to generate all procedures;
the step mapping module is used for finishing step mapping according to the step mapping rule, adding auxiliary steps and generating all the steps;
the assembly process flow generation module is used for generating the assembly process flow from all the working procedures and the working steps according to the preset content;
the design information extraction module, the process information assignment module, the process global mapping module, the process judgment module, the process sequencing module, the manual confirmation module, the process step mapping module and the assembly process flow generation module are sequentially connected.
2. The system of claim 1, wherein the design information includes substrate type information, cavity pocket information, component information, and assembly consumable information.
3. The system of claim 1, wherein the process information includes component electrical interconnection requirements, component power consumption, packaging requirements, and enclosure electrical interconnection requirements.
4. The system of claim 1, wherein the process decision rules include substrate type rule decision, in-cavity component rule decision, component characteristic decision, and enclosure characteristic decision.
5. The multi-chip assembly process flow generation system of claim 1, wherein the predetermined content includes a serial number, a work number name, a work step name, and a work step content description.
6. A method for generating an assembly process flow of a multi-chip assembly is characterized by comprising the following steps:
s1, inputting a design file;
s2, extracting design information related to the assembly process flow from the design file through a design information extraction module;
s3, assigning process information which is not contained in the design file but is necessary for generating the assembly process flow through a process information assignment module;
s4, according to the design information and the process information, the process global mapping module completes the process global mapping by using the process global mapping rule to generate process information;
s5, process judgment is carried out through the process judgment module according to the design information, the process information and the process judgment rule, process screening is achieved, and processes required by actual assembly are generated;
s6, sorting the procedures required by actual assembly through the procedure sorting module according to the procedure sorting rule;
s7, when the sorted procedure required by the actual assembly is normally generated, the step S8 is executed, otherwise, the step S3 is executed;
s8, manually screening, sorting and confirming the sorted procedures required by actual assembly through a manual confirmation module to generate all procedures;
s9, finishing the step mapping according to the step mapping rule through the step mapping module, adding auxiliary steps and generating all the steps;
and S10, generating an assembly process flow by the assembly process flow generation module according to all the procedures and the working steps according to preset contents.
7. The method of claim 6, wherein the global mapping rule of step S4 includes a die mapping procedure, a discrete component mapping procedure, a bonding wire mapping procedure, a bonding tape mapping procedure, and a frame mapping procedure;
the mapping procedure of the bare chip comprises the following steps: eutectic welding, conductive adhesive bonding and non-conductive adhesive bonding;
the mapping procedure of the discrete components comprises the following steps: reflow soldering and conductive adhesive bonding;
the bonding wire mapping procedure is ultrasonic thermocompression bonding;
the bonding belt mapping procedure is micro-gap welding;
the bounding box mapping procedure is as follows: reflow soldering, conductive adhesive bonding and non-conductive adhesive bonding.
8. The method of claim 7, wherein the process sequence rule of step S6 includes:
sorting the reflow soldering, the eutectic soldering, the conductive adhesive bonding, the non-conductive adhesive bonding, the micro-gap soldering and the ultrasonic hot-press soldering from high to low according to the operation temperature;
carrying out micro-gap welding or ultrasonic hot-press welding after reflow welding, eutectic welding, conductive adhesive bonding and non-conductive adhesive bonding;
carrying out ultrasonic thermocompression bonding after the micro gap bonding;
performing frame welding before component welding;
and conducting adhesive bonding or non-conducting adhesive bonding of the surrounding frame is carried out after the micro-gap welding and the ultrasonic thermocompression welding.
9. The method of claim 6, wherein the step mapping rules of step S9 include steps of automatic reflow soldering mapping, manual reflow soldering mapping, eutectic soldering mapping, conductive adhesive bonding mapping, non-conductive adhesive bonding mapping, ultrasonic thermal compression soldering mapping, micro-space soldering mapping and auxiliary steps;
the automatic reflow soldering mapping process comprises the steps of solder paste printing, automatic surface mounting, reflow soldering and process inspection in sequence;
the manual reflow soldering mapping process sequentially comprises manual coating of soldering paste, manual patching, reflow soldering and process inspection;
the eutectic welding mapping process comprises the steps of loading, programming/calling, running a program and process inspection in sequence;
the steps of the conductive adhesive bonding mapping are loading, dispensing, pasting, curing and process inspection in sequence;
the non-conductive adhesive bonding mapping process comprises the steps of feeding, dispensing, pasting, curing and process inspection in sequence;
the ultrasonic hot-press welding mapping process comprises the steps of feeding, programming/calling, bonding operation and process inspection in sequence;
the step of the micro-welding mapping comprises the steps of feeding, spot welding and process inspection in sequence;
the auxiliary steps comprise incoming material inspection, material identification and cleaning before assembly is started, and final inspection after assembly is completed.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114186298A (en) * | 2021-11-15 | 2022-03-15 | 广东宏远新科自动化技术开发有限公司 | Intelligent mechanical part manufacturing and operating method and system |
| CN114186298B (en) * | 2021-11-15 | 2022-09-27 | 广东宏远新科自动化技术开发有限公司 | Intelligent mechanical part manufacturing and operating method and system |
| CN116487309A (en) * | 2023-06-26 | 2023-07-25 | 中国电子科技集团公司第二十九研究所 | Multi-chip assembly multi-station automatic production line of multi-layer track and control method |
| CN116487309B (en) * | 2023-06-26 | 2023-08-22 | 中国电子科技集团公司第二十九研究所 | Multi-chip assembly multi-station automatic production line of multi-layer track and control method |
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| CN111709645B (en) | 2022-03-18 |
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