CN111708213A - Color film substrate mother board, display panel and display device - Google Patents
Color film substrate mother board, display panel and display device Download PDFInfo
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- CN111708213A CN111708213A CN202010620916.2A CN202010620916A CN111708213A CN 111708213 A CN111708213 A CN 111708213A CN 202010620916 A CN202010620916 A CN 202010620916A CN 111708213 A CN111708213 A CN 111708213A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133514—Colour filters
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
Abstract
The embodiment of the invention discloses a color film substrate mother board, a display panel and a display device. This various membrane base plate mother board includes: a first substrate base plate; the first substrate base plate comprises a plurality of sub color film base plate areas which are arranged in an array mode; a plurality of light-shielding layers and a plurality of planarization layers on the first substrate; the light shielding layer and the planarization layer are stacked and arranged at intervals along the direction perpendicular to the first substrate; the shading layer is positioned in the sub color film substrate area; the planarization layer is positioned in a gap between the sub color film substrate area and the adjacent sub color film substrate area; the at least one planarization layer comprises a plurality of disconnected first sub-planarization layers; and the spacing region between the adjacent first sub-planarization layers is positioned at the gap between at least part of the adjacent sub-color film substrate regions. The color film substrate mother board provided by the embodiment of the invention is used for solving the problem that a first substrate of the color film substrate mother board in the prior art is warped.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a color film substrate mother board, a display panel and a display device.
Background
Since fingerprints of everyone have uniqueness and invariance, a technology of recognizing fingerprints as identities has been rapidly developed in recent years. For example, in the field of mobile phones, the optical fingerprint identification technology is applied more and more widely with the requirement of more and more people on narrow borders and full screens of the mobile phones.
The in-screen fingerprint identification technology of the liquid crystal-based display device mainly comprises the steps of manufacturing a photosensitive sensor on the side of an array substrate, and then constructing a collimation through hole above the photosensitive sensor so as to enable light reflected back from a touch main body to irradiate the photosensitive sensor, and utilizing reflection difference of fingerprint ridges and fingerprint valleys to realize imaging identification. In order to construct the collimating through holes, when a color film substrate mother board is prepared, multiple light shielding layers are required to be prepared in a sub color film substrate area corresponding to a first substrate of the color film substrate mother board, the multiple light shielding layers located in the sub color film substrate area are provided with the collimating through holes, vertical projections of the collimating through holes on the light shielding layers on the first substrate are overlapped, and in a direction perpendicular to the first substrate, adjacent light shielding layers are spaced through a flattening layer arranged on the whole surface. However, because the preparation temperature of the planarization layer and the light shielding layer is high, and the planarization layer is thick, after a plurality of planarization layer processes and a plurality of light shielding layer processes, the planarization layer shrinks seriously, the first substrate is easy to warp, the bonding of the color film substrate mother board and the array substrate mother board is affected, and the display performance of the display panel formed subsequently is affected.
Disclosure of Invention
The embodiment of the invention provides a color film substrate mother board, a display panel and a display device, and aims to solve the problem that a first substrate of the color film substrate mother board in the prior art is warped.
In a first aspect, an embodiment of the present invention provides a color filter substrate mother board, where the color filter substrate mother board includes:
a first substrate base plate; the first substrate base plate comprises a plurality of sub color film base plate areas which are arranged in an array mode;
a plurality of light-shielding layers and a plurality of planarization layers on the first substrate;
the light shielding layer and the planarization layer are stacked and arranged at intervals along a direction perpendicular to the first substrate; the shading layer is positioned in the sub color film substrate area; the planarization layer is positioned in a gap between the sub color film substrate area and the adjacent sub color film substrate area;
at least one of the planarization layers comprises a plurality of unconnected first sub-planarization layers; and the spacing region between the adjacent first sub-planarization layers is positioned at the gap between at least part of the adjacent sub-color film substrate regions.
In a second aspect, an embodiment of the present invention further provides a display panel motherboard, including:
the color film substrate mother board according to the first aspect;
the array substrate mother board is arranged opposite to the color film substrate mother board;
the liquid crystal layer is positioned between the array substrate mother board and the color film substrate mother board;
the array substrate motherboard comprises a second substrate, and the second substrate comprises a plurality of sub-array substrate areas arranged in an array; the sub array substrate areas correspond to the sub color film substrate areas one by one; the sub color film substrate area is provided with a color film substrate, and the sub array substrate area is provided with an array substrate.
In a third aspect, an embodiment of the present invention further provides a display panel, where the display panel is formed by cutting along a cutting line of the display panel motherboard according to the second aspect;
the vertical projection of the cutting line on the plane of the first substrate base plate is positioned in the vertical projection of the gap between the adjacent sub color film base plate areas on the plane of the first substrate base plate; the display panel comprises the array substrate, the color film substrate and the liquid crystal layer.
In a fourth aspect, an embodiment of the present invention further provides a display device, where the display device includes the display panel described in the third aspect.
According to the color film substrate mother board, the display panel and the display device provided by the embodiment of the invention, the flattening layer arranged on the whole surface is set into the plurality of first sub-flattening layers which are not mutually connected, so that the stress generated by shrinkage of the flattening layer arranged on the whole surface in the curing process is released through the gap between the adjacent first sub-flattening layers, and the problem that the first substrate is warped due to the action of the stress on the first substrate is avoided; in addition, the spacing area between the adjacent first sub-planarization layers is positioned in the gap between at least part of the sub-color film substrate areas, so that the flatness between the films in the sub-color film substrate areas is ensured, and the display performance of the display panel is improved after the display panel is formed subsequently.
Drawings
Fig. 1 is a schematic structural diagram of a color filter substrate motherboard provided in the prior art;
FIG. 2 is a cross-sectional view taken along RR' of FIG. 1;
fig. 3 is a schematic structural diagram of a color filter substrate motherboard according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view taken along the direction BB' in FIG. 3
Fig. 5 is a schematic structural diagram of a planarization layer according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another planarization layer provided in an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of another planarization layer provided in an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of another planarization layer provided in an embodiment of the present invention;
fig. 9 is a schematic diagram of a film structure of a mother substrate of a color film substrate according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a display panel motherboard according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 13 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 14 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a light-shielding layer according to an embodiment of the present invention;
FIG. 16 is a schematic structural diagram of a light-shielding layer according to yet another embodiment of the present invention;
FIG. 17 is a schematic structural diagram of a light-shielding layer according to yet another embodiment of the present invention;
fig. 18 is a schematic structural diagram of a first sub-planarization layer according to an embodiment of the present invention;
fig. 19 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a color filter substrate mother board in the prior art, and fig. 2 is a cross-sectional view along an RR ' direction in fig. 1, as shown in fig. 1 and fig. 2, a color filter substrate mother board 100 ' in the prior art includes a first substrate 10 ', a plurality of light-shielding layers (not shown) on the first substrate 10 ', and a plurality of planarization layers 30 ' disposed on the entire surface; the light-shielding layers and the planarization layers 30' are spaced apart. The applicant finds that the preparation of the shading layer and the planarization layer 30 'both need to be processed by a thermal process, and when the planarization layer 30' arranged on the whole surface is cured by the thermal process, stress generated when the planarization layer 30 'shrinks acts on the first substrate 10', so that the first substrate 10 'warps, which affects the bonding of the color film substrate mother board 100' and the array substrate mother board, and further affects the display performance of the subsequently formed display panel.
Based on the above problem, an embodiment of the present invention provides a color film substrate mother board, including: a first substrate base plate; the first substrate base plate comprises a plurality of sub color film base plate areas which are arranged in an array mode; a plurality of light-shielding layers and a plurality of planarization layers on the first substrate; the light shielding layer and the planarization layer are stacked and arranged at intervals along the direction perpendicular to the first substrate; the shading layer is positioned in the sub color film substrate area; the planarization layer is positioned in a gap between the sub color film substrate area and the adjacent sub color film substrate area; the at least one planarization layer comprises a plurality of disconnected first sub-planarization layers; and the spacing region between the adjacent first sub-planarization layers is positioned at the gap between at least part of the adjacent sub-color film substrate regions. By adopting the technical scheme, the flattening layer arranged on the whole surface is arranged into the plurality of first sub-flattening layers which are not mutually connected, so that the stress generated by contraction of the flattening layer in the curing process is released through the gap between the connected first sub-flattening layers, and the problem that the first substrate base plate is warped due to the stress acting on the first substrate base plate is avoided; in addition, the spacing area between the connected first sub-planarization layers is positioned in the gap between at least part of the sub-color film substrate areas, so that the stability between the films in the sub-color film substrate areas is ensured, and the display performance of the display panel is improved after the display panel is formed subsequently.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 3 is a schematic structural diagram of a color filter substrate mother board according to an embodiment of the present invention, fig. 4 is a cross-sectional view along a BB' direction in fig. 3, and fig. 5 is a schematic structural diagram of a planarization layer according to an embodiment of the present invention, as shown in fig. 3, fig. 4, and fig. 5, a color filter substrate mother board 100 according to an embodiment of the present invention includes: a first substrate base plate 10; the first substrate base plate 10 includes a plurality of sub color film base plate regions CC arranged in an array; a plurality of light-shielding layers 20 and a plurality of planarization layers 30 on the first substrate 10; the light shielding layer 20 and the planarization layer 30 are stacked and spaced apart in a direction perpendicular to the first base substrate 10; the shading layer 20 is positioned in the sub color film substrate area CC; the planarization layer 30 is located in a gap DD between the color sub-film substrate area CC and the adjacent color sub-film substrate area CC; the at least one planarization layer 30 includes a plurality of unconnected first sub-planarization layers 311; the spacing region EE between adjacent first sub-planarization layers 311 is located at the gap DD between at least part of adjacent sub-color film substrate regions CC.
Specifically, at least one planarization layer 30 arranged on the whole surface is arranged into a plurality of first sub-planarization layers 311 which are not connected with each other, when the planarization layer 30 is cured through a thermal process, stress generated by shrinkage of the planarization layer 30 is released through a gap area EE between adjacent first sub-planarization layers 311, so that the problem that the first substrate 10 is warped due to the stress acting on the first substrate 10 is avoided, and the production yield of the color film substrate mother board 100 is improved; in addition, the space EE between the adjacent first sub-planarization layers 311 is located in the gap DD between at least part of the sub-color film substrate regions CC, so that the stability between the films in the sub-color film substrate regions CC is ensured, and the display performance of the display panel is improved after the display panel is formed subsequently.
Illustratively, as shown in fig. 3, 4 and 5, the planarization layer 30 includes a first planarization layer 31, a second planarization layer 32 and a third planarization layer 33, and accordingly, the light-shielding layer 20 is also three-layered. Wherein the first planarizing layer 31 includes a plurality of first sub-planarizing layers 311 which are not connected to each other, and the second planarizing layer 32 and the third planarizing layer 33 are disposed in an entire layer. Since the first sub-planarization layers 311 that are not connected to each other have the gaps EE, when the thermal process cures the first planarization layer 31, the stress generated by the shrinkage of the first planarization layer 31 is released through the gap regions EE between the adjacent first sub-planarization layers 311.
It should be noted that fig. 3, 4 and 5 only show that one planarization layer 30 is provided as the plurality of first sub-planarization layers 311, but the present application is not limited thereto, and those skilled in the art can determine the present invention according to actual situations; in other alternative embodiments, two planarization layers 30 or three planarization layers 30 may be provided as a plurality of first sub-planarization layers 311. It is understood that the greater the number of the planarization layers 30 provided as the plurality of first sub-planarization layers 311, the more the problem of warping of the first substrate base plate 10 can be alleviated.
It should be noted that, as shown in fig. 3, fig. 4 and fig. 5, in the embodiments, only a part of the film structures in the color film substrate motherboard 100 are shown, and the film structures do not represent actual sizes.
Optionally, the first substrate 10 has a supporting and protecting effect on other film layers in the color filter substrate mother board 100, and then each film layer of the color filter substrate mother board 100 is formed on the first substrate 10. Alternatively, the first substrate 10 may be a rigid substrate or a flexible substrate; the rigid substrate may be glass, and the flexible substrate may be polyimide, which is not limited herein.
Optionally, the light shielding layer 20 located in the color filter substrate area CC includes a plurality of collimating hole units 40, the light shielding layer 20 is configured to shield light, so as to prevent color mixing between adjacent sub-pixels in the color filter substrate area CC, meanwhile, the collimating hole 40 formed on each light shielding layer 20 is configured to provide a channel for light reflected back by the touch subject, so that the reflected light carrying fingerprint information can be received by the light sensor, and the opening structure FF formed on each light shielding layer 20 is configured to transmit light, so that light emitted by the backlight source can be received by human eyes through a color filter substrate subsequently formed by the color filter substrate motherboard 100.
Alternatively, the material of the light shielding layer 20 may include a black resin or other light shielding materials known to those skilled in the art, and is not limited herein. The planarization layer 30 functions to provide a flat surface. The material of the planarization layer 30 may include a transparent resin or other transparent insulating material known to those skilled in the art, and is not limited thereto. Optionally, the material of the planarization layer 30 may be, for example, a transparent photosensitive material, so that the first sub-planarization layer 311 may be formed by using an exposure and development process, the process steps are simple, and the manufacturing efficiency is improved.
In summary, in the color film substrate motherboard provided in the embodiment of the present invention, the planarization layer disposed on the entire surface is set as the plurality of first sub-planarization layers that are not connected to each other, so that the stress generated by shrinkage of the planarization layer in the curing process is released through the gap between the connected first sub-planarization layers, and the problem of warpage of the first substrate caused by the stress acting on the first substrate is avoided; in addition, the spacing area between the connected first sub-planarization layers is positioned in the gap between at least part of the sub-color film substrate areas, so that the stability between the films in the sub-color film substrate areas is ensured, and the display performance of the display panel is improved after the display panel is formed subsequently.
Optionally, fig. 6 is a schematic structural diagram of another planarization layer provided in the embodiment of the present invention, and as shown in fig. 6, the first sub-planarization layers 311 are arranged along a row direction of the color sub-film substrate area CC in an array arrangement. The row-direction stress generated by shrinkage when the planarization layer 30 is cured by the thermal process is released through the gaps EE between the adjacent first sub-planarization layers 311 arranged in the row direction of the array arrangement, thereby avoiding the problem that the first substrate base plate 10 is warped due to the stress acting on the first substrate base plate 10.
Optionally, fig. 7 is a schematic structural diagram of another planarization layer provided in an embodiment of the present invention, and as shown in fig. 7, the first sub-planarization layers 311 are arranged along the column direction of the array arrangement of the sub-color film substrate regions CC. The column-direction stress generated by shrinkage when the planarization layer 30 is cured by the thermal process is released through the gaps EE between the adjacent first sub-planarization layers 311 arranged in the column direction of the array arrangement, thereby avoiding the problem that the first substrate base plate 10 is warped due to the stress acting on the first substrate base plate 10.
Optionally, fig. 8 is a schematic structural diagram of another color filter substrate mother board according to an embodiment of the present invention, and as shown in fig. 8, the first sub planarization layer 311 is arranged along a row direction and a column direction of the color filter substrate CC array. The row-direction and column-direction stresses generated by shrinkage when the planarization layer 30 is cured by the thermal process are released through the gaps EE between the adjacent first sub-planarization layers 311 arranged in the row direction of the array arrangement and through the gaps EE between the adjacent first sub-planarization layers 311 arranged in the column direction of the array arrangement, respectively, so that the problem that the first substrate 10 is warped due to the row-direction and column-direction stresses acting on the first substrate 10 is further avoided.
Optionally, fig. 9 is a schematic diagram of a film structure of a color filter substrate mother board according to an embodiment of the present invention, and as shown in fig. 9, vertical projections of the first sub-planarization layers 311 in the planarization layers 30 of different layers on the plane of the first substrate 10 are overlapped.
Specifically, by respectively disposing the planarization layers 30 of different layers as the plurality of first sub-planarization layers 311 that are not connected to each other, the problem of warping of the first substrate 10 can be further avoided; in addition, because the vertical projections of the first sub-planarization layers 311 in the planarization layers 30 of different layers on the plane where the first substrate base plate 10 is located are overlapped, that is, the shapes of the first sub-planarization layers 311 in the planarization layers 30 of different layers are completely the same, that is, when the planarization layers 30 of different layers are prepared, if the exposure and development process is adopted, the same mask plate can be adopted without separately manufacturing the mask plate, so that the number of the mask plates used in the preparation process of the color film base plate 100 can be reduced, the process cost is reduced, the process steps are simplified, and the preparation efficiency is improved.
Based on the same inventive concept, the embodiment of the invention also provides a display panel motherboard. Fig. 10 is a schematic structural diagram of a display panel motherboard according to an embodiment of the present invention, and as shown in fig. 10, the display panel motherboard includes: the color film substrate mother board 100 provided in any of the embodiments above; the array substrate mother board 200 is arranged opposite to the color film substrate mother board 100; the liquid crystal layer 300 is positioned between the array substrate mother board 200 and the color film substrate mother board 100; the array substrate motherboard 200 includes a second substrate 210, and the second substrate 210 includes a plurality of sub-array substrate regions MM arranged in an array; the sub-array substrate areas MM correspond to the sub-color film substrate areas CC one by one; the sub color film substrate area CC is provided with a color film substrate, and the sub array substrate area MM is provided with an array substrate.
For example, the sealant 400 is coated around the sub color film substrate region CC of the color film substrate mother board 100, liquid crystal may be dropped in the center of the sub array substrate region MM of the array substrate mother board 200 by using a dropping injection method, then the color film substrate mother board 100 and the array substrate mother board 200 are subjected to an assembly process, and finally the sealant 400 is cured to form the display panel mother board. Because the planarization layer 30 in the color filter substrate mother board 100 includes the plurality of first sub-planarization layers 311, when the planarization layer 30 is cured by the thermal process, the stress generated by shrinkage of the planarization layer 30 is released through the gap area EE between the adjacent first sub-planarization layers 311, the problem that the first substrate 10 is warped due to the stress acting on the first substrate 10 is avoided, and the production yield of the color filter substrate mother board 100 is improved, so that when the color filter substrate mother board 100 and the array substrate mother board 200 are subsequently assembled, the problem that the surface of the color filter substrate mother board 100 facing the array substrate mother board 200 is uneven at the corners due to warping of the first substrate 10 and the problem that the yield of the display panel mother board is affected are avoided.
Based on the same inventive concept, an embodiment of the present invention further provides a display panel, where the display panel is formed by cutting along the cutting line of the mother board of the display panel provided in any of the above embodiments, and a vertical projection of the cutting line on a plane where the first substrate base board is located in a vertical projection of a gap between adjacent sub color film base board regions on the plane where the first substrate base board is located. Fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 11, the display panel 1100 includes an array substrate 1200, a color filter substrate 1300, and a liquid crystal layer 400.
On the basis of the foregoing solution, optionally, fig. 12 is a schematic structural diagram of another display panel provided in the embodiment of the present invention, and as shown in fig. 12, a color film substrate 1300 includes a first sub-substrate 1310; further comprising: a multilayer light-shielding layer 20 and a multilayer first sub-planarization layer 311; the plurality of light shielding layers 20 are provided with collimation through holes 40, and the vertical projections of the collimation through holes 40 on the light shielding layers 20 on the first sub-substrate 1310 are superposed; the light-shielding layer 20 further includes an opening structure FF; the color film substrate 1300 further includes a color resist layer 1320; the color resist layer 1320 includes a plurality of color resist blocks 1330 of different colors; the vertical projection of the color blocking block 1330 on the first sub-substrate 1310 is located within the vertical projection of the opening structure FF on the first sub-substrate 1310; the at least one first sub-planarization layer 311 includes a plurality of second sub-planarization layers 3110 that are not connected to each other, and the spacers NN between the adjacent second sub-planarization layers 3110 are also located in the spacers LL between at least some of the adjacent color resist blocks 1330; and/or fig. 13 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 13, at least one light shielding layer 20 includes a plurality of sub-light shielding layers 21 that are not connected to each other, and the spacers OO between adjacent sub-light shielding layers 21 are located in the spacers LL between at least some of the adjacent color-resist blocks 1330.
Specifically, there are various ways that the at least one first sub-planarization layer 311 includes a plurality of unconnected second sub-planarization layers 3110 and/or the at least one light-shielding layer 20 includes a plurality of unconnected sub-light-shielding layers 21, for example, as shown in fig. 12, wherein one first sub-planarization layer 311 includes a plurality of unconnected second sub-planarization layers 3110, when the layer of first sub-planarization layer 311 is cured by a thermal process, the stress generated by the shrinkage of the layer of first sub-planarization layer 311 is released through the NN between the adjacent second sub-planarization layers 3110 and does not act on the first sub-substrate 1310. As shown in fig. 13, one of the light-shielding layers 20 includes a plurality of sub-light-shielding layers 21 that are not connected to each other, and when the light-shielding layer 20 is cured by a thermal process, stress generated by shrinkage of the light-shielding layer 20 is released through the spaces OO between adjacent sub-light-shielding layers 21. As shown in fig. 14, one of the light-shielding layers 20 includes a plurality of unconnected sub-light-shielding layers 21 and one of the first sub-planarization layers 311 includes a plurality of unconnected second sub-planarization layers 3110, so that not only the stress generated by shrinkage when the thermal process cures the first sub-planarization layer 311, but also the stress generated by shrinkage when the thermal process cures the light-shielding layer 20 can be released, which is further beneficial to reducing the stress generated by thermal process curing acting on the first sub-substrate 1310, resulting in the problem of warpage of the first sub-substrate 1310, and is beneficial to improving the production yield 1310 of the display panel 100.
It should be noted that the above examples do not limit the present application, and those skilled in the art can determine the present application according to actual situations.
Referring to fig. 12, when at least one first sub-planarization layer 311 includes a plurality of second sub-planarization layers 3110 that are not connected to each other, and the spacers NN between the adjacent second sub-planarization layers 3110 are also located in the spacers LL between at least some of the adjacent color resist blocks 1330, when the first sub-planarization layer 311 is fabricated on the side away from the first sub-substrate 1310, the light shielding layer 20 is also located in the spacers NN between the adjacent second sub-planarization layers 3110, so that the light shielding layer 20 can not only shield the front light, i.e., the light in the direction perpendicular to the first sub-substrate 1310, but also shield the side light, and thus, the light shielding effect of the light shielding layer 20 is improved.
It is understood that the first sub-planarization layer 311 and the second sub-planarization layer 3110 are simultaneously formed when the display panel mother substrate is prepared.
Optionally, with continued reference to fig. 12, the array substrate 1200 includes a second sub-substrate 1210, a photosensor 1220, and a light-shielding layer 20; the light-shielding layer 20 on the array substrate 1200 is located on one side of the second sub-substrate 1210 facing the color film substrate 1300, and the photosensor 1220 is located between the second sub-substrate 1210 and the light-shielding layer 20; the light shielding layer 20 on the array substrate 1200 is also provided with collimation through holes 40, and the vertical projections of the collimation through holes 40 on the second sub-substrate 1210 are overlapped; the perpendicular projection of photo sensor 1220 on second sub-substrate base 1210 is located within the perpendicular projection of collimating via 40 on second sub-substrate base 1210.
Optionally, the light-shielding layer 20 on the array substrate 1200 may also include a plurality of sub-light-shielding layers (not shown) that are not connected to each other, so as to release the stress generated by the shrinkage of the light-shielding layer during the thermal process.
Optionally, a driving circuit 90 is disposed on a side of the second sub-substrate 1210 facing the color filter substrate 1300, and the driving circuit 90 includes a thin film transistor (not shown) to control the display of the display panel 1100.
Optionally, when the driving circuit 90 includes a thin film transistor, the light sensor 1220 is simultaneously fabricated, that is, the light sensor 1200 may also be formed by reusing a portion of the film layer formed by the original display panel, so as to reduce the overall thickness of the display panel 1100 while reducing the process.
Alternatively, the color resist layer 1320 may include a red color resist block R, a green color resist block G, a blue color resist block B, and other types of color resist blocks known to those skilled in the art, which are not limited herein, wherein each color resist block 1300 corresponds to one sub-pixel. The light passing through the liquid crystal layer 400 is filtered by the color resist block 1300, so that each sub-pixel has a fixed color. The display panel 1100 applies a voltage to the pixel electrode and the common electrode through the driving circuit 90 in the array substrate 1210, so as to drive the liquid crystal molecules to deflect, thereby realizing that light emitted by the backlight passes through the array substrate, is refracted out of the liquid crystal layer, and forms a color picture under the filtering action of the color resist 1330 of the color filter substrate 1300.
Optionally, fig. 15 is a schematic structural diagram of a light shielding layer according to an embodiment of the present invention, and as shown in fig. 15, the sub-light shielding layers 21 are arranged along a row direction of the color block array. The line-direction stress generated by shrinkage when the light shielding layer 20 is cured by the thermal process is released through the gaps OO between the adjacent light shielding sub-layers 21 arranged along the line direction, and the problem that the first sub-substrate is warped due to the stress acting on the first sub-substrate is avoided.
Optionally, fig. 16 is a schematic structural diagram of a light-shielding layer according to an embodiment of the present invention, and as shown in fig. 16, the sub-light-shielding layers 21 are arranged along the column direction of the color block array. The column-direction stress generated by shrinkage when the light shielding layer 20 is cured by the thermal process is released through the gaps OO between the adjacent light shielding sub-layers 21 arranged in the column direction, and the problem that the first sub-substrate is warped due to the stress acting on the first sub-substrate is avoided.
Optionally, fig. 17 is a schematic structural diagram of a light shielding layer according to an embodiment of the present invention, and as shown in fig. 17, the sub-light shielding layers 21 are arranged along a row direction and a column direction of the color block array. The row-direction and column-direction stresses generated by shrinkage when the light shielding layer 20 is cured by the thermal process are released through the gaps OO between the adjacent sub-light shielding layers 21 arranged in the row direction and through the gaps OO between the adjacent sub-light shielding layers 21 arranged in the column direction, respectively, so that the problem that the first sub-substrate is warped due to the action of the row-direction and column-direction stresses on the first sub-substrate is further avoided.
Optionally, with continued reference to fig. 13, the vertical projection of the multi-layer light-shielding layer 20 on the first sub-substrate 1310 covers the vertical projection of the gap FF between the color-resist blocks 1330 on the first sub-substrate 1310.
Considering that, when the light shielding layer 20 includes a plurality of sub-light shielding layers 21 that are not connected to each other, since the gaps OO are formed between the adjacent sub-light shielding layers 21, color mixing between the adjacent sub-pixels may occur through the gaps OO, the present embodiment avoids the problem of color mixing between the adjacent sub-pixels by the vertical projection of the multi-light shielding layer 20 on the first sub-substrate 1310 to cover the vertical projection of the gaps FF between the color blocking blocks 1330 on the first sub-substrate 1310, that is, the cooperation of the multi-light shielding layers.
Optionally, fig. 18 is a schematic structural diagram of the first sub-planarization layer provided in the embodiment of the present invention, and as shown in fig. 18, the second sub-planarization layer 3110 is arranged along the row direction and/or the column direction of the color resist block array.
Specifically, the row-direction and/or column-direction stress generated by shrinkage when the thermal process cures the first sub-planarization layer 311 is released through the gaps NN between the adjacent second sub-planarization layers 3110 arranged in the row direction and/or through the gaps NN between the adjacent second sub-planarization layers 3110 arranged in the column direction.
It should be noted that fig. 18 is only an example in which the second sub-planarization layer 3110 is arranged in the row direction and the column direction of the color resist block array.
Optionally, with continued reference to fig. 18, when at least one of the first sub-planarization layers 311 includes a plurality of second sub-planarization layers 3110 that are not connected to each other, and the space OO between adjacent second sub-planarization layers 3110 is also located in the space between at least some of the adjacent color resist blocks, the second sub-planarization layer 3110 further includes at least one first hollow structure SS; the vertical projection of the first hollow structure SS on the plane of the first sub-substrate base plate is not overlapped with the vertical projection of the spacing area between the adjacent color block blocks on the plane of the first sub-substrate base plate; the stress generated by shrinkage when the thermal process solidifies the first sub-planarization layer 311 is further released through the first hollow structure SS.
With reference to fig. 15, when at least one of the light-shielding layers 20 includes a plurality of sub-light-shielding layers 21 that are not connected to each other, and the spacing OO between adjacent sub-light-shielding layers 21 is located in the spacing between at least some of the adjacent color resist blocks, the sub-light-shielding layers 21 further include at least one second hollow-out structure TT; the vertical projection of the second hollow structure TT on the plane of the first sub-substrate base plate and the vertical projection of the spacing area between the adjacent color resistance blocks on the plane of the first sub-substrate base plate are not overlapped, and the stress generated by shrinkage when the shading layer 20 is cured by a thermal process is further released through the first hollow structure SS.
Based on the same inventive concept, the embodiment of the invention also provides a display device which comprises the display panel of any embodiment of the invention. Fig. 19 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 19, a display device 1000 according to an embodiment of the present invention includes the display panel 1100 according to the above embodiment, and because a principle of solving a problem of the display device is similar to that of the display panel according to the above embodiment, reference may be made to the embodiment of the display panel according to the embodiment of the display device 1000, and repeated details are not repeated. For example, the display device 1000 may be an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and an in-vehicle display device, which is not limited in this embodiment of the invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (11)
1. A color film substrate mother board is characterized by comprising:
a first substrate base plate; the first substrate base plate comprises a plurality of sub color film base plate areas which are arranged in an array mode;
a plurality of light-shielding layers and a plurality of planarization layers on the first substrate;
the light shielding layer and the planarization layer are stacked and arranged at intervals along a direction perpendicular to the first substrate; the shading layer is positioned in the sub color film substrate area; the planarization layer is positioned in a gap between the sub color film substrate area and the adjacent sub color film substrate area;
at least one of the planarization layers comprises a plurality of unconnected first sub-planarization layers; and the spacing region between the adjacent first sub-planarization layers is positioned at the gap between at least part of the adjacent sub-color film substrate regions.
2. The color filter substrate mother board according to claim 1, wherein the first sub planarization layers are arranged in a row direction and/or a column direction of the array arrangement of the sub color filter substrate regions.
3. The color filter substrate mother board according to claim 1, wherein vertical projections of the first sub-planarization layers in the planarization layers of different layers on a plane where the first substrate is located coincide.
4. A display panel motherboard, comprising:
the color filter substrate mother board according to any one of claims 1 to 3;
the array substrate mother board is arranged opposite to the color film substrate mother board;
the liquid crystal layer is positioned between the array substrate mother board and the color film substrate mother board;
the array substrate motherboard comprises a second substrate, and the second substrate comprises a plurality of sub-array substrate areas arranged in an array; the sub array substrate areas correspond to the sub color film substrate areas one by one; the sub color film substrate area is provided with a color film substrate, and the sub array substrate area is provided with an array substrate.
5. A display panel formed by cutting along a cutting line of the mother substrate of the display panel according to claim 4;
the vertical projection of the cutting line on the plane of the first substrate base plate is positioned in the vertical projection of the gap between the adjacent sub color film base plate areas on the plane of the first substrate base plate; the display panel comprises the array substrate, the color film substrate and the liquid crystal layer.
6. The display panel according to claim 5, wherein the color filter substrate comprises a first sub-substrate;
further comprising: a plurality of the light-shielding layers and a plurality of the first sub-planarization layers;
the plurality of light shielding layers are provided with collimation through holes, and the vertical projections of the collimation through holes on the light shielding layers on the first sub-substrate are superposed;
the light shielding layer further comprises an opening structure; the color film substrate further comprises a color resistance layer; the color resistance layer comprises a plurality of color resistance blocks with different colors; the vertical projection of the color block on the first sub-substrate base plate is positioned in the vertical projection of the opening structure on the first sub-substrate base plate;
at least one first sub-planarization layer comprises a plurality of second sub-planarization layers which are not connected with each other, and a spacer between the adjacent second sub-planarization layers is also positioned in a spacer between at least partial adjacent color block; and/or at least one layer of the shading layer comprises a plurality of shading sub-layers which are not mutually connected, and the interval between the adjacent shading sub-layers is positioned in the interval between at least partial adjacent color blocking blocks.
7. The display panel according to claim 6,
the sub-shading layers are arranged along the row direction and/or the column direction of the color resistance block array arrangement.
8. The display panel according to claim 7, wherein a vertical projection of the plurality of light-shielding layers on the first sub-substrate covers a vertical projection of a gap between the color resist blocks on the first sub-substrate.
9. The display panel according to claim 6, wherein the second sub-planarization layer is arranged along a row direction and/or a column direction of the color resist array arrangement.
10. The display panel according to claim 6, wherein when at least one of the first sub-planarization layers comprises a plurality of second sub-planarization layers that are not connected to each other, and the spacers between the adjacent second sub-planarization layers are further located in the spacers between at least some of the adjacent color resist blocks, the second sub-planarization layers further comprise at least one first hollow structure; the vertical projection of the first hollow structure on the plane of the first sub-substrate base plate is not overlapped with the vertical projection of the spacing area between the adjacent color resistance blocks on the plane of the first sub-substrate base plate;
when at least one layer of the light shielding layer comprises a plurality of unconnected sub light shielding layers, and the interval area between the adjacent sub light shielding layers is positioned in the interval area between at least partial adjacent color blocking blocks, the sub light shielding layer further comprises at least one second hollow structure; the vertical projection of the second hollow structure on the plane of the first sub-substrate base plate is not overlapped with the vertical projection of the spacing area between the adjacent color resistance blocks on the plane of the first sub-substrate base plate.
11. A display device characterized by comprising the display panel according to any one of claims 5 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010620916.2A CN111708213A (en) | 2020-06-30 | 2020-06-30 | Color film substrate mother board, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010620916.2A CN111708213A (en) | 2020-06-30 | 2020-06-30 | Color film substrate mother board, display panel and display device |
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| Publication Number | Publication Date |
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| CN111708213A true CN111708213A (en) | 2020-09-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010620916.2A Withdrawn CN111708213A (en) | 2020-06-30 | 2020-06-30 | Color film substrate mother board, display panel and display device |
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| CN (1) | CN111708213A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078190A (en) * | 2021-03-19 | 2021-07-06 | 厦门天马微电子有限公司 | Display panel and display device |
-
2020
- 2020-06-30 CN CN202010620916.2A patent/CN111708213A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078190A (en) * | 2021-03-19 | 2021-07-06 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113078190B (en) * | 2021-03-19 | 2022-08-23 | 厦门天马微电子有限公司 | Display panel and display device |
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