CN111684426B - 多节点系统低功率管理 - Google Patents

多节点系统低功率管理 Download PDF

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Publication number
CN111684426B
CN111684426B CN201880088614.6A CN201880088614A CN111684426B CN 111684426 B CN111684426 B CN 111684426B CN 201880088614 A CN201880088614 A CN 201880088614A CN 111684426 B CN111684426 B CN 111684426B
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node
processing node
processing
response
nodes
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Chinese (zh)
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CN111684426A (zh
Inventor
本杰明·特西恩
布赖恩·P·布鲁萨尔
维德希亚纳坦·卡利亚纳孙达拉姆
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
CN201880088614.6A 2017-12-21 2018-09-19 多节点系统低功率管理 Active CN111684426B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/850,261 2017-12-21
US15/850,261 US10671148B2 (en) 2017-12-21 2017-12-21 Multi-node system low power management
PCT/US2018/051789 WO2019125562A1 (en) 2017-12-21 2018-09-19 Multi-node system low power management

Publications (2)

Publication Number Publication Date
CN111684426A CN111684426A (zh) 2020-09-18
CN111684426B true CN111684426B (zh) 2024-11-05

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CN201880088614.6A Active CN111684426B (zh) 2017-12-21 2018-09-19 多节点系统低功率管理

Country Status (6)

Country Link
US (1) US10671148B2 (enExample)
EP (1) EP3729233B1 (enExample)
JP (1) JP6984022B2 (enExample)
KR (1) KR102355989B1 (enExample)
CN (1) CN111684426B (enExample)
WO (1) WO2019125562A1 (enExample)

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CN112612726B (zh) * 2020-12-08 2022-09-27 海光信息技术股份有限公司 基于缓存一致性的数据存储方法、装置、处理芯片及服务器
US11620248B2 (en) * 2021-03-31 2023-04-04 Advanced Micro Devices, Inc. Optical bridge interconnect unit for adjacent processors
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US11487340B1 (en) * 2021-06-24 2022-11-01 Advanced Micro Devices, Inc. Probe filter retention based low power state
US11989144B2 (en) * 2021-07-30 2024-05-21 Advanced Micro Devices, Inc. Centralized interrupt handling for chiplet processing units
CN114490194B (zh) * 2022-04-19 2022-07-01 海光信息技术股份有限公司 掉电处理方法、功能节点、处理系统、设备和存储介质
CN115269466A (zh) * 2022-07-29 2022-11-01 联想(北京)有限公司 一种电子设备及控制方法
US12050535B2 (en) * 2022-10-31 2024-07-30 Google Llc Dynamic migration of point-of-coherency and point-of-serialization in NUMA coherent interconnects
CN119292749B (zh) * 2024-10-29 2025-08-22 北京奕斯伟计算技术股份有限公司 集成电路、处理中断请求的方法及系统

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Also Published As

Publication number Publication date
JP2021507412A (ja) 2021-02-22
KR20200100152A (ko) 2020-08-25
WO2019125562A1 (en) 2019-06-27
CN111684426A (zh) 2020-09-18
EP3729233B1 (en) 2025-08-06
JP6984022B2 (ja) 2021-12-17
US20190196574A1 (en) 2019-06-27
US10671148B2 (en) 2020-06-02
EP3729233A1 (en) 2020-10-28
KR102355989B1 (ko) 2022-02-08

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