CN111682058B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN111682058B CN111682058B CN202010653194.0A CN202010653194A CN111682058B CN 111682058 B CN111682058 B CN 111682058B CN 202010653194 A CN202010653194 A CN 202010653194A CN 111682058 B CN111682058 B CN 111682058B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
Abstract
The invention relates to the technical field of display, and provides a display panel and a display device. The first data lines extend along the column direction and are positioned at two sides of the openings along the row direction; the second data line extends along the column direction and is positioned on the first side of the opening along the column direction; the third data line extends along the column direction and is positioned on the second side of the opening along the column direction; each second data line is connected with the first data line through a connecting line; and the source electrode driving circuit is connected with the third data line and the first data line and is used for providing data signals for the first data line, the second data line and the third data line. The display panel does not need to arrange data lines at the periphery of the opening, so that the technical problem that the opening frame is wide is solved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
AA Hole (display area punching) technology is a device in which a light-transmitting opening is formed in a display area of a display panel so as to dispose a camera in the opening. The technology can enable the display panel to be free from frames used for integrating equipment such as a camera and the like, so that the comprehensive screen effect can be truly realized. However, a frame region for integrating signal lines such as gate lines and data lines needs to be reserved around the opening, so that the width of a black frame around the opening is large, and the display effect is affected.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present invention and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a display panel and a display device, wherein the display panel can solve the technical problem that the width of a black frame at the position of an opening of a display area is large.
Other features and advantages of the invention will be apparent from the following detailed description, or may be learned by practice of the invention.
According to an aspect of the present invention, there is provided a display panel including a display area provided with an opening, the display panel further including: the display device comprises a plurality of sub-pixel units, a plurality of first data lines, a plurality of second data lines, a plurality of third data lines and a source electrode driving circuit. A plurality of the sub-pixel units are distributed along rows and columns; the plurality of first data lines extend along the column direction and are connected with the sub-pixel units in the same column, and the first data lines are positioned on two sides of the open holes along the row direction; the plurality of second data lines extend along the column direction, are positioned on the first side of the opening along the column direction, and are connected with the sub-pixel units in the same column positioned on the first side of the opening along the column direction; the plurality of third data lines extend along the column direction, are positioned at the second side of the opening along the column direction, and are connected with the sub-pixel units in the same column positioned at the second side of the opening along the column direction; each second data line is connected with the first data line through a connecting line; the source electrode driving circuit is connected with the third data line and the first data line and is used for providing data signals for the first data line, the second data line and the third data line.
In an exemplary embodiment of the present disclosure, the display panel further includes a plurality of first gate lines, a plurality of second gate lines, a plurality of third gate lines, a first gate driving circuit, and a second gate driving circuit. The first grid lines extend along the row direction and are positioned at two sides of the openings along the column direction; the plurality of second grid lines extend along the row direction, are positioned on the first side of the opening along the row direction, and are connected with the sub-pixel units in the same row on the first side of the opening along the row direction; a plurality of third grid lines extend along the row direction, are positioned at the second side of the opening along the row direction and are connected with the sub-pixel units in the same row at the second side of the opening along the row direction; the first grid driving circuit is connected with the first end of the first grid line and the second grid line and is used for providing a grid driving signal for the first grid line and the second grid line; the second grid driving circuit is connected with the second end of the first grid line and the third grid line and is used for providing a grid driving signal for the first grid line and the third grid line; the time sequence of the gate driving signals provided by the first gate driving circuit and the second gate driving circuit to the sub-pixel units in the same row is the same.
In an exemplary embodiment of the present disclosure, the second data lines are connected to the first data lines in a one-to-one correspondence; or, a plurality of second data lines are correspondingly connected with one first data line.
In an exemplary embodiment of the present disclosure, the display panel includes a frame area located around the display area, and the connection line is located in the frame area; or, the connecting line is located in the display area and is respectively connected with the first data line and the second data line through via holes.
In an exemplary embodiment of the present disclosure, a cross-sectional area of the second data line is greater than a cross-sectional area of the third data line.
In an exemplary embodiment of the present disclosure, the display panel further includes: a substrate and a conductive layer. The third data line is positioned on one side of the substrate base plate; the conducting layer is located on one side, facing the third data line, of the substrate base plate, and the orthographic projection of the conducting layer on the substrate base plate is at least partially overlapped with the orthographic projection of the third data line on the substrate base plate.
In one exemplary embodiment of the present disclosure, the plurality of sub-pixel units includes a first sub-pixel unit connected to the second data line and a second sub-pixel unit connected to the first data line and the third data line; the first sub-pixel unit includes a first pixel driving circuit including: the driving circuit comprises a first data writing circuit, a first driving circuit, a first light-emitting control circuit, a first reset circuit and a first capacitor. The first data writing circuit is connected with a first data signal end, a first node and a first reset signal end and used for responding to a signal of the first reset signal end to transmit a signal of the first data signal end to the first node; the first driving circuit is connected with a first power supply end, the first node and a second node and is used for inputting driving current to the second node according to a signal of the first node; the first light-emitting control circuit is connected with the second node, the light-emitting unit and a first enabling signal terminal and is used for responding to the signal of the first enabling signal terminal to transmit the signal of the second node to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected with a second power supply terminal; the first reset circuit is connected with the first reset signal terminal, the first initialization signal terminal and the second node and used for responding to the signal of the first reset signal terminal and transmitting the signal of the first initialization signal terminal to the second node; a first capacitor is connected between the first power supply terminal and the first node. The second sub-pixel unit includes a second pixel driving circuit including: the second data write circuit, the second drive circuit, the second luminescence control circuit, the compensation circuit, the second reset circuit and the second capacitor. The second data writing circuit is connected with a second data signal end, a third node and a grid driving signal end and is used for responding to a signal of the grid driving signal end and transmitting a signal of the second data signal end to the third node; the second driving circuit is connected with the third node, the fourth node and the fifth node and is used for inputting driving current to the fourth node according to a signal of the fifth node; the second light-emitting control circuit is connected with the first power supply end, the third node, the second enable signal end, the fourth node and the light-emitting unit, and is used for responding to the signal of the second enable signal end to transmit the signal of the first power supply end to the third node and responding to the signal of the second enable signal end to transmit the signal of the fourth node to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected with the second power supply end; the compensation circuit is connected with the fourth node, the fifth node and the grid driving signal end and is used for responding to the signal of the grid driving signal end to communicate the fourth node and the fifth node; the second reset circuit is connected with the fifth node, the reference voltage terminal, the second reset signal terminal, the first pole of the first light-emitting unit and the second initialization signal terminal, and is used for responding to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the fifth node and responding to the signal of the second reset signal terminal to transmit the signal of the second initialization signal terminal to the first pole of the first light-emitting unit; the second capacitor is connected between the first power supply end and the fifth node; the first reset signal end in the first sub-pixel unit and the second reset signal end in the second sub-pixel unit positioned on the same row are connected with the first grid line together, and the second reset signal end in the second sub-pixel unit and the grid driving signal end of the second sub-pixel unit positioned on the upper row are connected with the first grid line or the second grid line or the third grid line together.
In an exemplary embodiment of the present disclosure, the first data writing circuit includes a first transistor, a first pole of the first transistor is connected to the first data signal terminal, a second pole of the first transistor is connected to the first node, and a gate of the first transistor is connected to the first reset signal terminal. The first driving circuit comprises a first driving transistor, a first electrode of the first driving transistor is connected with the first power supply end, a second electrode of the first driving transistor is connected with the second node, and a grid electrode of the first driving transistor is connected with the first node. The first light-emitting control circuit comprises a second transistor, wherein the first pole of the second transistor is connected with the second node, the second pole of the second transistor is connected with the light-emitting unit, and the grid of the second transistor is connected with the first enabling signal end. The first reset circuit comprises a third transistor, wherein the first pole of the third transistor is connected with the first initialization signal end, the second pole of the third transistor is connected with the second node, and the grid electrode of the third transistor is connected with the first reset signal end.
In an exemplary embodiment of the present disclosure, the second data writing circuit includes a fourth transistor, a first pole of the fourth transistor is connected to the second data signal terminal, a second pole of the fourth transistor is connected to the third node, and a gate of the fourth transistor is connected to the gate driving signal terminal. The second driving circuit comprises a second driving transistor, a first pole of the second driving transistor is connected with the third node, a second pole of the second driving transistor is connected with the fourth node, and a grid electrode of the second driving transistor is connected with the fifth node. The second light-emitting control circuit comprises a fifth transistor and a sixth transistor, wherein the first pole of the fifth transistor is connected with the first power supply end, the second pole of the fifth transistor is connected with the third node, and the grid of the fifth transistor is connected with the second enable signal end; and a first pole of the sixth transistor is connected with the fourth node, a second pole of the sixth transistor is connected with the light-emitting unit, and a grid of the sixth transistor is connected with the second enabling signal end. The compensation circuit comprises a seventh transistor, wherein the first pole of the seventh transistor is connected with the fourth node, the second pole of the seventh transistor is connected with the fifth node, and the grid of the seventh transistor is connected with the grid driving signal end. The second reset circuit comprises an eighth transistor and a ninth transistor, wherein the first pole of the eighth transistor is connected with the reference voltage end, the second pole of the eighth transistor is connected with the fifth node, and the grid of the eighth transistor is connected with the second reset signal end; a first pole of the ninth transistor is connected to the second initialization signal terminal, a second pole of the ninth transistor is connected to a second pole of the sixth transistor, and a gate of the ninth transistor is connected to the second reset signal terminal.
According to an aspect of the present invention, there is provided a display device including the display panel described above.
The present disclosure provides a display panel and a display device, where the display panel includes a display area, the display area is provided with a hole, and the display panel further includes a plurality of sub-pixel units distributed along rows and columns, a plurality of first data lines, a plurality of second data lines, a plurality of third data lines, and a source driving circuit. The first data lines extend along the column direction and are positioned at two sides of the openings along the row direction; the second data line extends along the column direction and is positioned on the first side of the opening along the column direction; the third data line extends along the column direction and is positioned on the second side of the opening along the column direction; each second data line is connected with the first data line through a connecting line; and the source electrode driving circuit is connected with the third data line and the first data line and is used for providing data signals for the first data line, the second data line and the third data line. The display panel does not need to arrange data lines on the periphery of the opening, so that the technical problem that the opening frame is wide is solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic diagram of a display panel according to the related art;
FIG. 2 is a schematic diagram of an exemplary embodiment of a display panel according to the present disclosure;
FIG. 3 is a schematic diagram of another exemplary embodiment of a display panel according to the present disclosure;
FIG. 4 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure;
FIG. 5 is a schematic diagram of a first pixel driving circuit in an exemplary embodiment of a display panel according to the present disclosure;
FIG. 6 is a diagram illustrating a second pixel driving circuit according to an exemplary embodiment of a display panel of the present disclosure;
fig. 7 is a timing diagram of nodes in a driving method of a display panel according to the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components; the terms "comprising" and "having" are used in an inclusive sense and mean that there may be additional elements/components/integers other than the listed elements/components/integers.
As shown in fig. 1, which is a schematic structural diagram of a display panel in the related art, a display area of the display panel is provided with an opening 01, and a camera and other devices can be arranged in the opening 01, so that a full-screen effect can be really realized. Sub-pixel units are arranged around the opening 01, and signal lines such as grid lines and data lines connected with the sub-pixel units need to be integrated at the peripheral frame position of the opening 01, so that the width of a black frame around the opening is large, and the display effect is affected.
Based on this, the present disclosure first provides a display panel, as shown in fig. 2, which is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure. Display panel includes display area 11, display area 11 is provided with trompil AA hole, display panel still includes: a plurality of sub-pixel units 2, a plurality of first data lines 31, a plurality of second data lines 32, a plurality of third data lines 33, and a source driving circuit 5. A plurality of the sub-pixel units 2 are distributed along rows and columns; a plurality of first data lines 31 extend along the column direction Y and are connected to the sub-pixel units 2 in the same column, and the first data lines 31 are located at two sides of the opening AA hole along the row direction X; the plurality of second data lines 32 extend along the column direction Y, are positioned on the first side of the opening AA hole along the column direction Y, and are connected with the sub-pixel units 2 in the same column positioned on the first side of the opening AA hole along the column direction; a plurality of third data lines 33 extend along the column direction Y, are located at a second side of the opening AA hole along the column direction Y, and are connected to the sub-pixel units 2 in the same column at the second side of the opening AA hole along the column direction; wherein each of the second data lines 32 is connected to the first data line 31 through a connection line 4; the source driving circuit 5 is connected to the third data line 33 and the first data line 31, and is configured to provide data signals to the first data line, the second data line 32, and the third data line 33.
The display panel provided by the present disclosure connects the first data line 31 with the second data line 32 through the connection line 4, and the source driving circuit 5 may provide a data signal to the second data line 32 through the first data line 31. Thus, the second data line 32 and the third data line 33 may be disconnected at the position of the opening AA hole. That is, the display panel does not require the data lines to be arranged at the periphery of the opening, thereby reducing the width of the bezel around the opening AA hole.
In the present exemplary embodiment, as shown in fig. 2, the second data lines 32 and the first data lines 31 may be connected in a one-to-one correspondence. That is, each of the second data lines 32 is supplied with a data signal from a different first data line 31. It should be understood that, in other exemplary embodiments, a plurality of the second data lines 32 may also be correspondingly connected to one of the first data lines 31, that is, one first data line 31 may provide a data line signal to a plurality of the second data lines 32.
In the present exemplary embodiment, as shown in fig. 2, the display panel may further include a frame area 12 located around the display area 11, and the connection line 4 may be located in the frame area 12. It should be understood that, in other exemplary embodiments, the connection line 4 may also be located in the display region, and in this case, to avoid the connection line 4 from being crossed and shorted with the data line, the connection line may be connected with the first data line and the second data line respectively through a via hole, for example, the data line (including the first data line, the second data line, and the third data line) may be located in a source drain layer of the display panel, and the connection line may be located in a gate layer of the display panel.
In the exemplary embodiment, the data line is affected by its own resistance and parasitic capacitance, and the voltage of the data line on the side away from the source driving circuit is lower than the voltage close to the source driving circuit. As shown in fig. 2, the third data line 33 is closer to the source driving circuit 5 than the second data line 32. There is a large difference in voltage drop between the second data line 32 and the third data line 33. In the present exemplary embodiment, the voltage drop difference can be reduced by increasing the capacitance or changing the line width. For example, the cross-sectional area of the second data line may be greater than that of the third data line, so that a voltage drop difference between the second data line 32 and the third data line 33 is reduced by changing a resistance difference between the second data line and the third data line. For another example, in the present exemplary embodiment, the display panel may further include: a substrate and a conductive layer. The third data line 33 is positioned at one side of the substrate base plate; the conductive layer may be located on a side of the substrate base plate facing the third data line, and an orthogonal projection of the conductive layer on the substrate base plate is at least partially overlapped with an orthogonal projection of the third data line on the substrate base plate, so that a parasitic capacitance of the third data line 33 is compensated by the conductive layer, thereby further reducing a voltage drop difference between the second data line 32 and the third data line 33.
In the present exemplary embodiment, as shown in fig. 3, it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure. The display panel may further include a plurality of first gate lines 61, a plurality of second gate lines 62, a plurality of third gate lines 63, a first gate driving circuit 71, and a second gate driving circuit 72. A plurality of first gate lines 61 extend along the row direction X and are located at two sides of the opening AA hole along the column direction Y; a plurality of second gate lines 62 extending along the row direction X, located at a first side of the opening AA hole along the row direction X, and connected to the sub-pixel units 2 in the same row at the first side of the opening along the row direction; a plurality of third gate lines 63 extending along the row direction X, located at a second side of the openings along the row direction, and connected to the sub-pixel units 2 in the same row at the second side of the openings along the row direction; a first gate driving circuit 71 is connected to a first end of the first gate line 61 and the second gate line 62, and configured to provide a gate driving signal to the first gate line 61 and the second gate line 62; the second gate driving circuit 72 is connected to a second end of the first gate line 61 and the third gate line 63, and configured to provide a gate driving signal to the first gate line 61 and the third gate line 63; the first gate driving circuit 71 and the second gate driving circuit 72 provide the same timing of the gate driving signals to the sub-pixel units 2 in the same row. In this exemplary embodiment, the display panel may provide the gate driving signals to the second gate line and the third gate line through the first gate driving circuit and the second gate driving circuit, respectively, so that the second gate line 62 and the third gate line 63 may be disconnected at the opening AA hole, that is, the display panel does not need to arrange the gate lines at the periphery of the opening AA hole, thereby further reducing the width of the frame around the opening AA hole.
In the present exemplary embodiment, as shown in fig. 4, it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure. The plurality of sub-pixel units may include a first sub-pixel unit 21 connected to the second data line 32 and a second sub-pixel unit 22 connected to the first data line 31 and the third data line 33.
The first sub-pixel unit 21 may include a first pixel driving circuit, as shown in fig. 5, which is a schematic structural diagram of the first pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure. The first pixel driving circuit may include: a first data write circuit 81, a first drive circuit 82, a first light emission control circuit 83, a first reset circuit 84, and a first capacitor C1. The first Data writing circuit 81 may be connected to a first Data signal terminal Data1, a first node N1, and a first Reset signal terminal Reset1, and configured to transmit a signal of the first Data signal terminal Data1 to the first node N1 in response to a signal of the first Reset signal terminal Reset 1; the first driving circuit 82 is connected to a first power source terminal VDD, the first node N1, and a second node N2, and is configured to input a driving current to the second node N2 according to a signal of the first node N1; the first light emitting control circuit 83 is connected to the second node N2, the light emitting unit OLED, and the first enable signal terminal EM1, and configured to transmit the signal of the second node N2 to the first electrode of the light emitting unit OLED in response to the signal of the first enable signal terminal EM1, and the second electrode of the light emitting unit OLED is connected to the second power source terminal VSS; the first Reset circuit 84 is connected to the first Reset signal terminal Reset1, the first initialization signal terminal Vinit1, and the second node N2, and configured to transmit a signal of the first initialization signal terminal Vinit1 to the second node N2 in response to a signal of the first Reset signal terminal Reset 1; the first capacitor C1 is connected between said first supply terminal VDD and said first node N1.
The second sub-pixel unit may include a second pixel driving circuit, as shown in fig. 6, which is a schematic structural diagram of the second pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure. The second pixel driving circuit may include: a second data writing circuit 91, a second driving circuit 92, a second light emission control circuit 93, a compensation circuit 94, a second reset circuit 95, and a second capacitor C2. The second Data writing circuit 91 is connected to a second Data signal terminal Data2, a third node N3, and a Gate driving signal terminal Gate, and configured to transmit a signal of the second Data signal terminal Data2 to the third node N3 in response to a signal of the Gate driving signal terminal Gate; the second driving circuit 92 is connected to the third node N3, the fourth node N4 and the fifth node N5, and is configured to input a driving current to the fourth node N4 according to a signal of the fifth node N5; the second light-emission control circuit 93 is connected to the first power terminal VDD, the third node N3, the second enable signal terminal EM2, the fourth node N4, the light-emitting unit OLED, for transmitting a signal of the first power terminal to the third node N3 in response to a signal of the second enable signal terminal EM2, and for transmitting a signal of the fourth node N4 to the first electrode of the light-emitting unit OLED in response to a signal of the second enable signal terminal EM2, the second electrode of the light-emitting unit OLED being connected to the second power terminal VSS; the compensation circuit 94 is connected to the fourth node N4, the fifth node N5 and the Gate driving signal terminal Gate, and is configured to respond to a signal of the Gate driving signal terminal Gate to communicate the fourth node N4 and the fifth node N5; the second Reset circuit 95 is connected to the fifth node N5, the reference voltage terminal, the second Reset signal terminal Reset2, the first pole of the first light-emitting unit OLED, and the second initialization signal terminal Vinit2, and is configured to transmit a signal of the reference voltage terminal to the fifth node N5 in response to a signal of the second Reset signal terminal Reset2, and transmit a signal of the second initialization signal terminal Vinit2 to the first pole of the first light-emitting unit OLED in response to a signal of the second Reset signal terminal Reset2; the second capacitor C2 is connected between the first power terminal VDD and the fifth node N5.
In the present exemplary embodiment, as shown in fig. 4, the first Reset signal terminal Reset1 in the first sub-pixel unit 21 and the second Reset signal terminal Reset2 in the second sub-pixel unit 22 located in the same row may be commonly connected to one of the first Gate lines 61, and the second Reset signal terminal Reset2 in the second sub-pixel unit 22 and the Gate driving signal terminal Gate of the second sub-pixel unit 22 located in the row above the second Reset signal terminal Reset2 may be commonly connected to one of the first Gate lines 61, the second Gate lines 62, and the third Gate lines 63.
In addition, the first data signal terminal in the first sub-pixel driving circuit and the second data signal terminal in the second sub-pixel unit both provide data signals through data lines (including the first data line, the second data line, and the third data line). The display panel provided by the present exemplary embodiment may further include an enable signal line for providing an enable signal, the enable signal line may extend in a row direction, the sub-pixel units located in the same row may be connected to the same enable signal line, and the enable signal line may be disposed in the same manner as the gate line. That is, the display panel may include a plurality of first enable signal lines, a plurality of second enable signal lines, and a plurality of third enable signal lines. The plurality of first enabling signal lines extend along the row direction and are positioned at two sides of the open holes along the column direction; the plurality of second enabling signal lines extend along the row direction, are positioned on the first side of the opening along the row direction and are connected with the sub-pixel units in the same row on the first side of the opening along the row direction; and the plurality of third enabling signal lines extend along the row direction, are positioned at the second side of the opening along the row direction and are connected with the sub-pixel units in the same row positioned at the second side of the opening along the row direction.
In the present exemplary embodiment, as shown in fig. 5, the first Data writing circuit 81 may include a first transistor T1, a first pole of the first transistor T1 is connected to the first Data signal terminal Data1, a second pole is connected to the first node N1, and a gate is connected to the first Reset signal terminal Reset1. The first driving circuit 82 may include a first driving transistor DT1, a first electrode of the first driving transistor DT1 being connected to the first power source terminal VDD, a second electrode of the first driving transistor DT1 being connected to the second node N2, and a gate electrode of the first driving transistor DT1 being connected to the first node N1. The first light emission control circuit 83 may include a second transistor T2, a first pole of the second transistor T2 is connected to the second node N2, a second pole is connected to the light emitting unit OLED, and a gate is connected to the first enable signal terminal EM1. The first Reset circuit 84 may include a third transistor T3, a first pole of the third transistor T3 is connected to the first initialization signal terminal Vinit1, a second pole of the third transistor T3 is connected to the second node N2, and a gate of the third transistor T3 is connected to the first Reset signal terminal Reset1.
In the present exemplary embodiment, as shown in fig. 6, the second Data writing circuit 91 may include a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second Data signal terminal Data2, a second pole is connected to the third node N3, and a Gate is connected to the Gate driving signal terminal Gate. The second driving circuit 92 may include a second driving transistor DT2, a first pole of the second driving transistor DT2 being connected to the third node N3, a second pole thereof being connected to the fourth node N4, and a gate thereof being connected to the fifth node N5. The second light-emitting control circuit 93 may include a fifth transistor T5 and a sixth transistor T6, a first electrode of the fifth transistor T5 is connected to the first power terminal VDD, a second electrode is connected to the third node N3, and a gate is connected to the second enable signal terminal EM2; a first pole of the sixth transistor T6 is connected to the fourth node N4, a second pole thereof is connected to the light emitting unit OLED, and a gate thereof is connected to the second enable signal terminal EM2. The compensation circuit 94 may include a seventh transistor T7, a first pole of the seventh transistor T7 is connected to the fourth node N4, a second pole of the seventh transistor T7 is connected to the fifth node N5, and a Gate of the seventh transistor T7 is connected to the Gate driving signal terminal Gate. The second Reset circuit 95 may include an eighth transistor T8 and a ninth transistor T9, wherein a first pole of the eighth transistor T8 is connected to the reference voltage terminal Vref, a second pole of the eighth transistor T8 is connected to the fifth node N5, and a gate of the eighth transistor T8 is connected to the second Reset signal terminal Reset2; a first pole of the ninth transistor T9 is connected to the second initialization signal terminal Vinit2, a second pole thereof is connected to a second pole of the sixth transistor, and a gate thereof is connected to the second Reset signal terminal Reset2.
As shown in fig. 5 and 6, the first to ninth transistors, the first driving transistor, and the second driving transistor may be P-type transistors, the first power source terminal VDD may be a high-level power source terminal, and the second power source terminal may be a low-level power source terminal.
Fig. 7 is a timing diagram of each node in a driving method of a display panel according to the present disclosure. The display panel can drive the first sub-pixel unit and the second sub-pixel unit line by line. The present exemplary embodiment takes two first sub-pixel units and two second sub-pixel units located in the same row as an example for explanation. Where, reset1 represents a timing sequence of the first Reset signal terminal in fig. 5, reset2 represents a timing sequence of the second Reset signal terminal in fig. 6, EM1 represents a timing sequence of the first enable signal terminal in fig. 5, EM2 represents a timing sequence of the second enable signal terminal in fig. 6, data1 represents a timing sequence of the first Data signal terminal in fig. 5, data2 represents a timing sequence of the second Data signal terminal in fig. 6, and Gate represents a timing sequence of the Gate driving signal terminal in fig. 6. In the present exemplary embodiment, the first sub-pixel unit and the second sub-pixel unit located in the same row may be connected to the same enable signal line, so that timings of EM1 and EM2 are the same. The first Reset signal terminal Reset1 in the first sub-pixel unit 21 and the second Reset signal terminal Reset2 in the second sub-pixel unit 22 in the same row can be commonly connected to one of the first gate lines 61, and therefore, the timings of Reset1 and Reset2 are the same. As shown in fig. 7, the display panel driving method includes three stages: a first node T1, a second stage T2, and a third stage T3. In the first stage: for the first pixel driving circuit, the first Reset signal terminal Reset1 is at a low level, the first enable signal terminal EM1 is at a high level, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 is turned off, the first Data signal terminal Data can write a Data signal into the first node N1, and the first initialization signal terminal Vinit1 can obtain the threshold voltage of the first driving transistor DT1 according to the current thereof, so that the Data signal of the first Data signal terminal can be compensated; for the second pixel driving circuit, the second Reset signal terminal Reset2 outputs a low level signal, the second enable signal terminal outputs a high level signal, the eighth transistor T8 and the ninth transistor T9 are turned on, the second initialization signal terminal Vinit2 inputs an initialization signal to the first electrode of the light emitting unit OLED, and the reference signal terminal Vref inputs a reference signal to the fifth node N5. In the second stage: for the first pixel driving circuit, the voltage of the first node is unchanged under the action of the first capacitor C1, and the first enable signal end EM1 continuously turns off the second transistor T2; for the second pixel driving circuit, the Gate driving signal terminal Gate outputs a low level signal, the fourth transistor T4 and the seventh transistor T7 are turned on, and the second Data signal terminal Data2 writes a voltage Vth + Vdata2 into the fifth node, where Vth is a threshold voltage of the second driving transistor DT2, and Vdata2 is a voltage of the second Data signal terminal Data. In the third stage: for the first pixel driving circuit, the first enable signal terminal EM1 outputs a low level signal, so that the second transistor is turned on, and the light emitting unit OLED emits light; for the second pixel driving circuit, the second enable signal terminal EM2 outputs a low level signal, so that the fifth transistor and the sixth transistor are turned on, and the light emitting unit OLED emits light.
According to the driving method, the display panel provided by the disclosure obtains different data signals by the first pixel driving circuit and the second pixel driving circuit in the same row when the display panel is driven row by row. The data signals acquired by the first pixel driving circuit are the data signals acquired by the second pixel driving circuit in the previous row. The arrangement can realize that the first sub-pixel unit and the second sub-pixel unit in the same row emit light with different gray scales.
The present exemplary embodiment also provides a display device including the display panel described above. The display device can be a mobile phone, a television, a tablet computer and other display devices.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the following claims.
Claims (8)
1. The utility model provides a display panel, display panel includes the display area, the display area is provided with the trompil, its characterized in that, display panel still includes:
the plurality of sub-pixel units are distributed along rows and columns;
the plurality of first data lines extend along the column direction and are connected with the sub-pixel units in the same column, and the first data lines are positioned on two sides of the opening along the row direction;
the plurality of second data lines extend along the column direction, are positioned on the first side of the opening along the column direction, and are connected with the sub-pixel units in the same column positioned on the first side of the opening along the column direction;
a plurality of third data lines extending in the column direction, located on a second side of the opening in the column direction, and connected to the sub-pixel units in the same column on the second side of the opening in the column direction;
each second data line is connected with the first data line through a connecting line;
the source electrode driving circuit is connected with the third data line and the first data line and is used for providing data signals for the first data line, the second data line and the third data line;
the display panel further includes:
a plurality of first grid lines extending along the row direction and positioned at two sides of the openings along the column direction;
a plurality of second grid lines extending along the row direction, positioned at the first side of the opening along the row direction and connected with the sub-pixel units in the same row at the first side of the opening along the row direction;
a plurality of third gate lines extending in the row direction, located at a second side of the openings in the row direction, and connected to the sub-pixel units in the same row at the second side of the openings in the row direction;
the first grid driving circuit is connected with the first end of the first grid line and the second grid line and is used for providing a grid driving signal for the first grid line and the second grid line;
the second grid driving circuit is connected with the second end of the first grid line and the third grid line and is used for providing a grid driving signal for the first grid line and the third grid line;
the first grid driving circuit and the second grid driving circuit provide the same time sequence for the grid driving signals of the sub-pixel units in the same row;
the plurality of sub-pixel units comprise a first sub-pixel unit connected with the second data line and a second sub-pixel unit connected with the first data line and the third data line;
the first sub-pixel unit includes a first pixel driving circuit including:
the first data writing circuit is connected with a first data signal end, a first node and a first reset signal end and used for responding to a signal of the first reset signal end and transmitting a signal of the first data signal end to the first node;
the first driving circuit is connected with a first power supply end, the first node and the second node and used for inputting driving current to the second node according to a signal of the first node;
a first light emitting control circuit connected to the second node, the light emitting unit, and a first enable signal terminal, for transmitting a signal of the second node to a first electrode of the light emitting unit in response to a signal of the first enable signal terminal, a second electrode of the light emitting unit being connected to a second power terminal;
the first reset circuit is connected with the first reset signal end, the first initialization signal end and the second node and used for responding to the signal of the first reset signal end and transmitting the signal of the first initialization signal end to the second node;
a first capacitor connected between the first power supply terminal and the first node;
the second sub-pixel unit includes a second pixel driving circuit including:
the second data writing circuit is connected with a second data signal end, a third node and a grid driving signal end and is used for responding to the signal of the grid driving signal end and transmitting the signal of the second data signal end to the third node;
the second driving circuit is connected with the third node, the fourth node and the fifth node and used for inputting driving current to the fourth node according to a signal of the fifth node;
a second light-emitting control circuit connected to the first power terminal, a third node, a second enable signal terminal, a fourth node, and a light-emitting unit for transmitting a signal of the first power terminal to the third node in response to a signal of the second enable signal terminal and for transmitting a signal of the fourth node to a first electrode of the light-emitting unit in response to a signal of the second enable signal terminal, a second electrode of the light-emitting unit being connected to a second power terminal;
the compensation circuit is connected with the fourth node, the fifth node and a grid driving signal end and is used for responding to the signal of the grid driving signal end to communicate the fourth node and the fifth node;
a second reset circuit, connected to the fifth node, the reference voltage terminal, a second reset signal terminal, the first pole of the first light emitting unit, and the second initialization signal terminal, for transmitting a signal of the reference voltage terminal to the fifth node in response to a signal of the second reset signal terminal, and for transmitting a signal of the second initialization signal terminal to the first pole of the first light emitting unit in response to a signal of the second reset signal terminal;
a second capacitor connected between the first power supply terminal and the fifth node;
the first reset signal end in the first sub-pixel unit and the second reset signal end in the second sub-pixel unit positioned on the same row are connected with the first grid line together, and the second reset signal end in the second sub-pixel unit and the grid driving signal end of the second sub-pixel unit positioned on the upper row are connected with the first grid line or the second grid line or the third grid line together.
2. The display panel according to claim 1, wherein the second data lines are connected to the first data lines in a one-to-one correspondence;
or, a plurality of second data lines are correspondingly connected with one first data line.
3. The display panel according to claim 1, wherein the display panel comprises a frame area located around a display area, and the connection line is located in the frame area;
or the connecting line is positioned in the display area and is respectively connected with the first data line and the second data line through via holes.
4. The display panel according to claim 1, wherein a cross-sectional area of the second data line is larger than a cross-sectional area of the third data line.
5. The display panel according to claim 1, wherein the display panel further comprises:
the third data line is positioned on one side of the substrate base plate;
and the conductive layer is positioned on one side of the substrate base plate facing the first data line, and the orthographic projection of the conductive layer on the substrate base plate is at least partially overlapped with the orthographic projection of the third data line on the substrate base plate.
6. The display panel according to claim 1,
the first data writing circuit includes:
a first transistor, a first electrode of which is connected with the first data signal end, a second electrode of which is connected with the first node, and a grid electrode of which is connected with the first reset signal end;
the first drive circuit includes:
a first driving transistor, having a first electrode connected to the first power terminal, a second electrode connected to the second node, and a gate connected to the first node;
the first light emission control circuit includes:
a second transistor, wherein a first electrode of the second transistor is connected to the second node, a second electrode of the second transistor is connected to the light emitting unit, and a gate of the second transistor is connected to the first enable signal terminal;
the first reset circuit includes:
and a third transistor, wherein a first pole of the third transistor is connected with the first initialization signal end, a second pole of the third transistor is connected with the second node, and a grid electrode of the third transistor is connected with the first reset signal end.
7. The display panel according to claim 1,
the second data writing circuit includes:
a fourth transistor, having a first electrode connected to the second data signal terminal, a second electrode connected to the third node, and a gate connected to the gate driving signal terminal;
the second drive circuit includes:
a second driving transistor, having a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate connected to the fifth node;
the second light emission control circuit includes:
a fifth transistor having a first terminal connected to the first power terminal, a second terminal connected to the third node, and a gate connected to the second enable signal terminal;
a sixth transistor, having a first electrode connected to the fourth node, a second electrode connected to the light emitting unit, and a gate connected to the second enable signal terminal;
the compensation circuit includes:
a seventh transistor, having a first electrode connected to the fourth node, a second electrode connected to the fifth node, and a gate connected to the gate driving signal terminal;
the second reset circuit includes:
a first electrode of the eighth transistor is connected with the reference voltage end, a second electrode of the eighth transistor is connected with the fifth node, and a grid electrode of the eighth transistor is connected with the second reset signal end;
and a ninth transistor, wherein a first pole of the ninth transistor is connected to the second initialization signal terminal, a second pole of the ninth transistor is connected to a second pole of the sixth transistor, and a gate of the ninth transistor is connected to the second reset signal terminal.
8. A display device characterized by comprising the display panel according to any one of claims 1 to 7.
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| EP4318451A1 (en) * | 2021-09-14 | 2024-02-07 | BOE Technology Group Co., Ltd. | Display panel and display device |
| CN114495794B (en) * | 2022-02-18 | 2023-12-26 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2023159503A1 (en) * | 2022-02-25 | 2023-08-31 | 京东方科技集团股份有限公司 | Pixel circuit and driving method, display panel and driving method, and display device |
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| US8878755B2 (en) * | 2012-08-23 | 2014-11-04 | Au Optronics Corporation | Organic light-emitting diode display and method of driving same |
| CN104361857A (en) * | 2014-11-04 | 2015-02-18 | 深圳市华星光电技术有限公司 | Pixel driving circuit of organic light-emitting display |
| CN106157895B (en) * | 2016-07-04 | 2019-07-16 | 上海天马有机发光显示技术有限公司 | A kind of organic light emitting display panel and its driving method |
| CN109036250A (en) * | 2018-08-22 | 2018-12-18 | 京东方科技集团股份有限公司 | Display base plate, display panel and driving method, display device |
| CN108962037B (en) * | 2018-09-19 | 2021-08-27 | 京东方科技集团股份有限公司 | Display device and control method thereof |
| CN111128080B (en) * | 2020-03-30 | 2020-08-04 | 京东方科技集团股份有限公司 | Display substrate and display device |
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