CN111682032A - Display panel and method for manufacturing the same - Google Patents
Display panel and method for manufacturing the same Download PDFInfo
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- CN111682032A CN111682032A CN202010605334.7A CN202010605334A CN111682032A CN 111682032 A CN111682032 A CN 111682032A CN 202010605334 A CN202010605334 A CN 202010605334A CN 111682032 A CN111682032 A CN 111682032A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims description 48
- 239000010410 layer Substances 0.000 claims abstract description 207
- 230000007704 transition Effects 0.000 claims abstract description 76
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 238000002161 passivation Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000004642 Polyimide Substances 0.000 abstract description 25
- 229920001721 polyimide Polymers 0.000 abstract description 25
- 238000007639 printing Methods 0.000 abstract description 14
- 238000009413 insulation Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 38
- 230000008569 process Effects 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 12
- 238000009825 accumulation Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 230000008719 thickening Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007644 letterpress printing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The application discloses a display panel and a manufacturing method thereof. The display panel includes: the substrate, the buffer layer, the gate insulation layer, the interlayer dielectric layer, the flat layer, the passivation layer and the alignment layer. The buffer layer is arranged on the substrate. The gate insulating layer is disposed on the buffer layer. The interlayer dielectric layer is arranged on the grid insulation layer. The flat layer is arranged on the interlayer dielectric layer, the flat layer comprises a flat part and a transition part which are mutually adjacent, the flat part is arranged in the display area, the transition part is arranged in the part of the non-display area adjacent to the display area, and the thickness of the flat part is larger than that of the transition part. The passivation layer is disposed on the flat portion and the transition portion. The alignment layer is arranged on the passivation layer. The display panel has the effects of improving poor printing of polyimide and improving the yield of the manufacturing process.
Description
Technical Field
The invention relates to the display field, and more particularly to a display panel and a method for manufacturing the same.
Background
A Thin film transistor liquid crystal display (TFT-LCD) is composed of a TFT substrate, a Color Filter (CF) substrate and liquid crystal between the two. The basic operation principle is that, under the control of an applied voltage, liquid crystal molecules rotate due to the dielectric anisotropy of the liquid crystal, so that the refractive index or light transmittance of the liquid crystal is changed, thereby controlling the light output of the TFT-LCD. In order to better control the amount of light emitted from the liquid crystal, the TFT substrate and the CF substrate are generally coated with a Polyimide (PI) alignment film simultaneously during cell formation. By utilizing a strong interface between the liquid crystal and the PI alignment film, when the applied voltage is removed, the applied force returns the liquid crystal molecules after changing the alignment direction to their original state by viscoelasticity. Therefore, the PI alignment film is required to have characteristics of uniformity, adhesion, and stability.
A common printing method used in PI printing processes is letterpress printing. The PI in the relief grid is transferred to the TFT substrate by pressing to form individual PI patterns. The PI pattern naturally expands flat by the surface tension, and finally a PI alignment film having a uniform thickness is formed. In actual production, since PI is a liquid mixture and has strong fluidity, it often happens that the non-display area PI shrinks to the display area in the opposite direction of printing, resulting in thick accumulation of PI at the edge of the display area and poor uniformity. Therefore, LCD alignment abnormality is caused, and the panel display is poor.
Therefore, it is desirable to provide a display panel and a method for manufacturing the same to solve the problems of the prior art.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a manufacturing method thereof, which are helpful for improving poor PI printing and increasing the process yield.
The present invention provides a display panel, which includes a display area and a non-display area, wherein the non-display area surrounds the display area. The display panel includes: the substrate, the buffer layer, the gate insulation layer, the interlayer dielectric layer, the flat layer, the passivation layer and the alignment layer. The buffer layer is arranged on the substrate, wherein the buffer layer is positioned in the display area and the non-display area. The gate insulating layer is disposed on the buffer layer, wherein the gate insulating layer is disposed in the display region and the non-display region. The interlayer dielectric layer is arranged on the grid electrode insulating layer, wherein the interlayer dielectric layer is positioned in the display area and the non-display area. The flat layer is arranged on the interlayer dielectric layer, the flat layer comprises a flat part and a transition part which are mutually adjacent, the flat part is arranged in the display area, the transition part is arranged in the part of the non-display area adjacent to the display area, and the thickness of the flat part is larger than that of the transition part. The passivation layer is disposed on the flat portion and the transition portion. The alignment layer is arranged on the passivation layer.
In an embodiment of the invention, the transition portion further includes at least one protrusion.
In an embodiment of the present invention, the shape of the at least one protrusion includes at least one of a cylinder, a cone, an angular cylinder and a pyramid.
In an embodiment of the invention, the transition portion has a slope, wherein the slope starts from the interface of the flat portion and the transition portion and extends obliquely downwards.
In an embodiment of the present invention, the slope extends obliquely downward until it meets the interlayer dielectric layer.
Furthermore, another embodiment of the present invention provides a method for manufacturing a display panel, where the display panel includes a display area and a non-display area, and the non-display area surrounds the display area. The manufacturing method of the display panel comprises the following steps: providing a substrate; forming a buffer layer on the substrate, wherein the buffer layer is located in the display region and the non-display region; forming a gate insulating layer on the buffer layer, wherein the gate insulating layer is located in the display region and the non-display region; forming an interlayer dielectric layer on the gate insulating layer, wherein the interlayer dielectric layer is located in the display region and the non-display region; forming a flat layer on the interlayer dielectric layer, wherein the flat layer comprises a flat portion and a transition portion which are adjacent to each other, the flat portion is arranged in the display area, the transition portion is arranged in a portion of the non-display area adjacent to the display area, and the thickness of the flat portion is larger than that of the transition portion; forming a passivation layer on the flat portion and the transition portion; and forming an alignment layer on the passivation layer.
In an embodiment of the invention, the transition portion further includes at least one protrusion.
In one embodiment of the present invention, the step of forming the planarization layer on the interlayer dielectric layer comprises: the flat layer is formed by a gray-tone mask method or a halftone mask method.
In an embodiment of the invention, the transition portion has a slope, wherein the slope starts from the interface of the flat portion and the transition portion and extends obliquely downwards.
In an embodiment of the present invention, the slope extends obliquely downward until it meets the interlayer dielectric layer.
Compared with the prior art, the display panel and the manufacturing method thereof have the advantages that the Polyimide (PI) contraction backflow restraining area (the transition part corresponding to the flat layer) is manufactured in the part, adjacent to the display area, of the non-display area, so that poor PI printing is improved, and the manufacturing process yield is improved.
In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
FIGS. 1A and 1B are schematic cross-sectional views of a display panel before and after an alignment layer is disposed thereon according to an embodiment of the invention;
FIGS. 2A and 2B are schematic cross-sectional views illustrating a display panel before and after an alignment layer is disposed thereon according to another embodiment of the present invention; and
FIGS. 3A and 3B are schematic cross-sectional views of a typical display panel before and after an alignment layer is disposed thereon; and
fig. 4 is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the invention.
Detailed Description
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. Furthermore, directional phrases used herein, such as, for example, upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, lateral, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., refer only to the orientation of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
Referring to fig. 1A and fig. 1B, the display panel 10 of the embodiment of the invention is mainly directed to the improvement of the boundary between the display area 10A and the non-display area 10B, and therefore common components or layers, such as an active layer and a gate layer of a TFT structure, are not described or illustrated again.
The display panel 10 of the embodiment of the present invention includes a display area 10A and a non-display area 10B, and the non-display area 10B surrounds the display area 10A. The display panel 10 includes a substrate 11, a buffer layer 12, a gate insulating layer 13, an interlayer dielectric layer 14, a planarization layer 15, a passivation layer 16, and an alignment layer 17. The substrate 11 may be used to support the buffer layer 12, the gate insulating layer 13, the interlayer dielectric layer 14, the planarization layer 15, the passivation layer 16, and the alignment layer 17. In one embodiment, the substrate 11 is, for example, a flexible substrate, a transparent substrate or a flexible transparent substrate.
In the embodiment of the present invention, the buffer layer 12 is disposed on the substrate 11, wherein the buffer layer 12 is located in the display region 10A and the non-display region 10B. In one embodiment, the material and the manufacturing method of the buffer layer 12 can refer to the materials and the manufacturing methods commonly used in the general semiconductor process.
In the embodiment of the present invention, the gate insulating layer 13 is disposed on the buffer layer 12, wherein the gate insulating layer 13 is located in the display region 10A and the non-display region 10B. In one embodiment, the gate insulation layer 13 may be made of a material and a method, which are commonly used in a general semiconductor process.
In the embodiment of the present invention, the interlayer dielectric layer 14 is disposed on the gate insulating layer 13, wherein the interlayer dielectric layer 14 is located in the display region 10A and the non-display region 10B. In one embodiment, the interlayer dielectric layer 14 may be made of a material and/or a method that is commonly used in a general semiconductor process.
In the embodiment of the invention, the planarization layer 15 is disposed on the interlayer dielectric layer 14, the planarization layer 15 includes a planarization portion 151 and a transition portion 152 adjacent to each other, the planarization portion 151 is disposed in the display region 10A, the transition portion 152 is disposed in a portion of the non-display region 10B adjacent to the display region 10A, wherein a thickness of the planarization portion 151 is greater than a thickness of the transition portion 152. In one embodiment, the flat portion 151 and the transition portion 152 having different thicknesses may be formed at one time by, for example, a gray mask method or a half-tone mask method. It should be noted at this point that at least one feature of the present invention is to avoid the accumulation and thickening of the subsequently formed alignment layer in the display region 10A adjacent to the non-display region 10B by having the transition portion 152 (relative to the flat portion 151) thinner. The detailed description will be described in the following paragraphs. It should be noted that the material of the planarization layer 15 can refer to the materials commonly used in the general semiconductor process.
In the embodiment of the present invention, the passivation layer 16 is disposed on the flat portion 151 and the transition portion 152. In one embodiment, the passivation layer 16 may be formed by a method and a material commonly used in a general semiconductor process.
In the embodiment of the present invention, the alignment layer 17 is disposed on the passivation layer 16. In one embodiment, the material and the manufacturing method of the alignment layer 17 refer to materials and manufacturing methods commonly used in general semiconductor processes.
It should be noted here that due to the design of the flat portion 151 and the transition portion 152 of the flat layer 15 of the present invention, the passivation layer 16 and the alignment layer 17 on the transition portion 152 respectively generate a height difference with the passivation layer 16 and the alignment layer 17 on the flat portion 151, which helps to avoid the problem of the accumulation of the alignment material 171 (e.g. PI) used by the alignment layer 17 in the display region 10A becoming thick, as described below.
Referring to fig. 1A to 3B, generally, when the alignment layer 17 or 37 is disposed, it is performed by a relief printing method. However, in a typical display panel 30 (as shown in fig. 3A and 3B, which includes a substrate 31, a buffer layer 32, a gate insulating layer 33, an interlayer dielectric layer 34, a planarization layer 35, a passivation layer 36 and an alignment layer 37, but it is to be specifically mentioned that fig. 3A and 3B are only used for comparison purposes, and are not prior art recognized by the present invention), the thickness of the planarization layer 35 in the display region 30A is substantially the same as that of the planarization layer 35 in the non-display region 30B, so that the passivation layer 36 formed subsequently has the same thickness in the display region 30A and the non-display region 30B. This causes a situation where the alignment material 371 (for example, PI) located at the edge (i.e., located in the non-display region 30B) shrinks to the display region 30A when the alignment layer 37 is disposed by means of relief printing, and thus there is a problem that the accumulation of the alignment material 371 at the edge of the display region 30A becomes thick and the uniformity is poor. The display panel 10 according to the embodiment of the invention designs the flat portion 151 and the transition portion 152 having a thickness difference, so that a height difference is generated between the passivation layer 16 on the transition portion 152 and the passivation layer 16 on the flat portion 151. Therefore, when performing relief printing, the alignment material at the edge (i.e., at the transition portion 152) flows toward the non-display region 10B due to the height difference, thereby avoiding the problem of the alignment material being deposited thick at the edge of the display region.
In one embodiment, the transition portion 152 has a slope 152A, wherein the slope 152A starts from the intersection of the flat portion 151 and the transition portion 152 and extends obliquely downward. In one example, the slope 152A extends obliquely downward until it meets the ild layer 14. The slope 152A can promote the originally stacked alignment material to automatically flow toward the non-display region 10B, thereby avoiding the problem of the alignment material from being thickened at the edge of the display region.
In one embodiment, the transition portion 152 further comprises at least one protrusion 153 (shown in fig. 3A and 3B). The at least one protrusion 153 protrudes substantially outwardly from the upper surface of the transition portion 152. In one example, the shape of the at least one protrusion 153 includes geometric shapes, such as at least one of a cylinder, a cone, an angular cylinder, and a pyramid. Specifically, although the design of the transition portion 152 helps to solve the problem of the accumulation and thickening of the alignment material at the edge of the display region, the gas at the transition portion 152 occasionally forms a gas barrier, and instead blocks the flow of the alignment material toward the non-display region 10B. In the embodiment of the present invention, the at least one protrusion 153 is disposed to disturb the gas at the transition portion 152, so as to avoid the generation of a gas barrier. Therefore, the at least one protrusion 153 is helpful to establish a solid, liquid and gas equilibrium state to form a PI shrink reflow inhibition area, which can improve PI printing defects and increase the process yield. In one embodiment, the at least one protrusion 153 may be disposed on the inclined surface 152A. In another embodiment, the material of the at least one protrusion 153 may be the same as or different from that of the planarization layer 15. In one example, the at least one protrusion 153 may be formed together with the transition portion 152 and the flat portion 151 by a gray mask method or a half-tone mask method.
Referring to fig. 4, an embodiment of the present invention provides a method 40 for manufacturing a display panel, where the display panel includes a display area and a non-display area, and the non-display area surrounds the display area. The manufacturing method 40 includes steps 41 to 47: providing a substrate (step 41); forming a buffer layer on the substrate, wherein the buffer layer is located in the display region and the non-display region (step 42); forming a gate insulating layer on the buffer layer, wherein the gate insulating layer is located in the display region and the non-display region (step 43); forming an interlayer dielectric layer on the gate insulating layer, wherein the interlayer dielectric layer is located in the display region and the non-display region (step 44); forming a flat layer on the interlayer dielectric layer, wherein the flat layer comprises a flat portion and a transition portion adjacent to each other, the flat portion is disposed in the display region, the transition portion is disposed in a portion of the non-display region adjacent to the display region, and a thickness of the flat portion is greater than a thickness of the transition portion (step 45); forming a passivation layer on the flat portion and the transition portion (step 46); and forming an alignment layer on the passivation layer (step 47).
Referring to fig. 1A, fig. 1B, fig. 2A, fig. 2B and fig. 4, step 41 of the method 40 for manufacturing a display panel according to the embodiment of the present invention is: a substrate is provided. In this step 41, the substrate 11 may be used to support the buffer layer 12, the gate insulating layer 13, the interlayer dielectric layer 14, the planarization layer 15, the passivation layer 16 and the alignment layer 17. In one embodiment, the substrate 11 is, for example, a flexible substrate, a transparent substrate or a flexible transparent substrate.
In one embodiment, the transition portion 152 has a slope 152A, wherein the slope 152A starts from the intersection of the flat portion 151 and the transition portion 152 and extends obliquely downward. In one example, the slope 152A extends obliquely downward until it meets the ild layer 14. The slope 152A can promote the originally stacked alignment material to automatically flow toward the non-display region 10B, thereby avoiding the problem of the alignment material from being thickened at the edge of the display region.
In one embodiment, the transition portion 152 further comprises at least one protrusion 153. The at least one protrusion 153 protrudes substantially outwardly from the upper surface of the transition portion 152. In one example, the shape of the at least one protrusion 153 includes geometric shapes, such as at least one of a cylinder, a cone, an angular cylinder, and a pyramid. Specifically, although the design of the transition portion 152 helps to solve the problem of the accumulation and thickening of the alignment material at the edge of the display region, the gas at the transition portion 152 occasionally forms a gas barrier, and instead blocks the flow of the alignment material toward the non-display region 10B. In the embodiment of the present invention, the at least one protrusion 153 is disposed to disturb the gas at the transition portion 152, so as to avoid the generation of a gas barrier. Therefore, the at least one protrusion 153 is helpful to establish a solid, liquid and gas equilibrium state to form a PI shrink reflow inhibition area, which can improve PI printing defects and increase the process yield. In one embodiment, the at least one protrusion 153 may be disposed on the inclined surface 152A. In another embodiment, the material of the at least one protrusion 153 may be the same as or different from that of the planarization layer 15. In one example, the at least one protrusion 153 may be formed together with the transition portion 152 and the flat portion 151 by a gray mask method or a half-tone mask method.
It should be noted that, due to the design of the flat portion 151 and the transition portion 152 of the flat layer 15 of the present invention, the passivation layer 16 and the alignment layer 17 on the transition portion 152 have a height difference with the passivation layer 16 and the alignment layer 17 on the flat portion 151, respectively, which helps to avoid the problem of the accumulation of the alignment material (e.g. PI) used by the alignment layer 17 in the display region 10A becoming thick, as described below.
The alignment layer 17 is usually provided by means of relief printing. However, in a typical display panel (see fig. 3A and 3B), the thickness of the planarization layer 15 in the display area 30A is substantially the same as the thickness of the planarization layer 35 in the non-display area 30B, and thus the passivation layer 36 formed subsequently has the same thickness in the display area 30A and the non-display area 30B. This causes a situation where the alignment material (for example, PI) at the edge (i.e., at the non-display region 30B) shrinks to the display region 30A when the alignment layer 37 is disposed by means of relief printing, and thus the accumulation of the alignment material 371 at the edge of the display region 30A becomes thicker, which causes a problem of poor uniformity. The display panel 10 according to the embodiment of the invention designs the flat portion 151 and the transition portion 152 having a thickness difference, so that a height difference is generated between the passivation layer 16 on the transition portion 152 and the passivation layer 16 on the flat portion 151. Therefore, when performing relief printing, the alignment material at the edge (i.e., at the transition portion 152) flows toward the non-display region 10B due to the height difference, thereby avoiding the problem of the alignment material being deposited thick at the edge of the display region.
The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understanding the technical solutions and the core ideas of the present application. Those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel comprising a display area and a non-display area, the non-display area surrounding the display area, characterized in that: the display panel includes:
a substrate;
the buffer layer is arranged on the substrate, wherein the buffer layer is positioned in the display area and the non-display area;
the grid insulating layer is arranged on the buffer layer, and the grid insulating layer is positioned in the display area and the non-display area;
an interlayer dielectric layer disposed on the gate insulating layer, wherein the interlayer dielectric layer is located in the display region and the non-display region;
a flat layer disposed on the interlayer dielectric layer, the flat layer including a flat portion and a transition portion adjacent to each other, the flat portion being disposed in the display region, the transition portion being disposed in a portion of the non-display region adjacent to the display region, wherein a thickness at the flat portion is greater than a thickness at the transition portion;
a passivation layer disposed on the flat portion and the transition portion; and
and the alignment layer is arranged on the passivation layer.
2. The display panel of claim 1, wherein: the transition portion further comprises at least one protrusion.
3. The display panel of claim 2, wherein: the shape of the at least one protrusion includes at least one of a cylinder, a cone, an angular cylinder, and a pyramid.
4. The display panel of claim 1, wherein: the transition portion has a slope, wherein the slope starts from the interface of the flat portion and the transition portion and extends obliquely downward.
5. The display panel of claim 4, wherein: the bevel extends obliquely downward until it meets the interlevel dielectric layer.
6. A method of manufacturing a display panel including a display area and a non-display area surrounding the display area, characterized in that: the manufacturing method of the display panel comprises the following steps:
providing a substrate;
forming a buffer layer on the substrate, wherein the buffer layer is located in the display region and the non-display region;
forming a gate insulating layer on the buffer layer, wherein the gate insulating layer is located in the display region and the non-display region;
forming an interlayer dielectric layer on the gate insulating layer, wherein the interlayer dielectric layer is located in the display region and the non-display region;
forming a flat layer on the interlayer dielectric layer, wherein the flat layer comprises a flat portion and a transition portion which are adjacent to each other, the flat portion is arranged in the display area, the transition portion is arranged in a portion of the non-display area adjacent to the display area, and the thickness of the flat portion is larger than that of the transition portion;
forming a passivation layer on the flat portion and the transition portion; and
and forming an alignment layer on the passivation layer.
7. The method for manufacturing a display panel according to claim 6, wherein: the transition portion further comprises at least one protrusion.
8. The method for manufacturing a display panel according to claim 6 or 7, wherein: the step of forming the planarization layer on the interlayer dielectric layer comprises: the flat layer is formed by a gray-tone mask method or a halftone mask method.
9. The method for manufacturing a display panel according to claim 6, wherein: the transition portion has a slope, wherein the slope starts from the interface of the flat portion and the transition portion and extends obliquely downward.
10. The method for manufacturing a display panel according to claim 7, wherein: the bevel extends obliquely downward until it meets the interlevel dielectric layer.
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| CN107085324A (en) * | 2017-06-09 | 2017-08-22 | 厦门天马微电子有限公司 | Substrate and the liquid crystal display panel comprising it |
| CN107819014A (en) * | 2017-10-25 | 2018-03-20 | 武汉华星光电技术有限公司 | Flexible display panels and preparation method thereof |
| CN207381403U (en) * | 2017-08-31 | 2018-05-18 | 京东方科技集团股份有限公司 | Display base plate, display panel |
| CN110850639A (en) * | 2019-10-22 | 2020-02-28 | 武汉华星光电技术有限公司 | Display panel, mask plate and display device |
| CN110967884A (en) * | 2019-11-29 | 2020-04-07 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN110993814A (en) * | 2019-11-15 | 2020-04-10 | 深圳市华星光电半导体显示技术有限公司 | Display device and method for manufacturing the same |
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| CN107085324A (en) * | 2017-06-09 | 2017-08-22 | 厦门天马微电子有限公司 | Substrate and the liquid crystal display panel comprising it |
| CN207381403U (en) * | 2017-08-31 | 2018-05-18 | 京东方科技集团股份有限公司 | Display base plate, display panel |
| CN107819014A (en) * | 2017-10-25 | 2018-03-20 | 武汉华星光电技术有限公司 | Flexible display panels and preparation method thereof |
| CN110850639A (en) * | 2019-10-22 | 2020-02-28 | 武汉华星光电技术有限公司 | Display panel, mask plate and display device |
| CN110993814A (en) * | 2019-11-15 | 2020-04-10 | 深圳市华星光电半导体显示技术有限公司 | Display device and method for manufacturing the same |
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