CN111679524B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN111679524B CN111679524B CN202010534005.8A CN202010534005A CN111679524B CN 111679524 B CN111679524 B CN 111679524B CN 202010534005 A CN202010534005 A CN 202010534005A CN 111679524 B CN111679524 B CN 111679524B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/22—Antistatic materials or arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
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Abstract
The invention discloses a display panel and a display device, wherein the display panel is provided with a display area and a non-display area positioned on the periphery of the display area, the non-display area comprises an electrostatic protection area and a binding area, the display panel comprises an array substrate, an electricity leading structure is arranged on the array substrate and arranged in the electrostatic protection area, the electricity leading structure comprises an electricity leading part, a groove and an electricity leading tip are arranged on the electricity leading part, and the electricity leading tip protrudes towards the groove or the electricity leading tip protrudes towards one side far away from the array substrate. The grooves are etched on the electricity leading parts, the electricity leading tips protruding towards the grooves are formed, or the electricity leading tips are directly arranged on the electricity leading parts, so that electric charges on the array substrate are gathered on the electricity leading tips, the GIA circuit on the array substrate is protected, the electrostatic protection capability of the display panel is improved, and the display panel is prevented from being short-circuited or broken when the ESD protection capability is tested.
Description
Technical Field
The present invention relates to the field of liquid crystal display technologies, and in particular, to a display panel and a display device.
Background
A Liquid Crystal Display (LCD) has advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and is dominant in the field of flat panel displays. The liquid crystal display device includes a color filter substrate and a thin film transistor array substrate which are oppositely disposed, and a liquid crystal layer interposed therebetween.
Touch display screens have been widely used in many fields such as personal computers, smart phones, public information, smart appliances, industrial control, and the like. In the current touch field, there are mainly resistive touch screens, photoelectric touch screens, ultrasonic touch screens, planar capacitive touch screens, which are also externally hung and built-in according to the position distribution.
The principle of the touch display screen is that after a user touches the screen with a finger, capacitance on a touch layer changes, and therefore the position of the finger and an operation instruction are recognized. Since the touch signal applied to the touch layer in the touch display screen may interfere with the normal polarization of the liquid crystal, a shielding electrode is usually disposed on the color film substrate to prevent the signals in the touch layer and the liquid crystal cell from interfering with each other. After the display panel is manufactured, an ESD (Electro-Static discharge) protection capability test is performed on the display panel, and it is often found that the ESD protection capability cannot reach a specification value, mainly because the shielding electrode has a large resistance, and cannot rapidly lead out charges and cause a secondary discharge phenomenon, so that a liquid crystal layer is broken down and is applied to an array substrate, a gate driver array (GIA) circuit on the array substrate is shorted or disconnected, and an image is abnormal.
Disclosure of Invention
In order to overcome the disadvantages and shortcomings of the prior art, the present invention provides a display panel and a display device, so as to solve the problem that the display panel in the prior art is easy to cause short circuit or disconnection of the GIA circuit during the ESD protection capability test.
The purpose of the invention is realized by the following technical scheme:
the invention provides a display panel, which is provided with a display area and a non-display area positioned at the periphery of the display area, wherein the non-display area comprises an electrostatic protection area and a binding area, the display panel comprises an array substrate, an electricity leading structure is arranged on the array substrate and arranged in the electrostatic protection area, the electricity leading structure comprises an electricity leading part, a groove and an electricity leading tip are arranged on the electricity leading part, and the electricity leading tip protrudes towards the groove or the electricity leading tip protrudes towards one side far away from the array substrate.
Furthermore, the electricity leading structure further comprises a first capacitor plate and a second capacitor plate, the first capacitor plate and the second capacitor plate are located on different layers and are insulated and isolated, at least parts of the first capacitor plate and the second capacitor plate are overlapped to form a buffer capacitor, and the electricity leading part is electrically connected with the first capacitor plate.
Furthermore, the first capacitor plate comprises a first lead and a first lead-out wire, the second capacitor plate comprises a second lead and a second lead-out wire, the first lead and the second lead are overlapped up and down, the first lead-out wire and the second lead-out wire are overlapped up and down, and the lead part is arranged above the first lead and is in contact connection with the first lead.
Furthermore, the extending directions of the first lead and the second lead are perpendicular to the extending directions of the first lead and the second lead, and the first lead and the second lead extend towards one side far away from the display area.
Furthermore, the number of the first lead, the number of the second lead and the number of the power-leading parts are the same and are at least two, and each first lead is correspondingly connected with one power-leading part.
Further, a gate insulating layer and an active material layer are disposed between the first capacitor plate and the second capacitor plate, and the active material layer is disposed above the gate insulating layer.
Further, the shape of the opening of the groove comprises one of a cross shape, a V shape or a W shape.
Furthermore, the binding region is disposed at the edge of one side of the display region, and the electrostatic protection region is disposed at the edges of the other three sides of the display region.
Furthermore, the display panel further comprises a color film substrate arranged opposite to the array substrate and a liquid crystal layer positioned between the color film substrate and the array substrate, the array substrate is also provided with a common electrode and a pixel electrode, and the electricity leading part and the common electrode or the pixel electrode are positioned on the same layer.
The invention also provides a display device comprising the display panel.
The invention has the beneficial effects that: the display panel has the display area and is located the peripheral non-display area of display area, and the non-display area includes the electrostatic protection district and binds the district, and display panel includes array substrate, is equipped with on the array substrate and draws electric structure, draws electric structure to locate in the electrostatic protection district, draws electric structure to include and draws electric portion, draws to be equipped with the recess in the electric portion and draws electric point, draws electric point to the recess protrusion, perhaps, draws electric point to the one side protrusion of keeping away from array substrate. The grooves are etched on the electricity leading parts, the electricity leading tips protruding towards the grooves are formed, or the electricity leading tips are directly arranged on the electricity leading parts, so that electric charges on the array substrate are gathered on the electricity leading tips, the GIA circuit on the array substrate is protected, the electrostatic protection capability of the display panel is improved, and the display panel is prevented from being short-circuited or broken when the ESD protection capability is tested.
Drawings
Fig. 1 is a schematic plan view illustrating a display panel according to an embodiment of the invention;
FIG. 2 is an enlarged schematic view of the structure at A in FIG. 1;
FIG. 3 is a schematic diagram of a partial plan view of a first capacitor plate according to an embodiment of the invention;
FIG. 4 is a schematic perspective cross-sectional view of a current guiding structure according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a power guiding structure according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a display panel in an initial state according to an embodiment of the invention;
FIG. 7 is a schematic structural diagram of a display panel in a display state according to an embodiment of the invention;
fig. 8 is a schematic perspective cross-sectional view of a power conducting structure in a second embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the display panel and the display device according to the present invention with reference to the accompanying drawings and the preferred embodiments is as follows:
[ example one ]
Fig. 1 is a schematic plan view of a display panel according to a first embodiment of the present invention, fig. 2 is an enlarged schematic structural diagram at a point a in fig. 1, fig. 3 is a schematic partial plan view of a first capacitor plate according to a first embodiment of the present invention, fig. 4 is a schematic perspective sectional structural diagram of a power-on structure according to a first embodiment of the present invention, fig. 5 is a schematic sectional structural diagram of the power-on structure according to a first embodiment of the present invention, fig. 6 is a schematic structural diagram of the display panel in an initial state according to a first embodiment of the present invention, and fig. 7 is a schematic structural diagram of the display panel in a display state according to a first embodiment of the present invention.
As shown in fig. 1 to 7, a display panel according to a first embodiment of the present invention includes a display area 101 and a non-display area 102 located at a periphery of the display area 101, where the non-display area 102 includes an electrostatic protection area 102a and a binding area 102 b. The display area 101 has a plurality of sub-pixels and is used to normally display a picture, and the binding area 102b is used to bind a wire in the display panel with an external chip to apply a control signal to the display panel and control normal display of the display panel.
As shown in fig. 4, 5, 6 and 7, the display panel includes a color filter substrate 10, an array substrate 20 disposed opposite to the color filter substrate 10, and a liquid crystal layer 30 located between the color filter substrate 10 and the array substrate 20. Preferably, positive liquid crystal molecules, that is, liquid crystal molecules having positive dielectric anisotropy, are used in the liquid crystal layer 30, and in an initial state, the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color filter substrate 10 and the array substrate 20, and the alignment directions of the positive liquid crystal molecules on a side close to the color filter substrate 10 and the positive liquid crystal molecules on a side close to the array substrate 20 are parallel or antiparallel.
The color film substrate 10 is provided with color resist layers 11 arranged in an array and black matrixes 12 separating the color resist layers 11, the black matrixes 12 are distributed in a mesh shape in the display area 101, and the black matrixes 12 completely cover the non-display area 102. The color resist layer 11 is disposed in the display region 101, and the color resist layer 11 includes color resist materials of three colors of red (R), green (G), and blue (B), and correspondingly forms sub-pixels of the three colors of red (R), green (G), and blue (B). The color resist layer 11 and the black matrix 12 are further provided with a shielding electrode 13 on the whole surface on the side facing the liquid crystal layer 30 to prevent mutual interference of signals in the touch layer and the liquid crystal cell.
The array substrate 20 is provided with an electrical structure 21, and the electrical structure 21 is disposed in the electrostatic protection region 102a of the non-display region 102. The electricity leading structure 21 includes an electricity leading portion 211, and a groove 211a and an electricity leading tip 211b are provided on the electricity leading portion 211, and the electricity leading tip 211b protrudes toward the groove 211 a. Specifically, a metal layer is coated on the flat layer 202 and etched to form the electrical conducting portion 211, a through hole is formed in the flat layer 202, and the electrical conducting portion 211 forms a groove 211a in the through hole. In this embodiment, the shape of the opening of the groove 211a includes a cross shape, the conducting tips 211b are located at the intersection of the cross shape, that is, the conducting tips 211b are formed at the same time when the cross-shaped groove 211a is formed, and each conducting portion 211 has four conducting tips 211 b. Of course, the opening of the recess 211a may have a concave shape such as a "V" shape, a "W" shape, or a pentagram shape. The conducting tip 211b is similar to a lightning rod, so that charges on the array substrate 20 are accumulated on the conducting tip 211b to protect the GIA circuit on the array substrate 10, thereby increasing the electrostatic protection capability of the display panel and preventing the display panel from causing short circuit or disconnection of the GIA circuit during the ESD protection capability test.
In this embodiment, the electricity guiding structure 21 further includes a first capacitor plate 212 and a second capacitor plate 213, the first capacitor plate 212 and the second capacitor plate 213 are located at different layers and isolated from each other, the first capacitor plate 212 and the second capacitor plate 213 are at least partially overlapped to form a buffer capacitor, and the electricity guiding portion 211 is electrically connected to the first capacitor plate 212 at the through hole of the planarization layer 202. When the high voltage static electricity is applied to the leading tip 211b and is not ready to be led out, the buffer capacitor can effectively reduce the voltage and prevent the high voltage static electricity from being discharged again and applied to the GIA circuit, so as to avoid the short circuit or disconnection of the GIA circuit.
Further, a gate insulating layer 201 and an active material layer 214 are disposed between the first capacitor plate 212 and the second capacitor plate 213, and the active material layer 214 is located above the gate insulating layer 201. An active material layer 214 is remained between the first capacitor plate 212 and the second capacitor plate 213, so as to raise the leading portion 211, make the leading tip 211b more easily shocked by the high voltage static electricity, prevent the high voltage static electricity from hitting the GIA circuit, and increase the electrostatic protection capability of the display panel.
As shown in fig. 3, in the present embodiment, the first capacitor plate 212 includes a first lead 212a and a first lead-out line 212b, the second capacitor plate 213 includes a second lead and a second lead-out line, the first lead 212a and the second lead are overlapped with each other, the first lead 212b and the second lead are overlapped with each other, the lead portion 211 is disposed above the first lead 212a and connected to the first lead 212a in a contact manner, and the structure of the second capacitor plate 213 can refer to fig. 3. The first and second capacitor plates 212, 213 are identical in shape and size and overlap one another. The two ends of the first lead-out line 212b and the second lead-out line are both grounded, so that the charges on the first capacitor plate 212 and the second capacitor plate 213 can be led out quickly, and the lead-out capability of the charges is enhanced.
Further, the extending directions of the first lead 212a and the second lead are perpendicular to the extending directions of the first lead 212b and the second lead, and the first lead 212a and the second lead extend toward a side away from the display region 101. The number of the first leads 212a, the number of the second leads and the number of the electrical guiding portions 211 are at least two, and each first lead 212a is correspondingly connected with one electrical guiding portion 211. When the leading tip 211b is electrostatically shocked by high voltage, only the corresponding first lead 212a is damaged, and the entire leading structure 21 is not damaged, and other leading tips 211b without damage can also play a role of electrostatic protection.
In this embodiment, the binding region 102b is disposed at the edge of one side of the display region 101, the electrostatic protection region 102a is disposed at the edge of the other three sides of the display region 101, that is, the edge of one side of the display region 101 is used for disposing the binding region 102b, and the rest of the edges are used for disposing the electrostatic protection region 102 a. The charging structure 21 has the same overall shape as the electrostatic protection region 102 a.
In this embodiment, the array substrate 20 is defined by a plurality of scan lines (not shown) and a plurality of data lines (not shown) crossing each other in an insulated manner on a side facing the liquid crystal layer 30 to form a plurality of pixel units, a pixel electrode 23 and a thin film transistor 24 are disposed in each pixel unit, and the pixel electrode 23 is electrically connected to the data line of the adjacent thin film transistor 24 through the thin film transistor 24. The thin film transistor 24 includes a gate electrode 241, an active layer 242, a source electrode 243, and a drain electrode 244, the gate electrode 241, a scan line, and the second capacitor plate 213 are located in the same layer and made of the same metal layer, the gate electrode 241 is electrically connected to the scan line, the gate electrode 241 is separated from the active layer 242 by the gate insulating layer 201, the active layer 242 and the active layer 214 are located in the same layer and made of the same active layer film, the source electrode 243 is electrically connected to the data line, the drain electrode 244 is electrically connected to the pixel electrode 23 through a contact hole on the planarization layer 202, and the source electrode 243, the drain electrode 244, the data line, and the first capacitor plate 212 are located in the same layer and made of the same metal layer.
As shown in fig. 6 and 7, in the present embodiment, the common electrode 22 is further disposed on a side of the array substrate 20 facing the liquid crystal layer 30, and the common electrode 22 and the pixel electrode 23 are located at different layers and insulated and isolated by an insulating layer. The electricity drawing portion 211 is formed of the same transparent conductive layer as the common electrode 22, but the electricity drawing portion 211 may be formed of the same transparent conductive layer as the pixel electrode 23. The common electrode 22 may be located above or below the pixel electrode 23 (the common electrode 22 is shown below the pixel electrode 23 in fig. 6). Preferably, the common electrode 22 is a planar electrode disposed over the entire surface, and the pixel electrode 23 is a block electrode disposed in one block in each pixel unit or a slit electrode having a plurality of electrode bars to form a Fringe Field Switching (FFS) mode. Of course, In other embodiments, the pixel electrode 23 and the common electrode 22 may be located on the same layer, but they are insulated from each other, and each of the pixel electrode 23 and the common electrode 22 may include a plurality of electrode stripes, and the electrode stripes of the pixel electrode 23 and the electrode stripes of the common electrode 22 are alternately arranged to form an In-Plane Switching (IPS) mode; or, in other embodiments, the array substrate 20 is provided with the pixel electrode 23 on a side facing the liquid crystal layer 30, and the color filter substrate 10 is provided with the common electrode 22 on a side facing the liquid crystal layer 30, so as to form a TN mode or a VA mode, and for other descriptions of the TN mode and the VA mode, reference is made to the prior art, and details are not repeated here.
In this embodiment, an upper polarizer is disposed on the color filter substrate 10, a lower polarizer is disposed on the array substrate 20, and a transmission axis of the lower polarizer is perpendicular to a transmission axis of the upper polarizer. A sealing adhesive 40 is disposed between the color film substrate 10 and the array substrate 20, the sealing adhesive 40 is located in the non-display region 102 around the display panel, and the sealing adhesive 40 may cover the electric conduction structure 21, or the electric conduction structure 21 may also be disposed inside the sealing adhesive 40 (i.e., the side of the sealing adhesive 40 facing the liquid crystal layer 30).
The color film substrate 10 and the array substrate 20 may be made of glass, acrylic acid, polycarbonate, and other materials. The materials of the lead portion 211, the common electrode 22, and the pixel electrode 23 may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like.
[ example two ]
Fig. 8 is a schematic perspective sectional view of a current guiding structure in a second embodiment of the present invention. The display panel according to the second embodiment of the present invention is substantially the same as the display panel according to the first embodiment (fig. 1 to 7), except that in this embodiment, the conductive tip 211b protrudes toward a side away from the array substrate 20, the conductive portion 211 is electrically connected to the first capacitor plate 212 at the through hole of the planarization layer 202, the conductive portion 211 forms a groove 211a at the through hole of the planarization layer 202, and the conductive tip 211b and the groove 211a are staggered from each other at the position of the conductive portion 211.
In this embodiment, the height of the conductive tip 211b is increased and the electrostatic protection capability of the conductive tip 211b is enhanced by protruding the conductive tip 211b toward the side away from the array substrate 20, but a manufacturing process is added to manufacture the protrusion corresponding to the conductive tip 211b on the planarization layer 202.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
The invention also provides a display device comprising the display panel.
In this document, the terms upper, lower, left, right, front, rear and the like are used for defining the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the clarity and convenience of the technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It should also be understood that the terms "first," "second," and the like, as used herein, are used merely for descriptive purposes and not for limiting quantity or order.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A display panel is provided, the display panel has a display area (101) and a non-display area (102) located at the periphery of the display area (101), the non-display area (102) includes an electrostatic protection area (102a) and a binding area (102b), the display panel includes an array substrate (20), an electric leading structure (21) is disposed on the array substrate (20), the electric leading structure (21) is disposed in the electrostatic protection area (102a), the electric leading structure (21) includes an electric leading portion (211), a first capacitor plate (212) and a second capacitor plate (213), the first capacitor plate (212) and the second capacitor plate (213) are both connected to a ground line, the first capacitor plate (212) and the second capacitor plate (213) are located at different layers and are insulated and isolated, the first capacitor plate (212) and the second capacitor plate (213) are at least partially overlapped, the electricity leading part (211) is electrically connected with the first capacitor plate (212); the first capacitor plate (212) comprises a first lead (212a) and a first lead-out line (212b), the second capacitor plate (213) comprises a second lead and a second lead-out line, the first lead (212a) and the second lead are overlapped up and down, the first lead-out line (212b) and the second lead are overlapped up and down, and the lead part (211) is arranged above the first lead (212a) and is in contact connection with the first lead (212 a); the extending directions of the first lead (212a) and the second lead are perpendicular to the extending directions of the first lead (212b) and the second lead, and the first lead (212a) and the second lead extend towards one side far away from the display area (101); the number of the first leads (212a), the number of the second leads and the number of the electric leading parts (211) are the same and are at least two, and each first lead (212a) is correspondingly connected with one electric leading part (211);
the electricity leading part (211) is provided with a groove (211a) and an electricity leading tip (211b), and the electricity leading tip (211b) protrudes towards the groove (211a) or the electricity leading tip (211b) protrudes towards the side far away from the array substrate (20).
2. The display panel of claim 1, wherein a gate insulating layer (201) and an active material layer (214) are disposed between the first capacitor plate (212) and the second capacitor plate (213), the active material layer (214) being disposed over the gate insulating layer (201).
3. The display panel of claim 1, wherein the shape of the opening of the recess (211a) comprises one of a cross shape, a V shape or a W shape.
4. The display panel of claim 1, wherein the bonding region (102b) is disposed at the edge of one side of the display region (101), and the electrostatic discharge protection region (102a) is disposed at the edge of the other three sides of the display region (101).
5. The display panel according to claim 1, further comprising a color filter substrate (10) disposed opposite to the array substrate (20) and a liquid crystal layer (30) disposed between the color filter substrate (10) and the array substrate (20), wherein a common electrode (22) and a pixel electrode (23) are further disposed on the array substrate (20), and the power-on portion (211) is disposed on the same layer as the common electrode (22) or the pixel electrode (23).
6. A display device characterized by comprising the display panel according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010534005.8A CN111679524B (en) | 2020-06-12 | 2020-06-12 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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