CN111668264A

CN111668264A - Display unit, display device, and method of manufacturing display unit

Info

Publication number: CN111668264A
Application number: CN202010149953.XA
Authority: CN
Inventors: 林亨埈; 苏栋润; 朴庆珉
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2019-03-08
Filing date: 2020-03-06
Publication date: 2020-09-15
Also published as: US20230354684A1; US20200286965A1; KR20200108200A; US10916596B2; US20210242290A1; US11730044B2

Abstract

The present disclosure relates to a display unit, a display device, and a method of manufacturing a display unit. The display unit includes: a signal line electrically connected to the pixels arranged in the display region; a signal pad unit disposed in a peripheral region adjacent to the display region and including a signal pad electrically connected to the signal line; an inspection pad unit disposed in the conduction inspection region and including an inspection pad electrically connected to the signal pad, wherein the inspection pad is configured to receive a conduction inspection signal; and a power supply voltage line configured to apply a power supply voltage to the pixel, the power supply voltage line extending from the inspection pad unit to the peripheral region, and the power supply voltage line being divided into a plurality of sub-lines by at least one slit pattern in a cut-off region between the peripheral region and the conduction inspection region.

Description

Display unit, display device, and method of manufacturing display unit

Technical Field

Some embodiments of the inventive concept relate to a display unit, a display apparatus, and a method of manufacturing the display unit.

Background

Recently, various flat panel display devices having reduced weight and volume as compared to Cathode Ray Tube (CRT) displays have been developed. The flat panel display device includes a Liquid Crystal Display (LCD), a Field Emission Display (FED), a Plasma Display Panel (PDP), an Organic Light Emitting Diode (OLED) display, an inorganic electroluminescent display, and a quantum dot light emitting diode (QLED or QD-LED) display.

The OLED display displays an image by using an organic light emitting diode that emits light by recombination between electrons and holes. The OLED display has a fast response speed and is driven with low power consumption.

The OLED display includes an organic light emitting display panel, and the organic light emitting display panel performs an array inspection for inspecting electrical defects in a state of a display unit and a conduction inspection for inspecting conduction defects.

After the array inspection and the conduction inspection, a module process is performed. The module process comprises the following steps: a step of cutting an inspection region of the organic light emitting display panel, the inspection region having an inspection pad and an inspection circuit formed thereon for array inspection and conduction inspection; and a step of attaching the polarizing plate, the protective film, and the flexible circuit board having the driving chip mounted thereon to the cut organic light emitting display panel.

Disclosure of Invention

Some embodiments of the inventive concept provide a display unit for preventing cracks during a manufacturing process, a display apparatus including the display unit, and a method of manufacturing the display unit.

According to some embodiments of the inventive concept, a display unit includes: a signal line electrically connected to the pixels arranged in the display region; a signal pad unit disposed in a peripheral region adjacent to the display region and including a signal pad electrically connected to the signal line; an inspection pad unit disposed in the conduction inspection region and including an inspection pad electrically connected to the signal pad, wherein the inspection pad is configured to receive a conduction inspection signal; and a power supply voltage line for applying a power supply voltage to the pixel, the power supply voltage line extending from the inspection pad unit to the peripheral region, and the power supply voltage line being divided into a plurality of sub-lines by at least one slit pattern in a cut-off region between the peripheral region and the conduction inspection region.

In some embodiments of the inventive concept, the display unit may further include: an insulating film exposing the at least one slit pattern and the plurality of sub-lines in the cut-out region. Slit pattern

In some embodiments of the inventive concept, the insulating film may include: an inorganic insulating film provided over a gate electrode of a transistor included in the pixel; and an organic insulating film disposed over the source electrode and the drain electrode of the transistor.

In some embodiments of the inventive concept, the at least one slit pattern may have a width corresponding to an extending direction of the cutting line and a length corresponding to a direction intersecting the extending direction.

In some embodiments of the inventive concept, the width of the at least one slit pattern may be greater than a pitch of laser spots used during a cutting process.

In some embodiments of the inventive concept, the plurality of sub lines may have a line width corresponding to the extension direction of the cutting line, and the line width is greater than the pitch of the laser spots.

In some embodiments of the inventive concept, a width of the power supply voltage line located in the cut-off region may be determined according to a resistivity characteristic of the plurality of sub-lines.

In some embodiments of the inventive concept, the display unit may further include: a conduction check circuit disposed in the conduction check region and electrically connected to the check pad unit.

In some embodiments of the inventive concept, the pixel may include an organic light emitting diode, and the power supply voltage line may include at least one of a first power supply voltage line transferring a first power supply voltage to the organic light emitting diode and a second power supply voltage line transferring a second power supply voltage to the organic light emitting diode.

In some embodiments of the inventive concept, the peripheral region may include: a first peripheral region in which the signal pad unit is disposed, a second peripheral region adjacent to the first peripheral region, a third peripheral region facing the second peripheral region, and a fourth peripheral region facing the first peripheral region, the first to fourth peripheral regions may surround the display region, and the first power supply voltage line may extend from the inspection pad unit and be disposed in the first peripheral region.

In some embodiments of the inventive concept, the second power voltage line may extend from the inspection pad unit and be disposed in the second peripheral region, the third peripheral region, and the fourth peripheral region.

According to some embodiments of the inventive concept, a display apparatus includes: a display unit comprising: a signal line electrically connected to the pixels arranged in the display region; a signal pad unit disposed in a peripheral region adjacent to the display region and including a signal pad electrically connected to the signal line; and a power voltage line disposed in the peripheral region to apply a power voltage to the pixels and divided into a plurality of sub-lines in an edge region; and a flexible circuit board bonded to the signal pad unit through an anisotropic conductive film, wherein a driving integrated circuit for driving the display unit is mounted over the flexible circuit board.

In some embodiments of the inventive concept, the display unit may further include: an insulating film exposing the plurality of sub-lines disposed in the edge region.

In some embodiments of the inventive concept, the pixel may include an organic light emitting diode, and the power voltage line may include at least one of a first power voltage line and a second power voltage line, the first power voltage line transmitting a first power voltage to the organic light emitting diode, and the second power voltage line transmitting a second power voltage to the organic light emitting diode. .

In some embodiments of the inventive concept, the peripheral region may include: a first peripheral region in which the signal pad unit is disposed, a second peripheral region adjacent to the first peripheral region, a third peripheral region facing the second peripheral region, and a fourth peripheral region facing the first peripheral region, the first to fourth peripheral regions may surround the display region, and the first power supply voltage line may extend from the edge region and be disposed in the first peripheral region.

In some embodiments of the inventive concept, the second power voltage line may extend from the edge region and be disposed in the second peripheral region, the third peripheral region, and the fourth peripheral region.

According to some embodiments of the inventive concept, in a method of manufacturing a display unit, a signal line is formed, the signal line being electrically connected to a pixel disposed in a display region; forming a signal pad disposed in a peripheral region adjacent to the display region and electrically connected to the signal line; forming an inspection pad disposed in a conduction inspection region and electrically connected to the signal pad so that a conduction inspection signal is applied to the inspection pad; and forming a power supply voltage line extending from the inspection pad to the peripheral region and divided into a plurality of sub-lines by at least one slit pattern in a cut-off region between the peripheral region and the conduction inspection region.

In some embodiments of the inventive concept, the at least one slit pattern and the plurality of sub-lines may be exposed by removing the insulating film disposed over the at least one slit pattern and the plurality of sub-lines in the cut-off region.

In some embodiments of the inventive concept, the at least one slit pattern may have a width of the slit pattern corresponding to an extending direction of a cutting line, the width of the slit pattern may be greater than a pitch of laser spots used in a cutting process, the plurality of sub-lines may have a line width corresponding to the extending direction of the cutting line, and the line width may be greater than the pitch of the laser spots.

Drawings

The above and other features of the present inventive concept will be more fully understood from the detailed description of some embodiments of the inventive concept with reference to the accompanying drawings.

Fig. 1 is a plan view for explaining a display unit according to an embodiment of the inventive concept.

Fig. 2 is a pixel circuit diagram for explaining a pixel included in the display unit of fig. 1 according to an embodiment of the inventive concept.

Fig. 3 is a conceptual diagram for explaining a conduction check apparatus for the display unit of fig. 1 according to an embodiment of the inventive concept.

Fig. 4 is an enlarged view of a portion 'a' of fig. 1 to illustrate a structure of a power supply voltage line according to an embodiment of the inventive concept.

Fig. 5 is an enlarged view of a portion 'B' of fig. 4 for explaining a slit pattern and sub-lines in a cut-away area according to an embodiment of the inventive concept.

Fig. 6 is a cross-sectional view of the display unit of fig. 1 according to an embodiment of the inventive concept.

Fig. 7 and 8 are schematic views for explaining a laser cutting process according to a comparative example and an embodiment of the inventive concept, respectively.

Fig. 9A and 9B are conceptual diagrams describing various voltage lines according to some embodiments of the inventive concept.

Fig. 10 is a plan view of a display device according to an embodiment of the inventive concept.

Detailed Description

Hereinafter, some embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout this application, like reference numerals may refer to like elements.

It will be understood that when an element or layer is referred to as being "on," "over," "connected to," or "coupled to" another element or layer, it can be directly on, over, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Spatially relative terms such as "below … …," "below … …," "below," "under … …," "above … …," "above … …," and "on" may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device is turned over in the drawings, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below … …" and "below … …" can encompass both orientations of "above … …" and "below … …". The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements, or one or more intervening layers or elements may also be present.

Fig. 1 is a plan view for explaining a display unit according to an embodiment of the inventive concept. Fig. 2 is a pixel circuit diagram for explaining a pixel included in the display unit of fig. 1 according to an embodiment of the inventive concept. Fig. 3 is a conceptual diagram for explaining a conduction check apparatus for the display unit of fig. 1 according to an embodiment of the inventive concept.

Referring to fig. 1, the display unit 100 includes: a pixel PX that displays an image; a first power voltage line VL1 which transmits the first power voltage ELVDD to the pixels PX; and a second power voltage line VL2 which transmits the second power voltage ELVSS to the pixels PX.

In an embodiment of the inventive concept, the pixels PX may include organic light emitting diodes, the first power voltage ELVDD may be a high power voltage applied to the organic light emitting diodes, and the second power voltage ELVSS may be a low power voltage applied to the organic light emitting diodes.

For example, the display unit 100 may include a display area DA in which the pixels PX are arranged and a non-display area surrounding the display area DA in which the first and second power supply voltage lines VL1 and VL2 are arranged.

The display area DA may include a plurality of pixels PX arranged in a matrix form, and a plurality of data lines DL and a plurality of scan lines SL electrically connected to the plurality of pixels PX.

The data lines DL may extend in a first direction DR1, and may be aligned in a second direction DR2 intersecting the first direction DR 1.

The scan lines SL may extend in the second direction DR2, and may be aligned in the first direction DR 1.

Referring to fig. 2, the pixel PX may include a pixel circuit PXC.

The pixel circuit PXC may include an organic light emitting diode OLED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

The anode of the organic light emitting diode OLED may be electrically connected to the first transistor T1 via the sixth transistor T6, and the cathode may be electrically connected to the second power supply voltage ELVSS. The organic light emitting diode OLED may generate light having a luminance corresponding to the amount of current supplied from the first transistor T1.

The first power supply voltage ELVDD may be set to a voltage higher than the second power supply voltage ELVSS such that a current flows to the organic light emitting diode OLED.

The seventh transistor T7 may be electrically connected between the initialization power supply VINT and the anode of the organic light emitting diode OLED. In addition, the gate electrode of the seventh transistor T7 may be electrically connected to the (i +1) th scan line S1i +1 or the (i-1) th scan line S1 i-1. When the scan signal is supplied to the (i +1) th scan line S1i +1 or the (i-1) th scan line S1i-1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply VINT may be supplied to the anode of the organic light emitting diode OLED. Here, the initialization power supply VINT may be set to a voltage lower than that of the data signal.

The sixth transistor T6 may be electrically connected between the first transistor T1 and the organic light emitting diode OLED. In addition, a gate electrode of the sixth transistor T6 may be electrically connected to the ith light emission control line E1 i. When the light emission control signal is supplied to the ith light emission control line E1i, the sixth transistor T6 may be turned on.

The fifth transistor T5 may be electrically connected between the first power supply voltage ELVDD and the first transistor T1. In addition, a gate electrode of the fifth transistor T5 may be electrically connected to the ith light emission control line E1 i. When the light emission control signal is supplied to the ith light emission control line E1i, the fifth transistor T5 may be turned on.

A first electrode of the first transistor T1 (driving transistor) may be electrically connected to the first power voltage ELVDD via the fifth transistor T5, and a second electrode may be electrically connected to an anode electrode of the organic light emitting diode OLED via the sixth transistor T6. In addition, a gate electrode of the first transistor T1 may be electrically connected to the first node N1. In response to the voltage of the first node N1, the first transistor T1 may control the amount of current flowing from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the organic light emitting diode OLED.

The third transistor T3 may be electrically connected between the second electrode of the first transistor T1 and the first node N1. In addition, a gate electrode of the third transistor T3 may be electrically connected to the ith scan line S1 i. When the scan signal is supplied to the ith scan line S1i, the third transistor T3 may be turned on so that the second electrode of the first transistor T1 may be electrically connected to the first node N1. Accordingly, when the third transistor T3 is turned on, the first transistor T1 may be electrically connected in the form of a diode.

The fourth transistor T4 may be electrically connected between the first node N1 and the initialization power supply VINT. In addition, the gate electrode of the fourth transistor T4 may be electrically connected to the (i-1) th scan line S1 i-1. When the scan signal is supplied to the (i-1) th scan line S1i-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply VINT may be supplied to the first node N1.

The second transistor T2 may be electrically connected between the mth data line Dm and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be electrically connected to the ith scan line S1 i. When the scan signal is supplied to the ith scan line S1i, the second transistor T2 may be turned on so that the mth data line Dm may be electrically connected to the first electrode of the first transistor T1.

The storage capacitor CST may be electrically connected between the first power supply voltage ELVDD and the first node N1. The storage capacitor CST may store the data signal and a voltage corresponding to a threshold voltage of the first transistor T1.

Referring back to fig. 1, the non-display area includes a first peripheral area PA1, a second peripheral area PA2, a third peripheral area PA3, and a fourth peripheral area PA4 surrounding the display area DA. In addition, the non-display region may include a cut-out region CA adjacent to the first peripheral region PA1 and a conduction check region TSA adjacent to the cut-out region CA.

The first peripheral area PA1 corresponds to a first end of the data line DL and is adjacent to the display area DA. The first peripheral area PA1 may include a fan-out area FOA and a signal pad area SPA.

Fan-out lines FOL electrically connected to signal lines such as the data lines DL may be arranged in the fan-out region FOA. The signal pad unit SPD may be disposed in the signal pad region SPA, on or over which signal pads electrically connected to the fanout line FOL are arranged.

The second peripheral area PA2 corresponds to the first end of the scan line SL and is adjacent to the display area DA.

The third peripheral area PA3 corresponds to the second end of the scan line SL and is adjacent to the display area DA.

The fourth peripheral area PA4 corresponds to the second end of the data line DL and is adjacent to the display area DA.

The cutout region CA is arranged between the first peripheral region PA1 and the conduction check region TSA. After the conduction check process and before the module process, the cut-off area CA is cut along the cutting line CL set by the laser cutting process.

The conduction check region TSA may include: a conduction pad unit TPD having an inspection pad arranged thereon, to which an inspection signal for performing a conduction inspection process is applied; and a conduction check circuit TSC electrically connected to the conduction pad unit TPD. The inspection pad may be electrically connected to a signal pad of the signal pad unit SPD. The conduction check circuit TSC may be electrically connected to the data lines DL and the scan lines SL arranged in the display region DA.

The inspection control signal and the inspection data signal supplied from the conduction pad unit TPD may be applied to the data lines DL and the scan lines SL to turn on the pixels PX, so that the conduction inspection process may be performed.

In an embodiment of the inventive concept, the pass pad units TPD may be arranged in a laterally symmetrical structure with respect to the display area DA. For example, the pass pad unit TPD may include a first check pad unit TPD1 corresponding to the second peripheral region PA2 and a second check pad unit TPD2 corresponding to the third peripheral region PA 3.

Referring to fig. 3, the conduction check apparatus 200 may include a check control unit 201 and a check signal output unit 202.

The inspection control unit 201 may generate a plurality of inspection signals corresponding to the inspection mode. For example, the check signals may include the first power supply voltage ELVDD, the second power supply voltage ELVSS, the voltage of the initialization power supply VINT, and a plurality of check data signals DCR, DCG, and DCB.

The inspection signal output unit 202 may be electrically connected to the conductive pad unit TPD of the display unit 100, and may supply an inspection signal to the conductive pad unit TPD.

Referring back to fig. 1, in an embodiment of the inventive concept, the first power supply voltage line VL1 may include a first voltage line L11, a second voltage line L12, and a third voltage line L13.

The first voltage line L11 is electrically connected to the first check pad cell TPD1, and extends from the conduction check region TSA to the signal pad region SPA of the first peripheral region PA1 via the cut-off region CA along the first direction DR 1.

The second voltage line L12 is electrically connected to the second check pad cell TPD2, and extends from the conduction check region TSA to the signal pad region SPA of the first peripheral region PA1 via the cut-off region CA along the first direction DR 1.

The third voltage line L13 extends in the second direction DR2 from the fan-out region FOA of the first peripheral region PA1, and is electrically connected to the first voltage line L11 and the second voltage line L12.

In an embodiment of the inventive concept, the second power supply voltage line VL2 may include a first voltage line L21, a second voltage line L22, and a third voltage line L23.

The first voltage line L21 is electrically connected to the first check pad cell TPD1, extends from the conduction check region TSA to the signal pad region SPA and the fan-out region FOA of the first peripheral region PA1 via the cutout region CA along the first direction DR1, and continuously extends along the first direction DR1 in the second peripheral region PA 2.

The second voltage line L22 is electrically connected to the second check pad cell TPD2, extends from the conduction check region TSA to the signal pad region SPA and the fan-out region FOA of the first peripheral region PA1 via the cut-out region CA along the first direction DR1, and continuously extends along the first direction DR1 in the third peripheral region PA 3.

The third voltage line L23 extends in the second direction DR2 in the fourth peripheral region PA4, and is electrically connected to the first voltage line L21 and the second voltage line L22.

In an embodiment of the inventive concept, in the cut-off area CA, at least one of the first and second power voltage lines VL1 and VL2 may be branched or divided into a plurality of sub-lines by at least one slit pattern. The at least one slit pattern may have a length corresponding to a direction intersecting the extending direction of the cutting line CL, and may have a width corresponding to the extending direction of the cutting line CL. The sub-lines may be arranged in the extending direction of the cutting line CL.

The total maximum current capacity for driving the organic light emitting diodes OLED included in the pixels PX is a level of several tens of amperes, and as the size of the organic light emitting display increases, the current capacity with respect to the power supply voltage may increase. Accordingly, the widths of the first and second supply voltage lines VL1 and VL2 may be increased. When the width of the metal line is increased, defects such as cracks may occur in the display cell during the laser cutting process due to incomplete laser processing.

According to an embodiment of the inventive concept, in order to prevent defects such as cracks that may occur in a cutting process, in the cut-off area CA, at least one of the first and second power voltage lines VL1 and VL2 may be divided into a plurality of sub-lines by at least one slit pattern. The width of the slit pattern may be set in consideration of the pitch of the laser spots.

Fig. 4 is an enlarged view of a portion 'a' of fig. 1 to illustrate a structure of a power supply voltage line according to an embodiment of the inventive concept. Fig. 5 is an enlarged view of a portion 'B' of fig. 4 for explaining a slit pattern and sub-lines in a cut-away area according to an embodiment of the inventive concept.

Referring to fig. 4 and 5, the first power supply voltage line VL1 may transmit the first power supply voltage ELVDD, and the second power supply voltage line VL2 may transmit the second power supply voltage ELVSS.

At least one of the first and second power voltage lines VL1 and VL2 may include at least one slit pattern SP in the cut-off area CA.

As shown in the figure, the first power supply voltage line VL1 has a first width W1 in the conduction check region TSA and the first peripheral region PA1, and includes a slit pattern SP in the cut-off region CA between the conduction check region TSA and the first peripheral region PA 1. In the cut-off region CA, the first power voltage line VL1 may be divided into a first sub-line VL _ S1 and a second sub-line VL _ S2 by the slit pattern SP. Each of the first and second sub-lines VL _ S1 and VL _ S2 may have a second width W2 less than the first width W1.

In addition, the second power supply voltage line VL2 may have a first width W1 in the conduction check region TSA and the first peripheral region PA1, and may include a slit pattern SP in the cut-off region CA between the conduction check region TSA and the first peripheral region PA 1. In the cut-off area CA, the second power voltage line VL2 may be divided into a first sub-line VL _ S1 and a second sub-line VL _ S2 by the slit pattern SP. Each of the first and second sub-lines VL _ S1 and VL _ S2 may have a second width W2 less than the first width W1.

In an embodiment of the inventive concept, the width SW of the slit pattern SP may be set to be greater than or equal to the pitch LP of the laser spots used in the laser cutting process (SW ≧ LP).

In an embodiment of the inventive concept, the second width W2 (which may also be referred to as a line width) of each of the first and second sub-lines VL _ S1 and VL _ S2 may be set to be greater than or equal to the pitch LP of the laser spots (W2 ≧ LP).

Referring to fig. 1, 4 and 6, the display unit 100 may include a pixel area PXA in which pixels PX are formed and a cut-out area CA cut by a laser cutting process.

The display unit 100 may include a substrate 110, and the substrate 110 may include a pixel area PXA and a cut-out area CA.

The substrate 110 may be a transparent or opaque insulating substrate. For example, the substrate 110 may include glass or plastic, such as Polyimide (PI), Polycarbonate (PC), Polyethersulfone (PES), polyethylene terephthalate (PET), or polyacrylate.

Referring to the pixel area PXA of the display cell 100, a buffer layer 115 may be disposed on the substrate 110 or over the substrate 110. The buffer layer 115 may block impurities such as oxygen and moisture from penetrating through the substrate 110. In addition, the buffer layer 115 may provide a flat surface on top of the substrate 110. The buffer layer 115 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. Alternatively, the buffer layer 115 may be omitted.

The thin film transistor TFT and the storage capacitor CST (e.g., the storage capacitor CST of fig. 2) may be disposed on the buffer layer 115 or over the buffer layer 115. The thin film transistor TFT may include a semiconductor layer 120, a gate electrode 130, a source electrode 140, and a drain electrode 150. In an embodiment of the inventive concept, the thin film transistor TFT may have a top gate structure in which the gate electrode 130 is positioned above the semiconductor layer 120. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, the thin film transistor TFT may have a bottom gate structure in which the gate electrode 130 is positioned under the semiconductor layer 120.

The semiconductor layer 120 may be disposed on the buffer layer 115 or over the buffer layer 115. The semiconductor layer 120 may be formed of amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like. The semiconductor layer 120 may include a source region, a drain region, and a channel region formed between the source region and the drain region.

The gate insulating film 125 covering the semiconductor layer 120 may be disposed on the buffer layer 115 or over the buffer layer 115. The gate insulating film 125 may isolate the gate electrode 130 from the semiconductor layer 120. The gate insulating film 125 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

The gate electrode 130 may be disposed on the gate insulating film 125 or over the gate insulating film 125. The gate electrode 130 may overlap with a channel region of the semiconductor layer 120. The gate electrode 130 may be formed of a first metal layer. The first metal layer may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), or an alloy thereof.

An interlayer insulating film 135 covering the gate electrode 130 may be disposed on the gate insulating film 125 or over the gate insulating film 125. The interlayer insulating film 135 may isolate the source electrode 140 and the drain electrode 150 from the gate electrode 130. The interlayer insulating film 135 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

The source electrode 140 and the drain electrode 150 may be disposed on the interlayer insulating film 135 or over the interlayer insulating film 135. The source electrode 140 and the drain electrode 150 may be electrically connected to the source region and the drain region of the semiconductor layer 120 through contact holes formed in the interlayer insulating film 135 and the gate insulating film 125, respectively. The source electrode 140 and the drain electrode 150 may be formed of a second metal layer. The second metal layer may include an aluminum alloy. The aluminum alloy may include one of copper (Cu), vanadium (V), and silicon (Si).

In an embodiment of the inventive concept, the second metal layer may include a first layer, a second layer, and a third layer sequentially stacked. For example, the first layer may be disposed below the bottom surface of the second layer, and the third layer may be disposed on or above the top surface of the second layer. The first layer, the second layer, and the third layer may have a Ti/Al/Ti laminated structure including titanium (Ti), an aluminum alloy, and titanium, respectively.

The storage capacitor CST includes the first storage electrode 133 formed of the same first metal layer as the gate electrode 130 and the second storage electrode 153 formed of the same second metal layer as the source electrode 140 and the drain electrode 150. The second storage electrode 153 overlaps the first storage electrode 133, wherein the storage capacitor CST may be defined in an overlapping region between the first storage electrode 133 and the second storage electrode 153.

The planarization layer 175 may be disposed on the interlayer insulating film 135 or over the interlayer insulating film 135 to have a large thickness for covering the source electrode 140, the drain electrode 150, and the second storage electrode 153. The planarization layer 175 may include an organic material such as acrylic resin, epoxy resin, polyimide resin, or polyester resin.

The first electrode 180 may be disposed on the planarization layer 175 or disposed over the planarization layer 175. The first electrode 180 may be electrically connected to the drain electrode 150 of the thin film transistor TFT through a contact hole formed in the planarization layer 175. The first electrode 180 may include Indium Tin Oxide (ITO), silver, and ITO.

The pixel defining layer 190 covering the first electrode 180 may be disposed on the planarization layer 175 or disposed over the planarization layer 175. The pixel defining layer 190 may include an opening exposing the top surface of the first electrode 180 and defines a light emitting region. The pixel defining layer 190 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, or a polyester resin.

The organic light emitting layer 210 may be disposed in an opening exposing the top surface of the first electrode 180. The organic light emitting layer 210 may include a low molecular organic compound or a high molecular organic compound. In embodiments of the inventive concept, the organic light emitting layer 210 may emit red, green, or blue light. In embodiments of the inventive concept, when the organic light emitting layer 210 emits white light, the organic light emitting layer 210 may include a multi-layer structure including a red light emitting layer, a green light emitting layer, and a blue light emitting layer, or may include a single-layer structure including a red light emitting material, a green light emitting material, and a blue light emitting material.

The second electrode 230 may be disposed on the organic light emitting layer 210 or over the organic light emitting layer 210. For example, the second electrode 230 may be disposed on the organic light emitting layer 210 and the pixel defining layer 190 or above the organic light emitting layer 210 and the pixel defining layer 190. The second electrode 230 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof.

Referring to the cut-out area CA of the display unit 100, the buffer layer 115 may be disposed on the substrate 110 or over the substrate 110.

The gate insulating film 125 may be disposed on the buffer layer 115 or over the buffer layer 115. The first and second power supply voltage lines VL1 and VL2 formed of the first metal layer may be disposed on the gate insulating film 125 or over the gate insulating film 125.

In the cut-off region CA, the first power voltage line VL1 may include at least one slit pattern SP, and include a plurality of sub-lines VL _ S1 and VL _ S2. In addition, the second power voltage line VL2 may include at least one slit pattern SP, and include a plurality of sub-lines VL _ S1 and VL _ S2. At least one slit pattern SP and sub-lines VL _ S1 and VL _ S2 may be formed in a process of patterning the first metal layer.

In the cut-off region CA, the interlayer insulating film 135 exposes the sub-lines VL _ S1 and VL _ S2 of the first power supply voltage line VL1 and at least one slit pattern SP. The interlayer insulating film 135 may be formed of an inorganic material. The interlayer insulating film 135 formed over the sub-lines VL _ S1 and VL _ S2 and the at least one slit pattern SP may be removed in a subsequent process for forming a gate pad or a process for forming a gate pad. However, the inventive concept is not limited thereto, and the interlayer insulating film 135 formed on the sub-lines VL _ S1 and VL _ S2 and the at least one slit pattern SP or formed over the sub-lines VL _ S1 and VL _ S2 and the at least one slit pattern SP may be removed through various subsequent etching processes.

In addition, in the cut-off region CA, the planarization layer 175 exposes the sub-lines VL _ S1 and VL _ S2 of the first power voltage line VL1 and at least one slit pattern SP. The planarization layer 175 may be formed of an organic material. The planarization layer 175 formed over the sub-lines VL _ S1 and VL _ S2 and the at least one slit pattern SP may be removed in a process of forming a via hole (e.g., a contact hole in which the first electrode 180 of the pixel area PXA contacts the drain electrode 150). However, the inventive concept is not limited thereto, and the planarization layer 175 formed on or over the sub-lines VL _ S1 and VL _ S2 and the at least one slit pattern SP may be removed through various subsequent etching processes.

The sub-lines VL _ S1 and VL _ S2 corresponding to the first power voltage line VL1 of the cut-off region CA and the at least one slit pattern SP may be exposed to the outside in the laser cutting process.

In addition, the interlayer insulating film 135 and the planarization layer 175 may expose the sub-lines VL _ S1 and VL _ S2 of the second power voltage line VL2 and at least one slit pattern SP.

The sub-lines VL _ S1 and VL _ S2 corresponding to the second power voltage line VL2 of the cut-off region CA and the at least one slit pattern SP may be exposed to the outside in the laser cutting process.

The sub-lines VL _ S1 and VL _ S2 and the slit pattern SP are exposed in the laser cutting process, so that malfunctions and defects such as cracks due to lack of laser processing can be prevented.

In addition, the power supply voltage line of the cut-off area CA is formed to include the sub-lines VL _ S1 and VL _ S2 of at least one slit pattern SP, so that malfunctions and defects such as cracks due to incomplete laser processing may be prevented during the laser cutting process.

In the embodiments of the inventive concept, although the first and second power supply voltage lines VL1 and VL2 are illustrated as being formed of the first metal layer in the cut-off area CA, it is not limited thereto, and the first and second power supply voltage lines VL1 and VL2 may be formed of another metal material having excellent resistivity characteristics used during a process of manufacturing a display unit.

Fig. 7 is a conceptual diagram of laser processing performed on a cut-out area CA in which a metal line ML having a thick width W _ C is disposed according to a comparative example. Fig. 8 is a conceptual diagram of laser processing performed on a plurality of metal sub-lines ML _ S including a plurality of slit patterns SP according to an embodiment of the inventive concept.

Referring to fig. 7, when a metal line ML having a width greater than the pitch LP of a plurality of laser spots is disposed in a cut-off area CA according to a comparative example, the laser spots cannot penetrate to the substrate of the display unit due to the metal line and are reflected by the metal line during the laser cutting process, and thus defects such as cracks may occur in the display unit.

Referring to fig. 8, when the cut-off region CA according to an embodiment of the inventive concept includes at least one slit pattern SP having a width greater than or equal to the pitch LP of the laser spots, and the metal sub-lines ML _ S having a width W _ E greater than or equal to the pitch LP of the laser spots are provided, the laser may easily penetrate to the substrate of the display unit through the slit pattern SP during the laser cutting process, and the laser is prevented from being reflected on the metal sub-lines ML _ S, so that defects such as cracks may be prevented.

In an embodiment of the inventive concept, referring to fig. 9A, the power supply voltage line VL _ E1 may be formed of the same metal layer as that located in the cut-out region CA and adjacent regions TSA and PA1 adjacent to the cut-out region CA (e.g., the conduction check region TSA and the first peripheral region PA 1).

The power voltage line VL _ E1 includes a plurality of sub lines in the cutout area CA, and includes a plurality of slit patterns between the sub lines.

Due to the same resistivity characteristics, the power supply voltage line VL _ E1 may have a first width W1 in the adjacent regions TSA and PA1, and may have a second width W2 in the cutout region CA that is larger than the first width W1 by the width of the slit.

In an embodiment of the inventive concept, referring to fig. 9B, the power supply voltage line VL _ E2 may be formed of a metal layer different from the cut-off region CA and adjacent regions TSA and PA1 adjacent to the cut-off region CA.

The power voltage line VL _ E2 includes a plurality of sub lines in the cutout area CA, and includes a plurality of slit patterns between the sub lines.

The power supply voltage line VL _ E2 may be formed of a metal layer having a relatively low resistivity characteristic in the adjacent regions TSA and PA1, and may be formed of a metal layer having a relatively high resistivity characteristic in the cutout region CA.

Accordingly, the power supply voltage line VL _ E2 may have a third width W3 in the adjacent regions TSA and PA1 and a fourth width W4 smaller than the third width W3 in the cutout region CA based on the resistivity characteristics.

For example, when the resistivity of the supply voltage line VL _ E2 in the adjacent regions TSA and PA1 is substantially the same as the resistivity of the supply voltage line VL _ E1 described in fig. 9A, and the supply voltage line VL _ E2 has a relatively high resistivity characteristic in the cut-off region CA, the number of sub-lines of the supply voltage line VL _ E2 may be smaller than the number of sub-lines of the supply voltage line VL _ E1 shown in fig. 9A.

As described above, the number and width of the metal sub-lines may be variously determined based on the resistivity of the metal sub-lines formed in the cut-off region.

Referring to fig. 10, the display device may include a display unit 100A and a flexible circuit board 300.

After the laser cutting process is completed for the display unit 100 shown in fig. 1, the display unit 100A has a state in which the conduction check region TSA is cut off.

Similar to the display unit 100 of fig. 1, the display unit 100A may include a display area DA and first, second, third, and fourth peripheral areas PA1, PA2, PA3, and PA4 surrounding the display area DA.

For the display unit 100A, the conduction check region TSA included in the display unit 100 of fig. 1 may be removed, and a part of the cut-out region CA may be removed.

A part of the cut-away area CA of fig. 1 may remain in the edge area EA adjacent to the first peripheral area PA1 of the display unit 100A.

In the cut-off area CA of fig. 1, the first and second power voltage lines VL1 and VL2 include a plurality of sub-lines including at least one slit pattern. Accordingly, at least one of the first and second power voltage lines VL1 and VL2 may include a plurality of sub-lines VL _ S1 and VL _ S2 in the edge area EA of the display unit 100A.

The flexible circuit board 300 may be bonded to a signal pad unit SPD having a plurality of signal pads disposed in a signal pad area SPA of the first peripheral area PA1 by using an anisotropic conductive film. The flexible circuit board 300 may have mounted thereon a driving integrated circuit 310 for driving the display unit 100A.

After the laser cutting process, the display unit 100A may be attached to the flexible circuit board 300 through a module process.

In addition, at least one polarizer, a protective film, and the like may be attached to the display unit 100A through a module process.

According to some embodiments of the inventive concept as described above, the metal line is formed to include a plurality of sub-lines separated by at least one slit pattern in the cut-out region of the display unit, so that malfunction and defect due to laser processing lacking the metal line can be prevented. In addition, the organic insulating film and the inorganic insulating film on or over the at least one slit pattern and sub-line are removed in the cut-off region to expose the at least one slit pattern and sub-line, so that malfunction and defect due to incomplete laser processing can be prevented.

The inventive concept can be applied to any electronic device including a display device. For example, the inventive concept may be applied to smart phones, tablet computers, mobile phones, Personal Computers (PCs), home appliances, laptop computers, and the like.

While the inventive concept has been shown and described with reference to certain embodiments thereof, it will be apparent to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth by the present disclosure.

Claims

1. A display device, wherein the display device comprises:

a display unit comprising: a signal line electrically connected to the pixels arranged in the display region; a signal pad unit disposed in a peripheral region adjacent to the display region and including a signal pad electrically connected to the signal line; and a power supply voltage line disposed in the peripheral region, and configured to apply a power supply voltage to the pixels and divided into a plurality of sub-lines in an edge region; and

a flexible circuit board bonded to the signal pad unit through an anisotropic conductive film, wherein a driving integrated circuit configured to drive the display unit is mounted over the flexible circuit board.

2. The display device according to claim 1, wherein the display unit further comprises an insulating film exposing the plurality of sub lines disposed in the edge region.

3. The display device according to claim 2, wherein the insulating film comprises:

an inorganic insulating film provided over a gate electrode of a transistor included in the pixel; and

an organic insulating film disposed over the source and drain electrodes of the transistor.

4. The display device according to claim 1, wherein the pixel comprises an organic light emitting diode, and

wherein the power supply voltage line includes at least one of a first power supply voltage line configured to transmit a first power supply voltage to the organic light emitting diode and a second power supply voltage line configured to transmit a second power supply voltage to the organic light emitting diode.

5. The display device according to claim 4, wherein the peripheral region includes: a first peripheral region in which the signal pad unit is disposed, a second peripheral region adjacent to the first peripheral region, a third peripheral region facing the second peripheral region, and a fourth peripheral region facing the first peripheral region,

wherein the first to fourth peripheral regions surround the display region, and

wherein the first power supply voltage line extends from the edge region and is disposed in the first peripheral region.

6. The display device according to claim 5, wherein the second power supply voltage line extends from the edge region and is provided in the second peripheral region, the third peripheral region, and the fourth peripheral region.

7. A display unit, wherein the display unit comprises:

a signal line electrically connected to the pixels arranged in the display region;

a signal pad unit disposed in a peripheral region adjacent to the display region and including a signal pad electrically connected to the signal line;

an inspection pad unit disposed in the conduction inspection region and including an inspection pad electrically connected to the signal pad, wherein the inspection pad is configured to receive a conduction inspection signal; and

a power supply voltage line configured to apply a power supply voltage to the pixel, the power supply voltage line extending from the inspection pad unit to the peripheral region, and the power supply voltage line being divided into a plurality of sub-lines by at least one slit pattern in a cut-off region between the peripheral region and the conduction inspection region.

8. The display unit of claim 7, wherein the display unit further comprises:

an insulating film exposing the at least one slit pattern and the plurality of sub-lines in the cut-out region.

9. The display unit according to claim 8, wherein the insulating film comprises:

10. A method of manufacturing a display unit, wherein the method comprises:

forming signal lines electrically connected to pixels arranged in a display region;

forming a signal pad disposed in a peripheral region adjacent to the display region and electrically connected to the signal line;

forming an inspection pad disposed in a conduction inspection region and electrically connected to the signal pad so that a conduction inspection signal is applied to the inspection pad; and

forming a power supply voltage line extending from the inspection pad to the peripheral region and divided into a plurality of sub-lines by at least one slit pattern in a cut-off region between the peripheral region and the conduction inspection region.