CN111668192A - Test structure of semiconductor device, preparation method and test method thereof - Google Patents

Test structure of semiconductor device, preparation method and test method thereof Download PDF

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CN111668192A
CN111668192A CN202010723943.2A CN202010723943A CN111668192A CN 111668192 A CN111668192 A CN 111668192A CN 202010723943 A CN202010723943 A CN 202010723943A CN 111668192 A CN111668192 A CN 111668192A
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bit line
layer
gate layer
floating gate
dielectric layer
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CN111668192B (en
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曹启鹏
付博
王卉
曹子贵
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer Hardware Design (AREA)
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  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention provides a test structure of a semiconductor device, a preparation method of the test structure and a test method of the test structure. The test structure includes: the semiconductor substrate comprises a storage unit area and a bit line structure area positioned on one side of the storage unit area; the tunneling dielectric layer covers the surface of the semiconductor substrate of the bit line structure region and extends to the partial surface of the storage unit region; the floating gate layer is positioned on the surface of the tunneling dielectric layer; and the bit line is positioned on the floating gate layer of the bit line structure area, and the bottom of the bit line structure area is electrically contacted with the floating gate layer of the bit line structure area. In the test structure, the bit line of the bit line structure area is directly connected with the floating gate layer of the storage area, so that the parasitic capacitance between the floating gate layer of the storage unit area and the substrate is equal to the parasitic capacitance between the bit line and the substrate, and the parasitic capacitance between the floating gate layer and the substrate can be obtained by measuring the parasitic capacitance between the bit line and the substrate.

Description

Test structure of semiconductor device, preparation method and test method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test structure of a semiconductor device, a preparation method and a test method thereof.
Background
At present, a Flash memory (Flash memory), also called Flash memory, has become the mainstream of a non-volatile memory, and a memory cell of the Flash memory is formed by adding a Floating Gate (FG) and a Tunnel Oxide (Tunnel Oxide) on the basis of a conventional MOS transistor structure, and storing charges by using the Floating Gate to realize non-volatility of stored contents.
The size of the parasitic capacitance is one of the key factors that determine the speed and design margin of the flash memory. However, the floating gate in each memory cell (cell) in the flash memory is completely surrounded by the silicon dioxide insulating layer (to ensure that the charges in the floating gate do not leak), and is insulated and isolated from the floating gate and electrical structures such as a substrate, a control gate, a word line, a bit line and the like. Therefore, in the prior art, the parasitic capacitance between the floating gate and the substrate, the control gate, the word line, the bit line and other electrical structures in each memory cell cannot be measured for the flash memory with the storage capability.
Therefore, in order to avoid excessive design margins and increase speed, a parasitic capacitance test of a memory cell of a flash memory is required.
Disclosure of Invention
The invention aims to provide a test structure of a semiconductor device, a preparation method and a test method thereof, and aims to solve the problem that the parasitic capacitance between the floating gate and the substrate and other electrical structures in the conventional semiconductor device cannot be measured.
In order to solve the above technical problem, the present invention provides a test structure of a semiconductor device, the test structure comprising:
the semiconductor substrate comprises a storage unit area and a bit line structure area positioned on one side of the storage unit area;
the tunneling dielectric layer covers the surface of the semiconductor substrate of the bit line structure region and extends to the partial surface of the storage unit region;
the floating gate layer is positioned on the surface of the tunneling dielectric layer;
and the bit line is positioned on the floating gate layer of the bit line structure area, and the bottom of the bit line structure area is electrically contacted with the floating gate layer of the bit line structure area.
Optionally, the memory cell region of the semiconductor substrate further has an inter-gate dielectric layer and a control gate layer; the inter-gate dielectric layer and the control gate layer are sequentially stacked on the floating gate layer of the memory unit area to form a gate stack structure.
Optionally, the test structure may be a single memory bit structure or may be a dual memory bit structure sharing a word line or may be a dual memory bit structure sharing a source line.
Optionally, the bit line structure regions are disposed on two sides of the memory cell region of the word line sharing dual memory bit structure, a bit line is formed in each bit line structure region, an opening is formed in the gate stack structure of the memory cell region, the opening penetrates through the control gate layer, the inter-gate dielectric layer, the floating gate layer and the tunneling dielectric layer, a word line is formed in the opening, and the word line is insulated and isolated from the floating gate layer, the control gate layer and the semiconductor substrate; and a first side wall is also formed on the floating gate layer between the gate stack structure and the bit line, and at least covers the side walls of the control gate layer and the inter-gate dielectric layer facing the bit line.
Optionally, a second sidewall and a gate dielectric layer are further formed in the opening, the second sidewall covers the sidewall of the opening, the gate dielectric layer covers the second sidewall and the semiconductor substrate exposed at the bottom of the opening, and the word line is insulated and isolated from the floating gate layer, the control gate layer and the semiconductor substrate through the second sidewall and the gate dielectric layer.
Based on the test structure of the semiconductor device, the invention also provides a test method of the test structure of the semiconductor device, which comprises the following steps:
and applying a first bias voltage to the bit line and applying a second bias voltage to the semiconductor substrate to measure a first parasitic capacitance between the bit line and the semiconductor substrate, wherein the first parasitic capacitance is the parasitic capacitance between the floating gate layer and the semiconductor substrate.
Optionally, the test structure may further include at least one electrical structure of a control gate layer, a word line, and a source line, and the test method may further include:
and applying a first bias voltage to the bit line and applying a corresponding bias voltage to the electric structure, and measuring a second parasitic capacitance between the bit line and the electric structure, wherein the second parasitic capacitance is the parasitic capacitance between the floating gate layer and the electric structure.
Based on the test structure of the semiconductor device, the invention also provides a preparation method of the test structure of the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell area and a bit line structure area positioned on one side of the memory cell area;
forming a grid stacking structure on the semiconductor substrate, wherein the grid stacking structure comprises a tunneling dielectric layer and a floating gate layer which are sequentially stacked, and the tunneling dielectric layer and the floating gate layer are covered on the surface of the semiconductor substrate in the bit line structure region and extend to the partial surface of the memory cell region;
and forming a bit line, wherein the bit line is positioned on the floating gate layer of the bit line structure area, and the bottom of the bit line is electrically contacted with the floating gate layer of the bit line structure area.
Optionally, the step of forming a gate stack structure on the semiconductor substrate may include:
sequentially forming a tunneling dielectric layer, a floating gate layer, an inter-gate dielectric layer, a control gate layer and a hard mask layer on the semiconductor substrate;
etching the hard mask layer, the control gate layer and the inter-gate dielectric layer to the floating gate layer to form an opening;
forming a second side wall on the side wall of the opening;
etching the floating gate layer and the tunneling dielectric layer along the opening to the surface of the semiconductor substrate to form a groove;
forming a gate dielectric layer on the inner surface in the groove and filling the word line;
etching the hard mask layer, the control gate layer and the inter-gate dielectric layer to the surface of the floating gate layer;
and forming a first side wall on the surface of the floating gate layer, wherein the first side wall covers the side wall of the hard mask layer, the side wall of the control gate layer and the side wall of the inter-gate dielectric layer.
Optionally, the step of forming the bit line may include:
forming an interlayer dielectric layer, wherein the interlayer dielectric layer buries the grid stacking structure and the bit line structure region;
etching the interlayer dielectric layer in the bit line structure region to form a contact hole exposing the surface of the floating gate layer in the bit line structure region;
and filling conductive metal in the contact hole to form the bit line.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. the invention provides a novel test structure of a semiconductor device, wherein a bit line of a bit line structure region is directly connected with a floating gate layer of a storage region, so that the parasitic capacitance between the floating gate layer of a storage cell region and a substrate is equal to the parasitic capacitance between the bit line and the substrate, and the parasitic capacitance between the floating gate layer and the substrate can be obtained by measuring the parasitic capacitance between the bit line and the substrate.
2. Similarly, in the test structure, the bit line of the bit line structure region is directly connected with the floating gate layer of the storage region, the parasitic capacitance between the floating gate layer of the storage cell region and the word line is equal to the parasitic capacitance between the bit line and the word line, the parasitic capacitance between the floating gate layer of the storage cell region and the control gate layer is equal to the parasitic capacitance between the bit line and the control gate layer, and the parasitic capacitance between the floating gate layer of the storage cell region and the source line is equal to the parasitic capacitance between the bit line and the source line, so that the parasitic capacitances between the floating gate layer and the word line, between the control gate layer and between the floating gate layer and the source line can be respectively obtained by measuring the parasitic capacitances between the bit line and the word line, between the control gate layer and between the source line.
3. Furthermore, the quality of the tunneling oxide layer of the storage unit can be monitored by measuring the breakdown voltage between the bit line of the bit line structure region and the floating gate layer of the storage region in the test structure of the semiconductor device provided by the invention, so that the yield of the semiconductor device is ensured.
Drawings
FIG. 1 is a cross-sectional schematic view of a semiconductor device test structure according to an embodiment of the present invention, which is a word line shared dual memory bit structure;
FIG. 2 is a schematic cross-sectional view of a semiconductor device test structure of a single bit structure according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating a method of fabricating a semiconductor device test structure in accordance with an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to solve the problem that the parasitic capacitance between the floating gate and the substrate and other electrical structures in the semiconductor device in the prior art cannot be measured, the invention provides a test structure of the semiconductor device, a preparation method and a test method thereof, which are respectively explained in detail below.
First, a test structure of a semiconductor device according to an embodiment of the present invention is described below, where the test structure of the semiconductor device includes:
the semiconductor substrate comprises a storage unit area and a bit line structure area positioned on one side of the storage unit area;
the tunneling dielectric layer covers the surface of the semiconductor substrate of the bit line structure region and extends to the partial surface of the storage unit region;
the floating gate layer is positioned on the surface of the tunneling dielectric layer;
and the bit line is positioned on the floating gate layer of the bit line structure area, and the bottom of the bit line structure area is electrically contacted with the floating gate layer of the bit line structure area.
That is, in the test structure, since the bit line of the bit line structure region and the floating gate layer of the storage region are directly connected, the parasitic capacitance between the floating gate layer of the memory cell region and the substrate is equal to the parasitic capacitance between the bit line and the substrate, and thus the parasitic capacitance between the floating gate layer and the substrate can be obtained by measuring the parasitic capacitance between the bit line and the substrate.
It should be noted that the semiconductor test structure provided in the embodiment of the present invention may be a dual storage bit structure sharing a word line or may be a dual storage bit structure sharing a source line, and the following description specifically describes the test structure as the dual storage bit structure sharing the word line.
Fig. 1 is a schematic cross-sectional view of a semiconductor device test structure of a word line shared dual memory bit structure according to an embodiment of the present invention. As shown in fig. 1, a test structure of a semiconductor device according to an embodiment of the present invention includes: semiconductor substrate 100, tunnel dielectric layer 110, floating gate layer 120, intergate dielectric layer 130, control gate layer 140, second sidewall 150, gate dielectric layer 160, word line 170, bit line 180, and first sidewall 190.
The semiconductor substrate 100 may include a memory cell region M, and bit line structure regions N located at two sides of the memory cell region M; the semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a glass substrate, a III-V compound substrate (e.g., a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates known to those skilled in the art, or the like. The memory cell region M of the semiconductor substrate 100 further has an inter-gate dielectric layer 130 and a control gate layer 140, the inter-gate dielectric layer 130 is made of, for example, silicon dioxide or a silicon oxide-silicon nitride-silicon oxide stack (i.e., an ONO stack), and the control gate layer 140 is made of, for example, polysilicon; the inter-gate dielectric layer 130 and the control gate layer 140 are sequentially stacked on the floating gate layer 120 of the memory cell region M to form a gate stack structure, and the floating gate layer 120 is a film layer used for data storage in the memory cell region M. The tunneling dielectric layer 110 covers the surface of the semiconductor substrate 100 in the bit line structure region N and extends to a part of the surface of the memory cell region M; the floating gate layer 120 is located on the surface of the tunneling dielectric layer 110; the bit line 180 is located on the floating gate layer 120 of the bit line structure region N, and the bottom of the bit line 180 is electrically contacted with the floating gate layer 120 of the bit line structure region N. Since the bit line 180 is directly connected to the floating gate layer 120 of the memory region M, the parasitic capacitance between the floating gate layer 120 of the memory cell region M and the semiconductor substrate 100 is equal to the parasitic capacitance between the bit line 180 and the semiconductor substrate 100.
Illustratively, the bit line structure region N is disposed on both sides of the memory cell region M of the word line sharing dual memory bit structure, such as N1 and N2 shown in FIG. 1, wherein a bit line 180 is formed in each of the bit line structure regions (N1 or N2), and an opening (not shown) is formed in the gate stack structure of the memory cell region M, the opening penetrates through the control gate layer 140, the inter-gate dielectric layer 130, the floating gate layer 120 and the tunnel dielectric layer 110, the openings are formed with word lines 170, the word lines 170 are insulated and isolated from the floating gate layer 120, the control gate layer 130 and the semiconductor substrate 100, a first sidewall spacer 190 is further formed on the floating gate layer 120 between the gate stack structure and the bit line 180, the first sidewall spacers 190 at least cover the sidewalls of the control gate layer 140 and the inter-gate dielectric layer 130 facing the bit lines 180. The first spacers 190 are used to insulate and isolate the bit lines 180 from the control gate layer 140.
Furthermore, in some other embodiments of the present invention, the structure 190 in fig. 1 may also be an erase gate.
Further, a second sidewall 150 and a gate dielectric layer 160 are formed in the opening, the sidewall 150 is made of, for example, silicon nitride, the gate dielectric layer 160 is made of, for example, silicon dioxide, the second sidewall 150 covers the sidewall of the opening, the gate dielectric layer 160 covers the sidewall 150 and the semiconductor substrate 100 exposed at the bottom of the opening, and the word line 170 is insulated and isolated from the floating gate layer 120, the control gate layer 130 and the semiconductor substrate 100 through the second sidewall 150 and the gate dielectric layer 160.
It should be noted that, when the semiconductor test structure provided in the embodiment of the present invention is a dual storage bit structure sharing a source line, an opening formed in a gate stack structure of the memory cell region is filled with the source line, and a word line is further formed on a tunneling dielectric layer between the gate stack structure and the bit line. In the test structure, a bit line of a bit line structure region is directly connected with a floating gate layer of a storage region, the parasitic capacitance between the floating gate layer and a source line of a storage unit region is equal to the parasitic capacitance between the bit line and the source line, and the parasitic capacitance between the floating gate layer and a control gate layer of the storage unit region is equal to the parasitic capacitance between the bit line and the control gate layer, so that the parasitic capacitances between the floating gate layer and the control gate layer, the source line and a semiconductor substrate can be respectively obtained by measuring the parasitic capacitances between the bit line and the control gate layer, the source line and the semiconductor substrate.
Alternatively, in some other embodiments of the present invention, the test structure of the semiconductor device may also be a single storage bit structure. As shown in fig. 2, when the test structure of the semiconductor device is also a single memory bit structure, the test structure may include: the semiconductor device comprises a semiconductor substrate 200, a tunneling dielectric layer 210, a floating gate layer 220, an intergate dielectric layer 230, a control gate layer 240, a bit line 250, a sidewall spacer 260 and a word line 270. Illustratively, the semiconductor substrate 200 may include a memory cell region M1, and bit line structure regions N3 and N4 located at both sides of the memory cell region M; the memory cell region M1 of the semiconductor substrate 200 further has an inter-gate dielectric layer 230 and a control gate layer 240, wherein a word line layer (not shown) is formed on the control layer; the inter-gate dielectric layer 230 and the control gate layer 240 are sequentially stacked on the floating gate layer 220 of the memory cell region M1 to form a gate stack structure. The tunneling medium layer 210 covers the surface of the semiconductor substrate 200 of the bit line structure regions N3 and N4 and extends to a part of the surface of the memory cell region M1; the floating gate layer 220 is located on the entire surface of the tunneling dielectric layer 210; the bit line 250 is located on the floating gate layer 220 corresponding to the bit line structure regions N3 and N4, and the bottom of the bit line 250 is electrically contacted with the floating gate layer 220 of the bit line structure regions N3 and N4. Since the bit line 250 and the floating gate layer 220 of the memory region M1 are directly connected, the parasitic capacitance between the floating gate layer 220 of the memory cell region M1 and the semiconductor substrate 200 is equal to the parasitic capacitance between the bit line 250 and the semiconductor substrate 200, so that the parasitic capacitance between the floating gate layer 220 and the substrate 100 can be obtained by measuring the parasitic capacitance between the bit line 250 and the substrate 200.
Similarly, in the test structure provided by the embodiment of the invention, no matter the test structure is a double-storage-bit structure or a single-storage-bit structure, the bit line of the bit line structure region and the floating gate layer of the storage region are directly connected, the parasitic capacitance between the floating gate layer of the storage cell region and the word line is equal to the parasitic capacitance between the bit line and the word line, the parasitic capacitance between the floating gate layer of the storage cell region and the control gate layer is equal to the parasitic capacitance between the bit line and the control gate layer, and the parasitic capacitance between the floating gate layer of the storage cell region and the source line is equal to the parasitic capacitance between the bit line and the source line.
In addition, the quality of the tunneling oxide layer of the storage unit can be monitored by measuring the breakdown voltage between the bit line of the bit line structure region and the floating gate layer of the storage region in the test structure of the semiconductor device provided by the invention, so that the yield of the semiconductor device is ensured.
Based on the above test structure of the semiconductor device, an embodiment of the present invention further provides a test method for a test structure of a semiconductor device, which is described in detail below by taking the test structure of the semiconductor device shown in fig. 1 as an example, and the test method for a test structure of a semiconductor device includes the following steps:
applying a first bias voltage to the bit line 180 and applying a second bias voltage to the semiconductor substrate 100, and measuring a first parasitic capacitance between the bit line 180 and the semiconductor substrate 100, where the first parasitic capacitance is a parasitic capacitance between the floating gate layer 120 and the semiconductor substrate 100. Wherein the test structure may further include at least one of an electrical structure of the control gate layer 130, the word line (source line) 170 and the erase gate 190.
In this embodiment, a first bias voltage may be applied to the bit line 180 of the test structure, and a corresponding bias voltage may be applied to the electrical structures (the control gate layer 130, the word line 170 (source line), and the erase gate 190) of the test structure, so as to measure a second parasitic capacitance between the bit line 180 and the electrical structures, and since the bit line 180 of the bit line structure region N and the floating gate layer 120 of the storage region M in the test structure are directly connected, a parasitic capacitance between the floating gate layer 120 of the storage cell region M and the substrate 100 is equal to a parasitic capacitance between the bit line 180 and the substrate 100, that is, the second parasitic capacitance is a parasitic capacitance between the floating gate layer 120 and the electrical structures.
For example, a first parasitic capacitance between the semiconductor substrate 100 and the bit line 180 may be measured by electrically connecting a metal plug (not shown) connected to the bit line 180 to a ground terminal of a predetermined LCR tester, and electrically connecting a metal plug (not shown) connected to the semiconductor substrate 100 to a voltage input terminal of the LCR tester while applying the second bias voltage thereto.
It can be understood that, in the embodiment of the present invention, the quality of the tunnel oxide layer 110 of the memory cell can be monitored by measuring the breakdown voltage between the bit line 180 of the bit line structure region N and the floating gate layer 120 of the memory region M in the test structure of the semiconductor device provided by the present invention, so as to ensure the yield of the semiconductor device.
Based on the above test structure of the semiconductor device, the embodiment of the present invention further provides a method for manufacturing a test structure of a semiconductor device, which is described in detail below with reference to fig. 3 and taking the test structure of the semiconductor device shown in fig. 1 as an example, and the method for manufacturing a test structure of a semiconductor device of the present invention includes the following steps:
step S100, providing a semiconductor substrate 100, where the semiconductor substrate 100 includes a memory cell region M and a bit line structure region N located at one side of the memory cell region M.
Step S200, forming a gate stack structure on the semiconductor substrate 100, where the gate stack structure includes a tunneling dielectric layer 110 and a floating gate layer 120 stacked in sequence, and both the tunneling dielectric layer 110 and the floating gate layer 120 cover the surface of the semiconductor substrate 100 in the bit line structure region N and extend to a part of the surface of the memory cell region M.
Step S300, forming a bit line 180, where the bit line 180 is located on the floating gate layer 120 of the bit line structure region N, and the bottom of the bit line 180 is electrically contacted with the floating gate layer 120 of the bit line structure region.
It should be further noted that the step of forming a gate stack structure on the semiconductor substrate 100 in step S200 may include:
step S201, sequentially forming a tunneling dielectric layer 110, a floating gate layer 120, an inter-gate dielectric layer 130, a control gate layer 140, and a hard mask layer (not shown) on the semiconductor substrate 100;
step S202, etching the hard mask layer, the control gate layer 130 and the inter-gate dielectric layer 120 to the floating gate layer 120 to form an opening, and further forming a second side wall 150 on the side wall of the opening;
step 203, etching the floating gate layer 120 and the tunneling dielectric layer 110 to the surface of the semiconductor substrate 100 along the opening to form a trench;
step S204, forming a gate dielectric layer 160 on the inner surface in the groove and filling the word line 170;
step S205, etching the hard mask layer, the control gate layer 140 and the inter-gate dielectric layer 130 which are next to the bit line structure region N to the surface of the floating gate layer 120;
step S206, forming a first sidewall (erase gate) 190 on the surface of the floating gate layer 120, where the first sidewall (erase gate) 190 covers the sidewall of the hard mask layer, the sidewall of the control gate layer 140, and the sidewall of the inter-gate dielectric layer 130.
Optionally, the step of forming the bit line 180 includes:
forming an interlayer dielectric layer (not shown) which buries the gate stack structure and the bit line structure region N therein;
etching the interlayer dielectric layer in the bit line structure region N to form a contact hole (not shown) exposing the surface of the floating gate layer 120 in the bit line structure region;
the contact hole is filled with a conductive metal to form the bit line 180.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (10)

1. A test structure for a semiconductor device, the test structure comprising:
the semiconductor substrate comprises a storage unit area and a bit line structure area positioned on one side of the storage unit area;
the tunneling dielectric layer covers the surface of the semiconductor substrate of the bit line structure region and extends to the partial surface of the storage unit region;
the floating gate layer is positioned on the surface of the tunneling dielectric layer;
and the bit line is positioned on the floating gate layer of the bit line structure area, and the bottom of the bit line structure area is electrically contacted with the floating gate layer of the bit line structure area.
2. The test structure of a semiconductor device according to claim 1, wherein the memory cell region of the semiconductor substrate further has an intergate dielectric layer and a control gate layer; the inter-gate dielectric layer and the control gate layer are sequentially stacked on the floating gate layer of the memory unit area to form a gate stack structure.
3. The test structure of a semiconductor device of claim 2, wherein the test structure is a single memory bit structure or a dual memory bit structure sharing a word line or a dual memory bit structure sharing a source line.
4. The test structure of a semiconductor device according to claim 3, wherein the bit line structure regions are disposed on two sides of the memory cell region of the word line sharing dual memory bit structure, a bit line is formed in each bit line structure region, an opening is formed in the gate stack structure of the memory cell region, the opening penetrates through the control gate layer, the inter-gate dielectric layer, the floating gate layer and the tunneling dielectric layer, a word line is formed in the opening, and the word line is insulated and isolated from the floating gate layer, the control gate layer and the semiconductor substrate; and a first side wall is also formed on the floating gate layer between the gate stack structure and the bit line, and at least covers the side walls of the control gate layer and the inter-gate dielectric layer facing the bit line.
5. The test structure of a semiconductor device according to claim 4, wherein a second sidewall and a gate dielectric layer are further formed in the opening, the second sidewall covers the sidewall of the opening, the gate dielectric layer covers the second sidewall and the semiconductor substrate exposed at the bottom of the opening, and the word line is insulated and isolated from the floating gate layer, the control gate layer and the semiconductor substrate through the second sidewall and the gate dielectric layer.
6. A method for testing a test structure of a semiconductor device according to any of claims 1 to 5, the method comprising:
and applying a first bias voltage to the bit line and applying a second bias voltage to the semiconductor substrate to measure a first parasitic capacitance between the bit line and the semiconductor substrate, wherein the first parasitic capacitance is the parasitic capacitance between the floating gate layer and the semiconductor substrate.
7. The method of testing of claim 6, wherein the test structure further comprises at least one electrical structure of a control gate layer, a word line, and a source line, the method further comprising:
and applying a first bias voltage to the bit line and applying a corresponding bias voltage to the electric structure, and measuring a second parasitic capacitance between the bit line and the electric structure, wherein the second parasitic capacitance is the parasitic capacitance between the floating gate layer and the electric structure.
8. A method of fabricating the semiconductor device test structure of any of claims 1-5, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a memory cell area and a bit line structure area positioned on one side of the memory cell area;
forming a grid stacking structure on the semiconductor substrate, wherein the grid stacking structure comprises a tunneling dielectric layer and a floating gate layer which are sequentially stacked, and the tunneling dielectric layer and the floating gate layer are covered on the surface of the semiconductor substrate in the bit line structure region and extend to the partial surface of the memory cell region;
and forming a bit line, wherein the bit line is positioned on the floating gate layer of the bit line structure area, and the bottom of the bit line is electrically contacted with the floating gate layer of the bit line structure area.
9. The method of claim 8, wherein forming a gate stack structure on the semiconductor substrate comprises:
sequentially forming a tunneling dielectric layer, a floating gate layer, an inter-gate dielectric layer, a control gate layer and a hard mask layer on the semiconductor substrate;
etching the hard mask layer, the control gate layer and the inter-gate dielectric layer to the floating gate layer to form an opening;
forming a second side wall on the side wall of the opening;
etching the floating gate layer and the tunneling dielectric layer along the opening to the surface of the semiconductor substrate to form a groove;
forming a gate dielectric layer on the inner surface in the groove and filling the word line;
etching the hard mask layer, the control gate layer and the inter-gate dielectric layer to the surface of the floating gate layer;
and forming a first side wall on the surface of the floating gate layer, wherein the first side wall covers the side wall of the hard mask layer, the side wall of the control gate layer and the side wall of the inter-gate dielectric layer.
10. The method of manufacturing of claim 8, wherein the step of forming the bit line comprises:
forming an interlayer dielectric layer, wherein the interlayer dielectric layer buries the grid stacking structure and the bit line structure region;
etching the interlayer dielectric layer in the bit line structure region to form a contact hole exposing the surface of the floating gate layer in the bit line structure region;
and filling conductive metal in the contact hole to form the bit line.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112881882A (en) * 2021-01-08 2021-06-01 苏州苏纳光电有限公司 Method and device for testing parasitic capacitance of semiconductor chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050141281A1 (en) * 2003-12-31 2005-06-30 Dongbuanam Semiconductor Inc. Flash memory device and programming and erasing methods therewith
CN104465664A (en) * 2014-12-30 2015-03-25 上海华虹宏力半导体制造有限公司 Split-gate flash memory and manufacturing method thereof
CN105990357A (en) * 2015-02-03 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method, test structure of semiconductor device and method
CN108695332A (en) * 2018-05-18 2018-10-23 上海华虹宏力半导体制造有限公司 Gate-division type flash memory and forming method thereof, control method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050141281A1 (en) * 2003-12-31 2005-06-30 Dongbuanam Semiconductor Inc. Flash memory device and programming and erasing methods therewith
CN104465664A (en) * 2014-12-30 2015-03-25 上海华虹宏力半导体制造有限公司 Split-gate flash memory and manufacturing method thereof
CN105990357A (en) * 2015-02-03 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method, test structure of semiconductor device and method
CN108695332A (en) * 2018-05-18 2018-10-23 上海华虹宏力半导体制造有限公司 Gate-division type flash memory and forming method thereof, control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112881882A (en) * 2021-01-08 2021-06-01 苏州苏纳光电有限公司 Method and device for testing parasitic capacitance of semiconductor chip
CN112881882B (en) * 2021-01-08 2023-02-07 苏州苏纳光电有限公司 Method and device for testing parasitic capacitance of semiconductor chip

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