CN111654287A - High-precision 16-bit phase quantization analog-to-digital converter - Google Patents
High-precision 16-bit phase quantization analog-to-digital converter Download PDFInfo
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- CN111654287A CN111654287A CN202010455147.5A CN202010455147A CN111654287A CN 111654287 A CN111654287 A CN 111654287A CN 202010455147 A CN202010455147 A CN 202010455147A CN 111654287 A CN111654287 A CN 111654287A
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- H03—ELECTRONIC CIRCUITRY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The invention discloses a high-precision 16-bit phase quantization analog-to-digital converter. The circuit structure comprises an input pre-amplification unit, a weighted voltage division network, a single-end to differential amplification unit, a comparator array, an LVDS output buffer module and an on-chip bias circuit which are sequentially connected in series; the on-chip biasing circuit provides bias for the input pre-amplification unit, the single-ended to differential amplification unit, the comparator array and the LVDS output buffer module. The comparator array is composed of 8 comparators and 4 redundant comparators. According to the 16-bit phase quantization ADC structure provided by the invention, by adding the redundancy comparator, the phenomenon that the amplitude of a weighted signal is influenced by different load conditions when the weighted signal enters the comparator to cause the displacement of the intersection point and further cause the distortion of a phase interval is avoided, and the performance of the 16-bit phase quantization ADC is further improved.
Description
Technical Field
The invention belongs to the technical field of circuits, and relates to a high-precision phase quantization analog-to-digital converter, in particular to a circuit structure of a 16-bit phase quantization analog-to-digital converter (ADC).
Background
Analog-to-digital converters are ubiquitous in modern electronic devices, and are not replaceable, as a bridge between connecting analog and digital signals. The digitization object of a conventional analog-to-digital converter (ADC) is amplitude information of an analog signal, and if the digitization object is changed into phase information of the analog signal, the ADC is called a phase quantization ADC.
The phase quantization ADC has the advantages that the number of comparators can be greatly reduced on the basis of an orthogonal sampling technology, the complexity of a system is reduced, meanwhile, the performance is not influenced by the amplitude change of an analog signal, and digital phase modulation can be directly realized in system application. The orthogonal sampling technology is to convert an analog input signal into two paths of orthogonal signals I/Q and then perform subsequent processing. The function to be realized by the phase quantization ADC with the precision of N bits is to obtain 2 by comparing different combinations of various weighted signals of I/Q in pairsNA plurality of equal phase intervals, each interval having a width of (2 pi/2)N) And then output them quantized. Simply to obtain 2N-1The circuit and the I/Q have the same frequency and the duty ratio is 50 percent of square waves, and the phase difference between every two of the square waves is (2 П/2)N) And (4) degree. The higher the accuracy, the better the performance of the phase quantization ADC.
Therefore, a 16bit phase ADC should perform the following functions: deriving 2 from quadrature signal I/Q15Two ways differ by 2 pi/215≈9.6×10-5Has a duty ratio of 50% and is a square wave with the same frequency as the I/Q.
FIG. 1 shows the phase quantization principle of 16 bits to obtain 215And their expressions combined two by various weighted signals of the I/Q. As can be seen from the figure, the 16bit phaseThe implementation of a bit quantized ADC requires up to 215A weighted signal.
How to easily and accurately obtain these weighted signals in the circuit becomes a bottleneck in the realization of the 16-bit phase quantization ADC from theory.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a circuit structure of a 16-bit phase quantization ADC (analog to digital converter). A method of combining partial pressure and single-end to differential pressure is adopted, all weighted signals required by 16-bit phase quantization can be simply obtained, and meanwhile, a redundant comparator is added into a comparator array, so that the performance of the whole circuit is improved.
The technical solution of the invention is as follows:
a high-precision 16-bit phase quantization analog-to-digital converter comprises an input pre-amplification unit, a weighted voltage division network, a single-ended to differential amplification unit, a comparator array, an LVDS output buffer module and an on-chip biasing circuit which are sequentially connected in series; the on-chip biasing circuit provides bias for the input pre-amplification unit, the single-ended to differential amplification unit, the comparator array and the LVDS output buffer module.
The input pre-amplifying unit is an amplifier with about 5dB gain and is used for compensating amplitude loss caused by the weighting voltage division network.
The weighting voltage division network is an I/Q signal weighting network realized by resistance voltage division, and main weighting signals 0.38I/Q and 0.92I/Q required by the 16-bit phase ADC are obtained after the I/Q signals pass through the weighting voltage division network.
The single-end-to-differential amplifying unit realizes that the weighted signals 0.38I/Q and 0.92I/Q are converted from single end to differential, and obtains all weighted signals +/-0.38I/Q and +/-0.92I/Q required by the 16-bit phase ADC.
The comparator array consists of 8 comparators and 4 redundant comparators; one signal input end of the first redundant comparator receives a weighted signal +0.92I, and the other input end of the first redundant comparator receives a weighted signal-0.92I output by the single-ended-to-differential amplification unit; one signal input end of the second redundant comparator receives a weighted signal +0.38I output by the single-ended-to-differential amplification unit, and the other signal input end of the second redundant comparator receives a weighted signal +0.92Q output by the single-ended-to-differential amplification unit; one signal input end of the third redundant comparator receives a weighted signal-0.92Q output by the single-ended to differential amplification unit, and the other signal input end of the third redundant comparator receives a weighted signal-0.38Q output by the single-ended to differential amplification unit; one signal input end of the fourth redundant comparator receives a weighted signal-0.38I output by the single-ended to differential amplification unit, and the other signal input end of the fourth redundant comparator receives a weighted signal-0.38Q output by the single-ended to differential amplification unit; a positive signal input end of the first comparator receives a weighted signal +0.92I output by the single-end-to-differential amplification unit, and a negative signal input end of the first comparator receives a weighted signal-0.92I output by the single-end-to-differential amplification unit; the positive signal input end of the second comparator receives a weighted signal +0.38Q output by the single-end-to-differential amplification unit, and the negative signal input end of the second comparator receives a weighted signal-0.92I output by the single-end-to-differential amplification unit; the positive signal input end of the third comparator receives a weighted signal +0.38Q output by the single-end-to-differential amplification unit, and the negative signal input end of the third comparator receives a weighted signal-0.38I output by the single-end-to-differential amplification unit; a positive signal input end of the fourth comparator receives a weighted signal +0.38I output by the single-end-to-differential amplification unit, and a negative signal input end of the fourth comparator receives a weighted signal-0.92Q output by the single-end-to-differential amplification unit; a positive signal input end of the fifth comparator receives a weighted signal +0.92Q output by the single-end-to-differential amplification unit, and a negative signal input end of the fifth comparator receives a weighted signal-0.92Q output by the single-end-to-differential amplification unit; a positive signal input end of the sixth comparator receives a weighted signal +0.92Q output by the single-end-to-differential amplification unit, and a negative signal input end of the sixth comparator receives a weighted signal +0.38I output by the single-end-to-differential amplification unit; a positive signal input end of the seventh comparator receives a weighted signal-0.38I output by the single-end-to-differential amplification unit, and a negative signal input end of the seventh comparator receives a weighted signal-0.38Q output by the single-end-to-differential amplification unit; the positive signal input end of the eighth comparator receives the weighted signal +0.38Q output by the single-end-to-differential amplifying unit, and the negative signal input end of the eighth comparator is connected with the weighted signal +0.92I output by the single-end-to-differential amplifying unit.
The conventional successive approximation type AD is configured by a comparator and a DA converter through successive approximation logic, compares an input voltage with a built-in DA converter output for each bit sequentially from the MSB, and outputs a digital value through n times of comparisons. The price is cheap at low resolution (<12 bits), but very high at high precision (>12 bits). The product adopts a 16bit phase quantization comparison array and a redundancy comparison device, improves the A/D conversion precision, and greatly reduces the scale of an integrated circuit so as to greatly reduce the cost during high-precision analog-to-digital conversion. The comparison array containing the redundancy structure adopts a parallel model that more than two units work in parallel. During work, the units at all positions carry out average burden work, and the improvement of the overall work error of the circuit caused by self heating due to continuous work of a single component is effectively avoided.
The LVDS output buffer module is composed of 12 LVDS output buffer units, each LVDS output buffer unit receives the output of one comparator or redundant comparator and serves as an LVDS digital interface for continuously shaping the square wave output by the comparator and outputting the square wave meeting the LVDS standard, and therefore digital transmission and processing in the future are facilitated.
The input pre-amplifying unit, the single-end to differential amplifying unit, the comparator, the redundancy comparator and the LVDS output buffer unit all adopt the existing conventional amplifier structure.
The invention has the following beneficial effects:
1) the 16-bit phase quantization ADC structure provided by the invention simply obtains all I/Q weighted signals required by realizing the 16-bit phase quantization ADC function by a method of combining partial pressure and single-end to differential pressure, so that the 16-bit phase quantization ADC can be realized. Along with the improvement of the digital-to-analog conversion precision, the performance of the phase quantization ADC (analog-to-digital converter) including the performance of an application system where the phase quantization ADC is arranged is inevitably and obviously improved
2) According to the 16-bit phase quantization ADC structure provided by the invention, by adding the redundancy comparator, the phenomenon that the amplitude of a weighted signal is influenced by different load conditions when the weighted signal enters the comparator to cause the displacement of the intersection point, so that the phase interval is distorted is avoided, and the performance of the 16-bit phase quantization ADC is further improved;
3) the 16-bit phase quantization ADC structure provided by the invention has an LVDS digital interface, and is convenient for subsequent digital processing.
Drawings
FIG. 1 shows the phase quantization principle of 16 bits to obtain 215The first 8 of the square waves, where 1-16 represent the phase interval, V1-V8 are square waves.
Fig. 2 is a circuit configuration system block diagram of the present invention.
Fig. 3 is a basic differential amplifier circuit diagram.
Fig. 4 is a circuit schematic of a weighted voltage divider network.
FIG. 5 is a schematic diagram of a method for connecting a weighted signal to a comparator array.
Fig. 6 is a schematic diagram of phase interval distortion caused by different signal loads.
Fig. 7 is a pre-amplifying unit circuit.
Description of the preferred embodiments
The invention is further analyzed with reference to the following detailed drawings.
According to the invention, all weighted signals required by the 16-bit phase quantization ADC are obtained by adopting a simple resistance voltage division and single-end to differential conversion method, so that the whole circuit is convenient to realize; and the circuit performance is further improved by adding a redundant comparator.
As shown in fig. 2, the circuit structure system of the 16-bit phase quantization ADC is formed by sequentially connecting an input pre-amplification unit, a weighted voltage division network, a single-ended to differential amplification unit, a comparator array, and an LVDS output buffer module in series, and further includes an on-chip bias circuit for providing bias for other circuit components except the weighted voltage division network. The input end of the input pre-amplification unit receives the I/Q signal, and the output end of the input pre-amplification unit is in signal connection with the input end of the weighting voltage division network; the output end of the weighted voltage division network is in signal connection with the input end of the single-end differential conversion amplifying unit; the output end of the single-end-to-differential amplification unit is in signal connection with the input end of the comparator array; the output end of the comparator array is in signal connection with the input end of the LVDS output buffer module;
the input pre-amplifying unit is an amplifier with about 5dB gain and is used for compensating amplitude loss caused by the weighting voltage division network.
The weighting voltage division network is an I/Q signal weighting network realized by voltage division of resistors R3 and R4, and main weighting signals 0.38I/Q and 0.92I/Q required by the realization of the 16-bit phase ADC are obtained after the I/Q signals pass through the weighting voltage division network. The circuit specifically comprises resistors R2-R6 and an amplifier A3;
fig. 4 is a circuit diagram of a weighted voltage divider network, which specifically includes an amplifier a3, and five resistors R2, R3, R4, R5, and R6; an output port of the amplifier A3 is connected with one end of a resistor R3 and an A/D converter interface, a negative electrode port is connected with one end of a resistor R2 and the other end of a resistor R3, and a positive electrode port is connected with one end of a resistor R4, one end of a resistor R5 and one end of a resistor R6; the other end of the resistor R2 is grounded, and the other end of the resistor R4 is connected with an output signal U of the input pre-amplifying unit1The other end of the resistor R5 is connected with a reference voltage input interface Uref1The other end of the resistor R6 is grounded,
a reference voltage input interface Uref1And an in-phase addition circuit composed of A/D converter interface for realizing input signal U1、Uref1Are applied to amplifier a 3. Wherein R4, R5 and R6 are DC balance resistors, and in order to improve the common mode rejection ratio of the circuit and reduce the zero drift, the resistors are required to be balanced, namely: r4// R5// R6 is R2// R3. According to the principle of the addition circuit, the voltage at the output terminal of the amplifier A3 is
Wherein V1Represents U1Voltage value of Vref1Represents Uref1Voltage value of (d);
the single-end-to-differential amplifying unit realizes that the weighted signals are converted from single end to differential, and obtains all weighted signals +/-0.38I/Q and +/-0.92I/Q required by the 16-bit phase ADC.
The comparator array is used for combining the 8 weighted signals in pairs according to the 16bit phase ADC principle and then comparing the voltage to obtain 215Difference between two ways
And square waves with the same frequency as the I/Q.
The comparator array has a redundant part, which ensures that the load conditions of all weighted signals are consistent.
The LVDS output buffer is used for continuously shaping the square wave and outputting the square wave meeting the LVDS standard, so that the digital transmission and processing are facilitated.
The on-chip bias circuit is used for providing bias for other circuit components except the weighted voltage division network.
The input pre-amplifying unit, the single-end to differential amplifying unit, the comparator array and the LVDS output buffer are all realized by adopting a basic differential amplifier structure. Referring to fig. 3, the differential amplifier circuit includes a resistor R7, a resistor R8, an NMOS transistor M1, an NMOS transistor M2, and an NMOS transistor M3, wherein one end of the resistor R7 is connected to one end of the resistor R8, the other end of the resistor R7 is connected to the collector of the NMOS transistor M1, the other end of the resistor R8 is connected to the collector of the NMOS transistor M2, and the emitters of the NMOS transistor M1 and the NMOS transistor M2 are connected to the collector of the NMOS transistor M3.
Referring to fig. 5, the comparator array includes a redundant comparator a, a redundant comparator B, a redundant comparator C, a redundant comparator D, a comparator a, a comparator B, a comparator C, a comparator D, a comparator E, a comparator F, a comparator G, and a comparator H, wherein:
one signal input end of the redundancy comparator A is connected with a weighted signal +0.92I, and the other input end of the redundancy comparator A is connected with a weighted signal-0.92I;
one signal input end of the redundant comparator B is connected with a weighted signal +0.38I, and the other signal input end of the redundant comparator B is connected with a weighted signal + 0.92Q;
one signal input end of the redundancy comparator C is connected with a weighted signal-0.92Q, and the other signal input end of the redundancy comparator C is connected with a weighted signal-0.38Q;
one signal input end of the D redundant comparator is connected with a weighted signal-0.38I, and the other signal input end of the D redundant comparator is connected with a weighted signal-0.38Q;
the positive signal input end of the comparator A is connected with a weighted signal plus 0.92I, and the negative signal input end of the comparator A is connected with a weighted signal minus 0.92I;
the positive signal input end of the comparator B is connected with a weighted signal +0.38Q, and the negative signal input end of the comparator B is connected with a weighted signal-0.92I;
the positive signal input end of the comparator C is connected with a weighted signal +0.38Q, and the negative signal input end of the comparator C is connected with a weighted signal-0.38I;
the positive signal input end of the D comparator is connected with a weighted signal +0.38I, and the negative signal input end of the D comparator is connected with a weighted signal-0.92Q;
the positive signal input end of the comparator E is connected with a weighted signal +0.92Q, and the negative signal input end of the comparator E is connected with a weighted signal-0.92Q;
the positive signal input end of the F comparator is connected with a weighted signal +0.92Q, and the negative signal input end of the F comparator is connected with a weighted signal + 0.38I;
the positive signal input end of the G comparator is connected with a weighted signal-0.38I, and the negative signal input end of the G comparator is connected with a weighted signal-0.38Q;
the positive signal input end of the H comparator is connected with a weighted signal +0.38Q, and the negative signal input end of the H comparator is connected with a weighted signal + 0.92I.
During operation, the I/Q signals first enter the respective pre-amplification units for amplification, and gain of about 5dB is obtained to compensate for amplitude loss in the subsequent weighted voltage-dividing network, which has the advantage that the ADC will obtain a lower dynamic range lower limit. The circuit structure is shown in fig. 3, and is a basic differential amplifier structure. Although a differential amplifier, a single-in single-out mode of operation is used at this stage.
The pre-amplified I/Q signals enter the respective weighted voltage-dividing networks, and the circuit structure of the pre-amplifying unit is shown in fig. 7. The working principle of Q is described as an example. The capacitors C1, C2 and C3 are used for blocking the direct current, and the two series resistors R1 and R2 divide the voltage and have the function of an attenuator; since (R1+ R2)/R1 is 0.92/0.38 and the resistance R1+ resistance R2 is 50 Ω in order to obtain a good match, the resistance R1 is approximately equal to 29.3 Ω and the resistance R2 is approximately equal to 20.7 Ω; the resistors R3-R6 are used to provide DC operating points for the subsequent stages, typically in the order of K Ω. The I/Q respectively obtains 0.92I/Q and 0.38I/Q after passing through the respective weighted voltage division networks.
The four paths of signals respectively enter a single-end to differential amplification unit which is formed by cascading two basic differential amplifiers. In order to obtain a higher upper limit of the dynamic range, the gain cannot be too large, otherwise a large signal enters the amplitude limiting region in advance, so that the intersection point shifts when entering the comparator. After single-ended to differential amplification unit, fig. 1 shows a square wave diagram of all weighted signals required to achieve 8 phase quantities for a 16-bit phase quantization ADC.
The comparator is also formed by cascading a plurality of stages of basic differential amplifiers (figure 3), the intersection point of two paths of input signals is used as the rising and falling edge of the signal obtained by comparison, the signal obtained by comparison is amplified by a plurality of stages and finally is output in an amplitude limiting manner, figure 5 is a schematic diagram of the connection method of the weighted signal and the comparator array, firstly, the phase difference is 2 П/215Connecting the corresponding weighted signals with comparators with completely same 8-path structures pairwise; after connection, it can be seen that +0.38Q drives 3 paths of comparators, while-0.38Q drives only 1 path of comparators, and the other 6 weighted signals drive 2 paths of comparators; at this time, the load of each weighted signal is different, which causes amplitude variation of the weighted signal, resulting in shift of the intersection point when entering the comparator, and further causing distortion of the phase section. This is illustrated below by way of example in FIG. 1 at V2, where V2 is derived from a comparison of 0.38Q and-0.92I, as shown in FIG. 6. Since 0.38Q drives the 3-way comparator and-0.92I drives only two, the 0.38Q amplitude is necessarily compressed, as shown by the dashed sine wave. At this time, the phase difference between the square waves V2 ', V2' and V2 is delta phi and the phase difference between the square waves V1 and V3 is no longer equal to that between the square waves V1 and V3, which is obtained by comparing the square waves V2 ', V2' and V2 shown by the dotted line in FIG. 6
Respectively become (
-Δφ)、
Causing ADC phase distortion. To ensure that the loading of all weighted signals is the same, redundant comparators are added to the comparator array so that all weighted signals drive 3-way comparators, as shown in fig. 5.
The LVDS output buffer is also formed by cascading several stages of basic differential amplifiers (fig. 3) and functions to further shape the waveform output by the comparator and obtain a waveform satisfying the LVDS level interface.
The above-mentioned embodiments further explain the objects, technical solutions and advantages of the present invention in detail. It should be understood that the above-mentioned embodiments are only exemplary of the present invention, and are not intended to limit the present invention, and any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (2)
1. A high-precision 16-bit phase quantization analog-to-digital converter is characterized in that the circuit structure of the converter comprises an input pre-amplification unit, a weighted voltage division network, a single-end to differential conversion amplification unit, a comparator array, an LVDS output buffer module and an on-chip biasing circuit which are sequentially connected in series; the on-chip biasing circuit provides bias for the input pre-amplification unit, the single-end to differential amplification unit, the comparator array and the LVDS output buffer module;
the input pre-amplifying unit receives the I/Q signal and then performs gain amplification on the I/Q signal;
the weighting voltage division network receives the I/Q signals processed by the input pre-amplification unit, and main weighting signals 0.38I/Q and 0.92I/Q required by the 16-bit phase ADC are obtained through weighting voltage division processing;
the single-end-to-differential amplification unit receives the main weighting signals 0.38I/Q and 0.92I/Q processed by the weighting voltage division network, and converts the main weighting signals from single end to differential to obtain all the weighting signals +/-0.38I/Q and +/-0.92I/Q required by the 16-bit phase ADC;
the comparator array consists of 8 comparators and 4 redundant comparators; one signal input end of the first redundant comparator receives a weighted signal +0.92I output by the single-ended-to-differential amplification unit, and the other input end of the first redundant comparator receives a weighted signal-0.92I output by the single-ended-to-differential amplification unit; one signal input end of the second redundant comparator receives a weighted signal +0.38I output by the single-ended-to-differential amplification unit, and the other signal input end of the second redundant comparator receives a weighted signal +0.92Q output by the single-ended-to-differential amplification unit; one signal input end of the third redundant comparator receives a weighted signal-0.92Q output by the single-ended to differential amplification unit, and the other signal input end of the third redundant comparator receives a weighted signal-0.38Q output by the single-ended to differential amplification unit; one signal input end of the fourth redundant comparator receives a weighted signal-0.38I output by the single-ended to differential amplification unit, and the other signal input end of the fourth redundant comparator receives a weighted signal-0.38Q output by the single-ended to differential amplification unit; a positive signal input end of the first comparator receives a weighted signal +0.92I output by the single-end-to-differential amplification unit, and a negative signal input end of the first comparator receives a weighted signal-0.92I output by the single-end-to-differential amplification unit; the positive signal input end of the second comparator receives a weighted signal +0.38Q output by the single-end-to-differential amplification unit, and the negative signal input end of the second comparator receives a weighted signal-0.92I output by the single-end-to-differential amplification unit; the positive signal input end of the third comparator receives a weighted signal +0.38Q output by the single-end-to-differential amplification unit, and the negative signal input end of the third comparator receives a weighted signal-0.38I output by the single-end-to-differential amplification unit; a positive signal input end of the fourth comparator receives a weighted signal +0.38I output by the single-end-to-differential amplification unit, and a negative signal input end of the fourth comparator receives a weighted signal-0.92Q output by the single-end-to-differential amplification unit; a positive signal input end of the fifth comparator receives a weighted signal +0.92Q output by the single-end-to-differential amplification unit, and a negative signal input end of the fifth comparator receives a weighted signal-0.92Q output by the single-end-to-differential amplification unit; a positive signal input end of the sixth comparator receives a weighted signal +0.92Q output by the single-end-to-differential amplification unit, and a negative signal input end of the sixth comparator receives a weighted signal +0.38I output by the single-end-to-differential amplification unit; a positive signal input end of the seventh comparator receives a weighted signal-0.38I output by the single-end-to-differential amplification unit, and a negative signal input end of the seventh comparator receives a weighted signal-0.38Q output by the single-end-to-differential amplification unit; the positive signal input end of the eighth comparator receives a weighted signal +0.38Q output by the single-end-to-differential amplification unit, and the negative signal input end of the eighth comparator is connected with a weighted signal +0.92I output by the single-end-to-differential amplification unit;
the LVDS output buffer module is composed of 12 LVDS output buffer units, each LVDS output buffer unit receives the output of one comparator or redundant comparator and is used for continuously shaping the square wave output by the comparator and outputting the square wave meeting the LVDS standard, and therefore the digital transmission and processing in the future are facilitated.
2. The high-precision 16-bit phase quantization analog-to-digital converter of claim 1, wherein the input pre-amplifying unit, the single-ended to differential amplifying unit, the comparator, the redundancy comparator and the LVDS output buffer unit all adopt conventional amplifier structures.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606320A (en) * | 1994-12-06 | 1997-02-25 | Pacesetter Inc. | Method and apparatus for micropower analog-to-digital conversion in an implantable medical device |
| CN103178850A (en) * | 2013-03-06 | 2013-06-26 | 南京国博电子有限公司 | Circuit structure of 4bit phase quantization analog-to-digital converter |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606320A (en) * | 1994-12-06 | 1997-02-25 | Pacesetter Inc. | Method and apparatus for micropower analog-to-digital conversion in an implantable medical device |
| CN103178850A (en) * | 2013-03-06 | 2013-06-26 | 南京国博电子有限公司 | Circuit structure of 4bit phase quantization analog-to-digital converter |
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Application publication date: 20200911 |
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