CN111654272A - Drive control circuit - Google Patents
Drive control circuit Download PDFInfo
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- CN111654272A CN111654272A CN201911359198.1A CN201911359198A CN111654272A CN 111654272 A CN111654272 A CN 111654272A CN 201911359198 A CN201911359198 A CN 201911359198A CN 111654272 A CN111654272 A CN 111654272A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
Abstract
The invention provides a drive control circuit which comprises two drive chips, a dead zone generating circuit, a pulse generating circuit, two delay circuits and two totem-pole circuits, wherein reset pins of the two drive chips are connected with the output end of the pulse generating circuit; the output ends of the two totem-pole circuits are respectively connected with the upper tube and the lower tube; the output end of the delay circuit is connected with the input end of the dead zone generating circuit. The drive control circuit has simple structure and low cost, can realize the independent turn-off function of a power device (IGBT or MOSFET) without depending on the CPLD, reduces the probability and time of the motor controller entering a safe working mode caused by the self fault of the CPLD, and enhances the independence between the electrical functions without depending on the CPLD.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a driving control circuit.
Background
High reliability vehicle motor controllers, due to functional safety requirements, typically component manufacturers increase the cost of some hardware and software solutions to meet functional safety requirements. In order to confirm an independent turn-off path and dead time of a power device (such as an IGBT) in an existing product, a programmable logic gate (CPLD) needs to be added to realize the safe turn-off of the IGBT, so that the power device can be safely turned off when a short-circuit fault or an under-voltage fault of a driver occurs.
The existing prior art for realizing independent turn-off of the IGBT mainly has the following disadvantages:
(1) due to the use of the CPLD, the complexity of the control system and the material cost of the electric control unit are increased.
(2) When the CPLD has internal faults and the internal clock is inconsistent with the external clock. To ensure the functional safety of the motor controller, the motor controller is forced to switch to a safe state even under the condition that the IGBT does not have a short circuit or the driver is under-voltage. The performance and user experience of the motor controller is impaired from the point of view of the fail-safe running time of the motor controller.
(3) The power supply scheme of the driving circuit depends on the clock signal of the CPLD, so that the reliability dependency relationship exists between the driving circuit and the CPLD.
In view of the deficiencies of the prior art in achieving independent turn-off of IGBTs, those skilled in the art are always seeking solutions.
Disclosure of Invention
The invention aims to provide a drive control circuit to overcome the defects of the prior art for realizing independent turn-off of an IGBT.
In order to solve the above technical problem, the present invention provides a driving control circuit, which is adapted to independently turn off an upper tube and a lower tube in a driving control bridge arm, and comprises: the circuit comprises two driving chips, a dead zone generating circuit, a pulse generating circuit, two delay circuits and two totem-pole circuits, wherein reset pins of the two driving chips are connected with the output end of the pulse generating circuit, pulse width modulation input pins of the two driving chips are connected with the output end of the dead zone generating circuit, and output pins of the two driving chips are respectively connected with the input end of the totem-pole circuit; the output ends of the two totem-pole circuits are respectively connected with the upper tube and the lower tube; and the output end of the delay circuit is connected with the input end of the dead zone generating circuit.
Optionally, in the drive control circuit, the upper tube and the lower tube are both field effect transistors or insulated gate bipolar transistors.
Optionally, in the drive control circuit, the dead band generating circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a first comparator and a second comparator, wherein the third resistor is connected with the second capacitor in parallel and then connected with the positive input end of the second comparator; one end of the second capacitor is connected with the second resistor, and the other end of the second capacitor is grounded; the positive input end of the first comparator is connected with the negative input end of the second comparator, the first resistor is connected with one end of the first capacitor and then connected with the negative input end of the first comparator, and the other end of the first capacitor is grounded; the output end of the first comparator is connected with a pulse width modulation input pin of a driving chip indirectly connected with the upper tube; and the output end of the second comparator is connected with a pulse width modulation input pin of a driving chip indirectly connected with the lower tube.
Optionally, in the drive control circuit, the pulse generating circuit includes: the circuit comprises a third capacitor, a first diode, a fourth resistor, a fifth resistor, a sixth resistor and a third comparator, wherein one end of the fourth resistor is respectively connected with one end of the third capacitor and the anode of the first diode, and the other end of the fourth resistor is grounded; the cathode of the first diode is connected with the sixth resistor in series and then is connected with the positive input end of the third comparator; one end of the fifth resistor is connected with the cathode of the first diode, and the other end of the fifth resistor is grounded; and the output end of the third comparator is used as the output end of the pulse generating circuit.
Optionally, in the drive control circuit, the dead time of the dead time generation circuit is 2 μ s, the pulse duration generated by the pulse generation circuit is 1ms, and the delay time of the delay circuit is 1 ms.
Optionally, in the drive control circuit, each totem-pole circuit includes an N-type triode and a P-type triode, an emitter of the N-type triode is connected with an emitter of the P-type triode and is connected with a gate of an upper tube or a lower tube through a resistor, a base of the N-type triode is connected with a base of the P-type triode and is connected with an output pin of the drive chip as an input end of the totem-pole circuit; and the collector electrode of the N-type triode is connected with a power supply of the upper tube or the lower tube, and the collector electrode of the P-type triode is grounded.
Optionally, the driving control circuit further includes a first or gate, a second or gate, an NMOS transistor, and a second diode connected in parallel and in reverse direction with the NMOS transistor, the two delay circuits include a first delay circuit and a second delay circuit, the first delay circuit receives a trigger signal of a lower tube, and an output end of the first delay circuit is connected to an input end of the dead zone generating circuit through the first or gate; the second delay circuit receives a trigger signal of an upper tube, the output end of the second delay circuit is connected with the input end of the second OR gate, the output end of the second OR gate is connected with the grid electrode of the NMOS tube, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the output end of the first OR gate; the trigger signal of the lower tube is generated when the drive chip indirectly connected with the lower tube outputs a short-circuit fault signal and/or a power supply under-voltage fault signal; the trigger signal of the upper tube is generated when the drive chip indirectly connected with the upper tube outputs a short-circuit fault signal and/or a power supply under-voltage fault signal.
Optionally, the drive control circuit further includes a third or gate, an input end of the third or gate receives a trigger signal of an upper tube and a trigger signal of a lower tube, and an output end of the third or gate is connected to an input end of the pulse generating circuit.
Optionally, in the drive control circuit, an input terminal of the first or gate further receives a U-phase half-bridge tube signal; and the input end of the second OR gate also receives a power supply abnormity or program disorder signal and a fault signal that the voltage of the direct-current bus is overhigh.
Optionally, in the drive control circuit, each driver chip further includes a short-circuit fault signal output pin and a power supply under-voltage fault signal output pin.
In the drive control circuit provided by the invention, the drive control circuit comprises two drive chips, a dead zone generating circuit, a pulse generating circuit, two delay circuits and two totem-pole circuits, wherein reset pins of the two drive chips are connected with the output end of the pulse generating circuit, pulse width modulation input pins of the two drive chips are connected with the output end of the dead zone generating circuit, and output pins of the two drive chips are respectively connected with the input end of the totem-pole circuit; the output ends of the two totem-pole circuits are respectively connected with the upper tube and the lower tube; and the output end of the delay circuit is connected with the input end of the dead zone generating circuit. The drive control circuit has simple structure and low cost, can realize the independent turn-off function of a power device (IGBT or MOSFET) without depending on the CPLD, reduces the probability and time of the motor controller entering a safe working mode caused by the self fault of the CPLD, and enhances the independence between the electrical functions without depending on the CPLD.
Drawings
FIG. 1 is a circuit diagram of a driving control circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a dead band generation circuit in an embodiment of the present invention;
FIG. 3 is a circuit diagram of a pulse generation circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the trigger signal generation process for all upper and lower tubes in the inverter according to an embodiment of the present invention;
FIG. 5 is a simulation result of a dead band generation circuit in an embodiment of the present invention;
FIG. 6 shows a simulation result of a pulse duration of 1ms generated by the pulse generation circuit according to an embodiment of the present invention.
Detailed Description
The driving control circuit according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Certain terms are used throughout the description and claims to refer to particular system components. As one skilled in the art will appreciate, different companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …".
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
Furthermore, each of the embodiments described below has one or more technical features, and thus, the use of the technical features of any one embodiment does not necessarily mean that all of the technical features of any one embodiment are implemented at the same time or that only some or all of the technical features of different embodiments are implemented separately. In other words, those skilled in the art can selectively implement some or all of the features of any embodiment or combinations of some or all of the features of multiple embodiments according to the disclosure of the present invention and according to design specifications or implementation requirements, thereby increasing the flexibility in implementing the invention.
The present invention will be described in more detail with reference to the accompanying drawings, in order to make the objects and features of the present invention more comprehensible, embodiments thereof will be described in detail below, but the present invention may be implemented in various forms and should not be construed as being limited to the embodiments described.
Please refer to fig. 1, which is a circuit diagram of a driving control circuit according to the present invention. The driving control circuit is suitable for driving and controlling independent turn-off of an upper tube Q1 and a lower tube Q2 in a bridge arm. As shown in fig. 1, the drive control circuit includes: the circuit comprises two driving chips, a dead zone generating circuit, a pulse generating circuit, two delay circuits and two totem-pole circuits, wherein reset pins RST of the two driving chips are connected with the output end of the pulse generating circuit, pulse width modulation input pins Pwm _ in of the two driving chips are connected with the output end of the dead zone generating circuit, and output pins of the two driving chips are respectively connected with the input end of the totem-pole circuit; the output ends of the two totem-pole circuits are respectively connected with the upper tube Q1 and the lower tube Q2; and the output end of the delay circuit is connected with the input end of the dead zone generating circuit. The upper tube Q1 and the lower tube Q2 are both power devices, specifically field effect transistors (MOSFETs) or Insulated Gate Bipolar Transistors (IGBTs), the driving chips are driving chips with an isolation function and used for driving the power devices, each driving chip corresponds to one power device, and when the two driving chips respectively drive the upper tube Q1 and the lower tube Q2, the independent turn-off of the upper tube Q1 and the lower tube Q2 can be realized based on the circuit design of the driving control circuit of the present invention. The totem-pole circuit is used for increasing current capacity. When a reset signal is input to a reset pin RST of the driving chip, the output of a Pwm signal of the driving chip is blocked.
Here, the dead time of the dead time generation circuit, the pulse duration generated by the pulse generation circuit, and the delay time of the delay circuit may be selectively set according to actual conditions. The dead time of the dead time generation circuit in this embodiment is preferably 2 μ s, the pulse duration generated by the pulse generation circuit is preferably 1ms, and the delay time of the delay circuit is preferably 1 ms.
Referring to fig. 1 and fig. 2, fig. 2 is a circuit diagram of a dead-time generation circuit in the present embodiment. As shown in fig. 2, the dead zone generation circuit includes: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a first comparator CP1 and a second comparator CP2, wherein the third resistor R3 is connected with the second capacitor C2 in parallel and then connected with the positive input end of a second comparator CP 2; one end of the second capacitor C2 is connected with the second resistor R2, and the other end is grounded; a positive input end of the first comparator CP1 is connected to a negative input end of the second comparator CP2, the first resistor R1 is connected to one end of the first capacitor C1 and then to the negative input end of the first comparator CP1, and the other end of the first capacitor C1 is grounded; the output end of the first comparator CP1 is connected with a pulse width modulation input pin Pwm _ in of a driving chip indirectly connected with an upper tube Q1; the output terminal of the second comparator CP2 is connected to the Pwm input pin Pwm _ in of the driver chip indirectly connected to the lower tube Q2.
Please refer to fig. 3, which is a circuit diagram of the pulse generating circuit in the present embodiment. As shown in fig. 3, the pulse generating circuit includes: the pulse generator comprises a third capacitor C3, a first diode (D1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a third comparator CP3, wherein one end of the fourth resistor R4 is respectively connected with one end of the third capacitor C3 and the anode of the first diode (D1), the other end of the fourth resistor R4 is grounded, the cathode of the first diode D1 is connected with the sixth resistor R6 in series and then is connected with the positive input end of the third comparator CP3, one end of the fifth resistor R5 is connected with the cathode of the first diode D1, the other end of the fifth resistor R5 is grounded, and the output end of the third comparator CP3 serves as the output end of the pulse generation circuit.
With reference to fig. 1, each totem-pole circuit includes an N-type triode and a P-type triode, an emitter of the N-type triode is connected to an emitter of the P-type triode and is connected to a gate of an upper tube Q1 or a lower tube Q2 through a resistor, a base of the N-type triode is connected to a base of the P-type triode and is connected to an output pin of the driving chip as an input terminal of the totem-pole circuit; the collector of the N-type triode is connected with a power supply (PVDD _ HU or PVDD _ LU) of an upper tube Q1 or a lower tube Q2, and the collector of the P-type triode is grounded.
Further, the drive control circuit further comprises a first OR gate OR1, a second OR gate OR2, a third OR gate OR3, an NMOS transistor and a second diode D2 connected in parallel and in reverse direction with the NMOS transistor, the two delay circuits comprise a first delay circuit and a second delay circuit, the first delay circuit receives a trigger signal of a lower tube Q2, and an output end of the first delay circuit is connected with an input end of the dead zone generation circuit through the first OR gate; the second delay circuit receives a trigger signal of an upper tube Q1, the output end of the second delay circuit is connected with the input end of the second OR gate, the output end of the second OR gate is connected with the grid electrode of the NMOS tube, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the output end of the first OR gate; the input end of the third OR gate OR3 receives a trigger signal of an upper tube Q1 and a trigger signal of a lower tube Q2, and the output end of the third OR gate OR3 is connected with the input end of the pulse generating circuit. The trigger signal of the lower tube Q2 is generated when the drive chip indirectly connected with the lower tube Q2 outputs a short-circuit fault signal and/or an under-voltage power supply fault signal; the trigger signal of the upper tube Q1 is generated when the drive chip indirectly connected with the upper tube Q1 outputs a short-circuit fault signal and/or an under-voltage power fault signal.
Please refer to fig. 1 and 4 to understand the generation process of the trigger signal. Fig. 4 is a schematic diagram of the trigger signal generation process for all upper and lower tubes in the inverter. As shown in fig. 1, each driver chip further includes a short-circuit Fault signal output pin SC _ Fault _ UH and an under-voltage power Fault signal output pin UV _ Fault _ UH, where a signal output by the short-circuit Fault signal output pin SC _ Fault _ UH is a short-circuit Fault signal, and a signal output by the under-voltage power Fault signal output pin UV _ Fault _ UH is an under-voltage power Fault signal.
The process of generating the trigger signal is explained in detail below by taking an example in which the inverter includes 6 IGBTs. The circuit diagram of the driving control circuit in fig. 1 is a situation of an upper tube Q1 and a lower tube Q2 arranged in a U-phase arm in the inverter, and actually, a driving control circuit is also respectively arranged for an upper tube Q1 and a lower tube Q2 in a V-phase arm and a W-phase arm in the inverter (i.e., the same as U), and since the circuit layout of the driving control circuit for each phase of the inverter is the same, redundant description is not repeated here. As shown in fig. 4, the short-circuit Fault signals output by the driver chips of the upper tubes in the U-phase, the V-phase, and the W-phase of the inverter are SC _ Fault _ UH, SC _ Fault _ VH, and SC _ Fault _ WH, respectively, and the trigger signal NFLTAH of the upper tube is generated when the driver chip of the upper tube in any phase (U-phase, V-phase, OR W-phase) outputs the short-circuit Fault signal through the OR gate OR. The power supply under-voltage Fault signals output by the driving chips of the upper tubes in the U-phase, the W-phase and the V-phase of the inverter are respectively UV _ Fault _ UH, UV _ Fault _ VH and UV _ Fault _ WH, and the driving chip of the upper tube in any phase (the U-phase, the V-phase OR the W-phase) outputs the power supply under-voltage Fault signals, so that the trigger signal NFLTBH of the upper tube is generated through an OR gate OR.
Short-circuit Fault signals output by the driving chips of the lower tubes in the U-phase, the V-phase and the W-phase of the inverter are SC _ Fault _ UL, SC _ Fault _ VL and SC _ Fault _ WL respectively, and when the driving chip of the lower tube in any phase (the U-phase, the V-phase OR the W-phase) outputs a short-circuit Fault signal, a trigger signal NFLTAL of the lower tube is generated through an OR gate OR. The undervoltage power failure signals output by the driving chip of the lower tube in the U-phase, the W-phase and the V-phase of the inverter are respectively UV _ Fault _ UL, UV _ Fault _ VL and UV _ Fault _ WL, and the driving chip of the lower tube in any phase (the U-phase, the V-phase OR the W-phase) outputs the undervoltage power failure signals, so that the trigger signal NFLTBL of the lower tube is generated through an OR gate OR. As shown in fig. 3, once any IGBT has a short-circuit fault or an undervoltage fault, an enable pulse with a duration of 1ms is finally output through the or logic of the third or gate, thereby ensuring that all the driver chips synchronously block PWM (pulse width modulation) signals of 6 IGBTs.
In order to ensure that when the motor controller enters an active short circuit mode (ASC) from a normal working state, overshoot phenomenon exists in the current of the stator side. The pulse generated by the pulse generating circuit can be maintained for a preset time to ensure that 6 IGBTs of the inverter are in a PWM signal blocking stage within the preset time before the motor controller enters an active short-circuit mode (ASC). After a predetermined time, the upper three tubes (or the lower three tubes) of the inverter are automatically selected to enter the ASC according to the circuit logic shown in fig. 1.
In this embodiment, the input end of the first OR gate OR1 further receives a U-phase Half-bridge upper tube signal HBHU _ I _ INV, where HBHU is called Half bridge upper High in english; the input of the second OR gate OR2 also receives: the DSP (digital signal processor) power supply monitoring chip can send out a power supply abnormity or program disorder signal SZTKT (high availability) and a fault signal NUZKMAX with overhigh direct-current bus voltage, so that the DSP is ensured to enter a safety mode of a lower three-tube ASC under a fault mode of power supply abnormity or program disorder. In other words, as long as the first or gate receives any one of the output signal of the first delay circuit and the U-phase half-bridge tube-passing signal HBHU _ I _ INV, the first or gate outputs a tube-passing pulse width modulation signal Pwm _ HU; and as long as the second OR gate receives any one of the signal output by the second delay circuit, the power supply abnormality or program disorder signal SZTKT and the fault signal NUZKMAX with overhigh direct-current bus voltage, the second OR gate outputs a signal to the drain electrode of the NMOS tube. In order to ensure the protection of overvoltage at the direct current bus side of the motor controller, the definition of the safety state is to make the lower three tubes of the motor inverter enter an ASC mode. According to the dead zone generation circuit shown in fig. 2, the PWM _ HU signal is forced to be pulled low by the conducting MOS transistor, thereby ensuring that the lower three transistors enter the ASC mode.
To verify the feasibility of the above-mentioned part of the critical circuit, simulation results are given for the two subcircuits of fig. 2 and 3. Fig. 5 is a simulation result of the dead zone generation circuit, in which simulation waveforms of PWM _ HU and the generated two complementary PWM _ lower (corresponding to PWM _ Q1 in fig. 3), PWM _ upper (corresponding to PWM _ Q2 in fig. 3) are respectively given. Fig. 6 is a simulation result of a Pulse generated by the Pulse generating circuit with a Pulse duration of 1ms, in which the input Fault signal is Fault _ in, and an enable Pulse _1ms with a Pulse width of 1ms is output after passing through the Pulse generating circuit.
In summary, in the driving control circuit provided by the present invention, the driving control circuit includes two driving chips, a dead zone generating circuit, a pulse generating circuit, two delay circuits, and two totem-pole circuits, reset pins of the two driving chips are connected to an output terminal of the pulse generating circuit, pulse width modulation input pins of the two driving chips are connected to an output terminal of the dead zone generating circuit, and output pins of the two driving chips are connected to an input terminal of one totem-pole circuit respectively; the output ends of the two totem-pole circuits are respectively connected with the upper tube and the lower tube; and the output end of the delay circuit is connected with the input end of the dead zone generating circuit. The drive control circuit has simple structure and low cost, can realize the independent turn-off function of a power device (IGBT or MOSFET) without depending on the CPLD, reduces the probability and time of the motor controller entering a safe working mode caused by the self fault of the CPLD, and enhances the independence between the electrical functions without depending on the CPLD.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A drive control circuit adapted for drive control of independent turn-off of an upper tube (Q1) and a lower tube (Q2) in a bridge arm, comprising: the circuit comprises two driving chips, a dead zone generating circuit, a pulse generating circuit, two delay circuits and two totem-pole circuits, wherein reset pins (RST) of the two driving chips are connected with the output end of the pulse generating circuit, pulse width modulation input pins (Pwm _ in) of the two driving chips are connected with the output end of the dead zone generating circuit, and output pins of the two driving chips are respectively connected with the input end of the totem-pole circuit; the output ends of the two totem-pole circuits are respectively connected with the upper tube and the lower tube; and the output end of the delay circuit is connected with the input end of the dead zone generating circuit.
2. The drive control circuit of claim 1, wherein the upper tube and the lower tube are both field effect transistors (MOSFETs) or Insulated Gate Bipolar Transistors (IGBTs).
3. The drive control circuit according to claim 1, wherein the dead zone generating circuit includes: the circuit comprises a first resistor (R1), a second resistor (R2), a third resistor (R3), a first capacitor (C1), a second capacitor (C2), a first comparator (CP1) and a second comparator (CP2), wherein the third resistor (R3) is connected with the second capacitor (C2) in parallel and then connected with the positive input end of the second comparator (CP 2); one end of the second capacitor (C2) is connected with the second resistor (R2), and the other end is grounded; the positive input end of the first comparator (CP1) is connected with the negative input end of the second comparator (CP2), the first resistor (R1) is connected with one end of the first capacitor (C1) and then connected with the negative input end of the first comparator (CP1), and the other end of the first capacitor (C1) is grounded; the output end of the first comparator (CP1) is connected with a pulse width modulation input pin (Pwm _ in) of a driving chip indirectly connected with an upper tube; the output of the second comparator (CP2) is connected to the pulse width modulation input pin (Pwm _ in) of the driver chip which is indirectly connected to the lower tube.
4. The drive control circuit of claim 3, wherein the pulse generation circuit comprises: a third capacitor (C3), a first diode (D1), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6) and a third comparator (CP3), wherein one end of the fourth resistor (R4) is respectively connected with one end of the third capacitor (C3) and the anode of the first diode (D1), and the other end of the fourth resistor is grounded; the cathode of the first diode (D1) is connected with the positive input end of the third comparator (CP3) after being connected with the sixth resistor (R6) in series; one end of the fifth resistor (R5) is connected with the cathode of the first diode (D1), and the other end is grounded; the output terminal of the third comparator (CP3) is used as the output terminal of the pulse generating circuit.
5. The drive control circuit according to claim 4, wherein the dead time of the dead time generation circuit is 2 μ s, the pulse duration generated by the pulse generation circuit is 1ms, and the delay time of the delay circuit is 1 ms.
6. The driving control circuit as claimed in claim 4, wherein each totem-pole circuit comprises an N-type triode and a P-type triode, an emitter of the N-type triode is connected with an emitter of the P-type triode and is connected with a gate of an upper tube or a lower tube through a resistor, a base of the N-type triode is connected with a base of the P-type triode and is connected with an output pin of the driving chip as an input end of the totem-pole circuit; the collector of the N-type triode is connected with a power supply (PVDD _ HU or PVDD _ LU) of an upper tube or a lower tube, and the collector of the P-type triode is grounded.
7. The drive control circuit of claim 6, further comprising a first OR gate (OR1), a second OR gate (OR2), an NMOS transistor, and a second diode (D2) connected in parallel and in reverse with the NMOS transistor, wherein the two delay circuits include a first delay circuit and a second delay circuit, the first delay circuit receives a trigger signal of a lower tube, and an output terminal of the first delay circuit is connected to an input terminal of the dead zone generation circuit through the first OR gate; the second delay circuit receives a trigger signal of an upper tube, the output end of the second delay circuit is connected with the input end of the second OR gate, the output end of the second OR gate is connected with the grid electrode of the NMOS tube, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the output end of the first OR gate; the trigger signal of the lower tube is generated when the drive chip indirectly connected with the lower tube outputs a short-circuit fault signal and/or a power supply under-voltage fault signal; the trigger signal of the upper tube is generated when the drive chip indirectly connected with the upper tube outputs a short-circuit fault signal and/or a power supply under-voltage fault signal.
8. The drive control circuit of claim 7, further comprising a third OR gate (OR3), an input of the third OR gate (OR3) receiving a trigger signal for an upper tube and a trigger signal for a lower tube, an output of the third OR gate (OR3) being connected to an input of the pulse generation circuit.
9. The drive control circuit of claim 7, wherein the input of the first OR gate (OR1) further receives a U-phase half-bridge tube-over-bridge signal (HBHU _ I _ INV); the input of the second OR-gate (OR2) also receives a mains supply anomaly OR program disturbance Signal (SZTKT) and a fault signal (NUZKMAX) that the dc bus voltage is too high.
10. The driving control circuit according to any one of claims 1 to 9, wherein each driving chip further comprises a short-circuit Fault signal output pin (SC _ Fault _ UH) and an under-voltage power Fault signal output pin (UV _ Fault _ UH).
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| CN201911359198.1A CN111654272A (en) | 2019-12-25 | 2019-12-25 | Drive control circuit |
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| CN201911359198.1A CN111654272A (en) | 2019-12-25 | 2019-12-25 | Drive control circuit |
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Cited By (4)
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| CN113114110A (en) * | 2021-04-23 | 2021-07-13 | 长城电源技术有限公司 | Power supply driving module and power supply equipment |
| CN113315355A (en) * | 2021-07-02 | 2021-08-27 | 上海空间电源研究所 | High-reliability delay isolation driving circuit for spacecraft |
| CN114296506A (en) * | 2021-12-30 | 2022-04-08 | 青岛青源峰达太赫兹科技有限公司 | Adjustable bias voltage source suitable for high-precision terahertz time-domain spectroscopy system |
| CN116778646A (en) * | 2023-08-24 | 2023-09-19 | 深圳和成东科技有限公司 | Intelligent cash register circuit device |
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| CN113114110A (en) * | 2021-04-23 | 2021-07-13 | 长城电源技术有限公司 | Power supply driving module and power supply equipment |
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| CN116778646A (en) * | 2023-08-24 | 2023-09-19 | 深圳和成东科技有限公司 | Intelligent cash register circuit device |
| CN116778646B (en) * | 2023-08-24 | 2023-10-20 | 深圳和成东科技有限公司 | Intelligent cash register circuit device |
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