CN111654269A - Method for eliminating current overshoot and switching circuit - Google Patents

Method for eliminating current overshoot and switching circuit Download PDF

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Publication number
CN111654269A
CN111654269A CN202010668661.7A CN202010668661A CN111654269A CN 111654269 A CN111654269 A CN 111654269A CN 202010668661 A CN202010668661 A CN 202010668661A CN 111654269 A CN111654269 A CN 111654269A
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power
integrator
power failure
current
state
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闫志光
刘柳胜
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MAXIC TECHNOLOGY (BEIJING) CO LTD
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MAXIC TECHNOLOGY (BEIJING) CO LTD
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention provides a method for eliminating current overshoot and a switch circuit, belonging to the field of switch power supplies and comprising the steps of judging whether a system enters a power-down state or not; if the system enters a power-down state, starting a power-down protection device; and when the power failure time reaches a preset time, and the preset time is longer than the period time of the bus voltage VM, the integrator performs reverse integration. The invention relates to a method for eliminating current overshoots, according to which an error signal V is generatedcompThe signal rising is limited, and after the power is re-electrified, the current overshoot is limited, so that the overshoot phenomenon of the output current can be greatly reduced.

Description

Method for eliminating current overshoot and switching circuit
Technical Field
The invention belongs to the field of switching power supplies, and particularly relates to a method for eliminating current overshoot and a switching circuit.
Background
In the design and implementation of the switch-mode power supply circuit, the integrating loop is a common circuit (as shown in fig. 1 and fig. 2). Referring to fig. 1, after passing through a rectifier bridge, the commercial power outputs a dc signal VM (bus voltage) to power the switch mode power supply. The switch type power supply is composed of an Error Amplifier (EA), a driver, a switch network, a feedback circuit and the like. The feedback circuit samples the output voltage or current electrical parameters to obtain a feedback signal VfbThen fed back to an input (e.g., inverting input) of the error amplifier and set to the reference potential VrefComparing and amplifying to output a fault at the output of EADifference signal Vcomp. When the feedback signal VfbBelow VrefTime, error signal Vcomp(ii) is increased; on the contrary, when the feedback signal VfbGreater than VrefTime, error signal VcompAnd decreases. Error signal VcompComparing the driver with a sawtooth wave (or triangular wave) signal to obtain a PWM (Pulse-width-modulation) signal V with variable duty ratiopwm。VpwmThe power switch tube M1 in the driving switch network is turned on and off, and the switch of M1 controls the energy storage device, such as the inductor L, to store and release energy, so as to control the output voltage or current to reach a preset value.
In the switch type integral loop power supply circuit in fig. 1 and 2, if the input commercial power is off (the wall switch is turned off), the output voltage and current are reduced until the output voltage and current are reduced to zero, and the feedback electrical parameter VfbThe signal also tapers off, resulting in an error signal V during power downcompGradually increase until it is far above V in steady statecompThe value is obtained. Referring to FIG. 4, if the system is powered back up, the error signal is already much larger than V at normal steady statecompThe duty ratio of the PWM signal generated by the driver is relatively large, resulting in an output current ILAnd is also much larger than the current in steady state, i.e. causes current overshoot, which is detrimental to the reliability of the system.
Disclosure of Invention
The invention aims to provide a method for eliminating current overshoot and a switch circuit, and aims to solve the technical problems that when the conventional switch type power supply system is powered up again in the power failure process, current overshoot is easily caused, and the reliability of the system is damaged.
In order to achieve the purpose, the invention adopts the technical scheme that: a method for eliminating current overshoot and a switching circuit are provided, which comprises the following steps:
judging whether the system enters a power-down state or not;
when the system enters a power-down state, starting a power-down protection device;
and when the power failure time reaches a preset time, and the preset time is longer than the period time of the bus voltage VM, the integrator performs reverse integration.
Further, the judging whether the system enters a power-down state includes:
and acquiring power failure parameters, and judging whether the system enters a power failure state or not according to the power failure parameter change state.
Further, acquiring a power-down parameter, and judging whether the system enters a power-down state according to a power-down parameter change state comprises:
acquiring bus voltage VM, wherein the bus voltage VM is lower than a power-down threshold voltage and continuously drops; and judging that the system enters a power-down state.
Further, acquiring a power-down parameter, and judging whether the system enters a power-down state according to a power-down parameter change state comprises:
and acquiring the current or voltage of a sampling resistor, wherein the current or voltage of the sampling resistor is lower than a threshold value, and when the current or voltage of the sampling resistor continuously drops, judging that the system enters a power-down state.
Further, the method also comprises the steps of obtaining power failure parameters and judging whether to end the power failure state.
Further, the acquiring the power-down parameter and judging whether to end the power-down state includes:
and acquiring a bus voltage VM which is higher than a power-on threshold value, ending the power-down state of the system, and recovering the original state of the integrator.
Further, the acquiring the power-down parameter and judging whether to end the power-down state includes:
and acquiring a sampling resistance parameter, wherein the sampling resistance parameter is higher than a power-on threshold value, the system finishes a power-down state, and the integrator recovers an original state.
Further, the sampled resistance parameter comprises a sampled resistance voltage or a sampled resistance current
Further, the inverse integration time is between 0-.
Further, the inverse integration time is.
Further, the inverse integration time is greater than.
The invention also provides a switching circuit which is characterized by comprising a power-down protection device, wherein the power-down protection device controls the integrator according to the method
Furthermore, the power failure protection device comprises a power failure detection device and a power failure timer, wherein the power failure detection device detects the bus voltage VM, and controls the integrator to work according to the timing of the power failure timer.
Furthermore, the power failure protection device comprises a power failure detection device and a power failure timer, wherein the power failure detection device detects electrical parameters of the sampling resistor, and controls the integrator to work according to the timing of the power failure timer.
Further, the integrator includes an error amplifier EA and an integrating capacitor C connected in series with the error amplifier EAcomp。
Further, the integrator is a digital integrator.
The method for eliminating the current overshoot and the switch circuit provided by the invention have the beneficial effects that: compared with the prior art, the method for eliminating the current overshoot provided by the invention has the advantages that when the integrator reaches the time, the integrator symmetrically reverses the integration time period, and the error signal V is generated at the timecompThe signal is 0, and after the power is re-electrified, the overshoot phenomenon does not occur. In another case, the error signal V is only integrated by the integrator in the reverse directioncompIt becomes smaller and the overshoot effect can be reduced. According to the switch circuit provided by the invention, when the power is re-electrified in the power-down process, the current overshoot phenomenon is reduced or eliminated, the damage to the switch circuit is small, and the service life of the switch circuit is prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a circuit diagram of an integration loop provided in the prior art;
FIG. 2 is a circuit diagram of another integration loop provided by the prior art;
fig. 3 is a schematic diagram of a relative relationship between an error signal, a bus voltage, and an output current after a loop system provided in the prior art is stabilized.
Fig. 4 is a schematic diagram of a relative relationship between an error signal, a bus voltage, and an output current when a loop system provided in the prior art is powered up again.
FIG. 5 is a block diagram of a method for eliminating current overshoot according to a first embodiment of the present invention;
FIG. 6 is a stop-symmetrical integral waveform of the present invention;
FIG. 7 is a block diagram of a method for eliminating current overshoot by bus sampling according to a second embodiment of the present invention;
FIG. 8 is a block diagram of a method for eliminating current overshoot by sampling with a sampling resistor according to a third embodiment of the present invention;
FIG. 9 is a schematic diagram of ending a power-down state in a fourth embodiment of the present invention;
FIG. 10 is a schematic diagram of a four-bus sampling circuit according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a five-sampling resistor sampling circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The switching buck type LED constant current driving circuit in the prior art comprises an integrator, wherein the integrator consists of an error amplifier EA and an integrating capacitor CcompThe integrator transmits the electric signal of the sampling resistor to the driver through integration processing; the driver being dependent on the error signal V output by the integratorcompPWM signal V generated by comparing with sawtooth wave or triangular wavepwm，VpwmThe power switch tube M1 is driven to be turned on and off.
When M1 is on, current flows through the LED string, through inductors L, M1, and through resistor Rcs.
When M1 is off, current flows through the LED string, inductor L and freewheeling diode D.
With the technical scheme in the prior art, when a bus is powered off, an error signal V can be generatedcompRaised condition. If the power is quickly powered on, the PWM signal is increased, and the output current I is increasedLIncreasing beyond the steady state current creates an overshoot.
In order to solve the above technical problem, the present application provides the following embodiments:
example 1
As shown in fig. 5, a method for eliminating current overshoot provided by the present invention includes the following steps:
judging whether the system enters a power-down state or not;
when the system enters a power failure state, starting a power failure protection device, and starting a power failure timer to record power failure time;
when the power-off time reaches a preset time, the integrator starts to perform inverse integration, wherein the preset time is greater than the period time of the bus voltage VM.
The voltage of the sampling resistor is reduced due to the reduction of the bus voltage caused by power failure, so that the voltage of the sampling resistor is reduced, and V is further causedrefAnd VfbIs increased, the error signal V generated by the integratorcompWill increase, causing the driver to generate a PWM signal exceeding the steady state value, outputting a current ILIncreasing beyond the steady state current creates an overshoot.
Therefore, in the present embodiment, by controlling the integrator, the error signal V due to long-time integration is prevented from being causedcompContinues to increase. By setting a reasonable preset time, the integrator is stopped in a reasonable range to prevent VcompWhen the rising time is increased continuously, the integrator is integrated in the reverse direction on the basis of the rising time, and the error signal V is further reducedcompThe current overshoot phenomenon is reduced when the bus is powered up again.
In order to ensure that the integrator works normally, the preset time in this embodiment needs to be longer than the cycle time of the bus voltage. I.e. greater than or equal to 10ms for 50Hz mains.
As shown in the waveform diagram of fig. 6, when the bus voltage is lower than the power-down threshold voltage and continuously decreases, the bus voltage enters a power-down state, the recording of the power-down time is started, and at this time, because the bus voltage starts to decrease, the error signal V output by the integratorcompIncreasing, when the power-off time reaches the preset time, the integrator starts to perform inverse integration to prevent the error signal VcompThe continuous increase results in an overshoot phenomenon.
Example 1.1
The embodiment is further optimized on the basis of the embodiment 1. As shown in fig. 5, a method for eliminating current overshoot provided by the present invention includes the following steps:
judging whether the system enters a power-down state or not;
when the system enters a power failure state, starting a power failure protection device, and starting a power failure timer to record power failure time;
when the power-off time reaches a preset time, the integrator starts to perform inverse integration, wherein the preset time is greater than the period time of the bus voltage VM.
The voltage of the sampling resistor is reduced due to the reduction of the bus voltage caused by power failure, so that the voltage of the sampling resistor is reduced, and V is further causedrefAnd VfbIs increased, the error signal V generated by the integratorcompWill increase, causing the driver to generate a PWM signal exceeding the steady state value, outputting a current ILIncreasing beyond the steady state current creates an overshoot.
As can be seen from fig. 6, the error V is integrated at time instantcompReaches a maximum value, at which point the inverse integration, the integration error VcompWill be reduced, integrating the error V at any time between from 2compWill be smaller than the error peak, see the integral error V from any time to 2compMay serve to reduce current overshoot.
Particularly at time 2, when the integral error V is presentcompAnd when the integral is zero, the integration is stopped, the system is waited to be powered on again, and the overshoot phenomenon cannot exist in the system.
When the inverse integration time exceeds the time, i.e. exceeds 2 moments, the integration error VcompAre still less than the error peak, at which point power is re-applied,the overshoot phenomenon can be suppressed.
It should be noted that the power-down threshold voltage can be set by a user according to actual conditions.
It should be noted that, when the bus is powered off, the integrator in the invention integrates upwards, and the error signal VcompIn the rise state, which is related to the positive and negative termination of the integrator, but both reflect the error signal VcompVariations from the initial values do not depart from the problems reflected in the substance of this application.
Example 2
As shown in fig. 7, a method for eliminating current overshoot includes the following steps:
obtaining bus voltage parameters, and when the bus voltage is less than the power-down threshold voltage VPLAnd the bus voltage continues to drop (as shown in fig. 6), at which point the determination system enters a powered down state.
Starting a power failure protection device, and starting a power failure timer to record power failure time;
when the power-off time reaches a preset time, the integrator performs inverse integration, wherein the preset time is greater than the period time of the bus voltage VM.
When the inverse integration time of the integrator is reached, namely the inverse integration reaches 2 moments, the integrator stops integrating until the system is powered on next time. The same inverse integration time may be any time from 2 in embodiment 1, or may be greater than 2.
The voltage of the sampling resistor is reduced due to the reduction of the bus voltage caused by power failure, so that the voltage of the sampling resistor is reduced, and V is further causedrefAnd VfbIs increased, the error signal V generated by the integratorcompWill increase, causing the driver to generate a PWM signal exceeding the steady state value, outputting a current ILIncreasing beyond the steady state current creates an overshoot.
As can be seen from fig. 6, the error V is integrated at time instantcompReaches a maximum value, at which point the inverse integration, the integration error VcompWill be reduced, integrating the error V at any time between from 2compWill be smaller than the error peak, see the integral error V from any time to 2compAll can play a role in reducing current passingThe function of the dashes.
Particularly at time 2, when the integral error V is presentcompAnd when the integral is zero, the integration is stopped, the system is waited to be powered on again, and the overshoot phenomenon cannot exist in the system.
When the inverse integration time exceeds the time, i.e. exceeds 2 moments, the integration error VcompThe error peak value is still smaller, and the overshoot phenomenon can be restrained by electrifying again at the moment.
On the basis of the first embodiment, the present embodiment further defines it. And judging the working condition of the bus by acquiring the bus voltage, and presuming whether the system is in a power-down state. Compared with other sampling modes, the method is more direct, and the circuit is simpler to realize.
Example 3
As shown in fig. 8, a method for eliminating current overshoot includes the following steps:
and acquiring electrical parameters of the sampling resistor, and when the electrical parameters of the sampling resistor are smaller than a threshold value and continuously decrease, judging that the system enters a power-down state. Wherein the sampled resistive electrical parameter comprises a sampled resistive current or voltage.
Starting a power failure protection device, and starting a power failure timer to record power failure time;
when the power-off time reaches a preset time, the integrator reversely integrates to the moment 2, wherein the preset time is larger than the period time of the bus voltage VM.
The voltage of the sampling resistor is reduced due to the reduction of the bus voltage caused by power failure, so that the voltage of the sampling resistor is reduced, and V is further causedrefAnd VfbIs increased, the error signal V generated by the integratorcompWill increase, causing the driver to generate a PWM signal exceeding the steady state value, outputting a current ILIncreasing beyond the steady state current creates an overshoot.
Therefore, in the present embodiment, by controlling the integration time of the integrator, the error signal is prevented from continuously increasing due to long-time integration. When the power-down duration is reached, the integrator starts to perform inverse integration to the 2 nd moment, and the error signal V is obtainedcomp0, there is no overshoot.
In order to ensure that the integrator works normally, the preset time in this embodiment needs to be longer than the cycle time of the bus voltage. I.e. greater than or equal to 10ms for 50Hz mains.
On the basis of the first embodiment, the present embodiment further defines it. In the embodiment, whether the system enters a power-down state or not is determined by acquiring the electrical parameters of the sampling resistor. The difference of the electrical parameters of the sampling resistor is very obvious between the two states of power-on and power-off of the system, so that the judgment on whether the power-off is carried out can be realized without an excessively precise detection means.
On the basis of the first to third embodiments, the method further comprises the steps of obtaining the power failure parameter and judging whether to end the power failure state.
Example 4
And judging whether the system is in a power-down state or not by any one of the first to third methods or combination of the first to third embodiments.
A method of eliminating current overshoot comprising:
and acquiring a bus voltage parameter, and when the bus voltage is smaller than the power-down threshold voltage and the bus voltage continuously drops (as shown in fig. 6), judging that the system enters a power-down state.
And/or
And acquiring electrical parameters of the sampling resistor, and when the electrical parameters of the sampling resistor are smaller than a threshold value and continuously decrease, judging that the system enters a power-down state. Wherein the sampled resistive electrical parameter comprises a sampled resistive current or voltage.
Starting a power failure protection device, and starting a power failure timer to record power failure time;
and when the power-off time reaches a preset time, stopping integrating by the integrator, wherein the preset time is greater than the period time of the bus voltage VM.
After the steps are completed, the system enters a power-down state, and the integrator performs inverse integration.
As shown in fig. 9, the power-down parameter is obtained in real time, and when the electrical parameter is greater than the threshold, the system ends the power-down state, and the integrator recovers the integration. Wherein the electrical parameter comprises one or a combination of a bus voltage or a current of the sampling resistor.
The bus sampling has the following advantages: the mode of judging whether to enter the power-down state or not through the bus voltage state is more direct and obvious, and the circuit is simpler to realize.
Sampling resistance sampling has the following advantages: the difference of the electrical parameters of the sampling resistor is large in two states of system power-on and system power-off, and the power-off state can be judged without an excessively precise detection means.
On the basis of the first to fourth embodiments, the present application further provides a switch circuit for implementing the method in the above embodiments.
Example 5
As shown in fig. 10, the present invention provides a switching circuit with power-down protection function, which includes a rectifier bridge for converting an ac voltage into a dc voltage, a diode D, LED string light and a filter capacitor connected in parallel, wherein an inductor L is connected in series between the diode D and the LED string light, and a power tube M1 and a sampling resistor R connected in series are connected between the diode D and the inductor LCSWherein the resistance R is sampledCSGrounding;
comprising an integrator, a driver stage for generating an error signal V based on the output of the integratorcompComparing with sawtooth wave to generate PWM signal Vpwm，VpwmThe power switch tube M1 is driven to be turned on and off.
When M1 is on, current flows through LED string light, inductor L, M1 and resistor Rcs。
When M1 is off, current flows through the LED string, inductor L and freewheeling diode D.
Still include the power down protection device, the power down protection device includes power down detection device and power down timer, like power down detection device follows the bus sampling in this embodiment. And judging the working condition of the bus by acquiring the bus voltage, and presuming whether the system is in a power-down state. Compared with other sampling modes, the method is more direct, and the circuit is simpler to realize.
Example 6
As shown in FIG. 11, the present invention provides a switching circuit with power down protection function, comprising a rectifier bridge for converting AC voltage into DC voltageThe LED lamp comprises a current voltage, a diode D, LED lamp string and a filter capacitor which are connected in parallel, wherein an inductor L is connected between a diode D and the LED lamp string in series, and a power tube M1 and a sampling resistor R which are connected in series are connected between the diode D and the inductor LCSWherein the resistance R is sampledCSGrounding;
comprising an integrator, a driver stage for generating an error signal V based on the output of the integratorcompComparing with sawtooth wave to generate PWM signal Vpwm，VpwmThe power switch tube M1 is driven to be turned on and off.
When M1 is on, current flows through the LED string, through inductors L, M1, and through resistor Rcs.
When M1 is off, current flows through the LED string, inductor L and freewheeling diode D.
The power failure protection device comprises a power failure detection device and a power failure timer, and the power failure detection device samples from the sampling resistor in the embodiment. The difference between the electrical parameters of the sampling resistor when the system is powered on and the system is powered off is very obvious, so that the judgment on whether the power is off can be realized without an excessively precise detection means. Wherein the sampled resistance electrical parameter comprises a current or a voltage of the sampled resistance.
In this embodiment, the sampling resistor is disposed at a ground position, and the sampling resistor may be located at any position in the circuit that can be realized without departing from the spirit of the present application.
It should be noted that, in the above embodiment, the integrator includes the error amplifier EA and the integrating capacitor C connected in series with the error amplifier EAcomp. Or the integrator is a digital integrator.
In the above embodiment, the power-down detection device has a preset parameter V thereinref2And the power failure detection circuit is used for comparing with the sampling electrical parameter to judge the power failure state.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (16)

1. A method of eliminating current overshoot, comprising:
judging whether the system enters a power-down state or not;
when the system enters a power-down state, starting a power-down protection device;
and when the power failure time reaches a preset time, and the preset time is longer than the period time of the bus voltage VM, the integrator performs reverse integration.
2. The method of claim 1, wherein determining whether the system has entered a power-down state comprises:
and acquiring power failure parameters, and judging whether the system enters a power failure state or not according to the power failure parameter change state.
3. The method for eliminating the current overshoot as claimed in claim 2, wherein the step of obtaining the power-down parameter and the step of judging whether the system enters the power-down state according to the power-down parameter change state comprises the following steps:
acquiring bus voltage VM, wherein the bus voltage VM is lower than a power-down threshold voltage and continuously drops; and judging that the system enters a power-down state.
4. The method for eliminating the current overshoot as claimed in claim 2, wherein the step of obtaining the power-down parameter and the step of judging whether the system enters the power-down state according to the power-down parameter change state comprises the following steps:
and acquiring the current or voltage of a sampling resistor, wherein the current or voltage of the sampling resistor is lower than a threshold value, and when the current or voltage of the sampling resistor continuously drops, judging that the system enters a power-down state.
5. The method for eliminating the current overshoot as claimed in claim 1, further comprising obtaining a power down parameter and determining whether to end the power down state.
6. The method for eliminating current overshoot according to claim 5, wherein the obtaining the power-down parameter and the determining whether to end the power-down state comprises:
and acquiring a bus voltage VM which is higher than a power-on threshold value, ending the power-down state of the system, and recovering the original state of the integrator.
7. The method for eliminating current overshoot according to claim 5, wherein the obtaining the power-down parameter and the determining whether to end the power-down state comprises:
and acquiring a sampling resistance parameter, wherein the sampling resistance parameter is higher than a power-on threshold value, the system finishes a power-down state, and the integrator recovers an original state.
8. The method as claimed in claim 7, wherein the sampled resistor parameter comprises a sampled resistor voltage or a sampled resistor current.
9. The method as claimed in claim 1, wherein the inverse integration time is between 0-inclusive.
10. The method as claimed in claim 1, wherein the inverse integration time is.
11. The method of claim 1, wherein the inverse integration time is greater than.
12. A switching circuit comprising power down protection means, said power down protection means controlling an integrator in accordance with the method of any one of claims 1 to 11.
13. A switching circuit according to claim 12, wherein: the power failure protection device comprises a power failure detection device and a power failure timer, wherein the power failure detection device detects the bus voltage VM, and controls the integrator to work according to the timing of the power failure timer.
14. A switching circuit according to claim 12, wherein: the power failure protection device comprises a power failure detection device and a power failure timer, wherein the power failure detection device detects electrical parameters of a sampling resistor, and controls the integrator to work according to the timing of the power failure timer.
15. A switching circuit according to claim 13 or 14, wherein: the integrator comprises an error amplifier EA and an integrating capacitor C connected in series with the error amplifier EAcomp。
16. A switching circuit according to claim 13 or 14, wherein: the integrator is a digital integrator.
CN202010668661.7A 2020-07-13 2020-07-13 Method for eliminating current overshoot and switching circuit Pending CN111654269A (en)

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Application Number Priority Date Filing Date Title
CN202010668661.7A CN111654269A (en) 2020-07-13 2020-07-13 Method for eliminating current overshoot and switching circuit

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Address before: Room 01, 10 / F, block a, Tiangong building, No.30 Xueyuan Road, Haidian District, Beijing

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