CN113394964B - Control circuit and PFC circuit applying same - Google Patents
Control circuit and PFC circuit applying same Download PDFInfo
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- CN113394964B CN113394964B CN202110659531.1A CN202110659531A CN113394964B CN 113394964 B CN113394964 B CN 113394964B CN 202110659531 A CN202110659531 A CN 202110659531A CN 113394964 B CN113394964 B CN 113394964B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a control circuit and a PFC circuit using the same, wherein a power stage circuit in the PFC circuit is enabled to be in a working state when the amplitude of alternating current input voltage is lower; when the amplitude of the alternating-current input voltage is higher, the PFC circuit is not enabled to be in a stop working state, so that the overall efficiency of the system can be improved, and the capacity of an output capacitor is reduced.
Description
Technical Field
The present invention relates to power electronics, and more particularly, to a control circuit and a PFC circuit using the same.
Background
In various drivers, PF (power factor) is an important energy saving index, which not only affects the conversion efficiency of the driver, but also pollutes the power grid of the whole power supply system when the power factor is low, so the requirements on PFC circuits (power factor correction circuits) are higher and higher.
As shown in fig. 1, an operation waveform diagram of a conventional PFC circuit is shown, in which the PFC circuit outputs a voltage V BUS Set value V of (2) BUS,REF Is very high, no matter the input voltage V IN The PFC circuit continuously works due to the high and low amplitude, and the system efficiency is low due to the working mode, especially when the input voltage V is input IN When the voltage boosting ratio of the power level circuit is low, the duty ratio is large, and the loss is obvious; and in order to reduce the output voltage V BUS The ripple of the (c) output capacitor is also typically large, resulting in an excessively large system volume.
Disclosure of Invention
In view of the above, the present invention provides a control circuit and a PFC circuit using the same, so as to solve the problems of large loss and excessive volume of the existing PFC circuit system.
In a first aspect, a control circuit is provided, applied to a PFC circuit, the PFC circuit further includes a power stage circuit, the PFC circuit converts an ac input voltage into a dc bus voltage and outputs the dc bus voltage, and is characterized in that,
and the control circuit controls the enabling state of the power stage circuit in one power frequency period according to the amplitude of the alternating current input voltage so as to improve the efficiency of the PFC circuit.
Preferably, the control circuit controls the power stage circuit to be enabled to be in an operating state when the amplitude of the ac input voltage is low; is not enabled to be in a stop operation state when the amplitude of the alternating input voltage is high.
Preferably, the control circuit controls the power stage circuit to be in an operating state all the time in one power frequency period when the peak value of the alternating current input voltage is in the first state so that the direct current bus voltage is always smaller than an overvoltage threshold value.
Preferably, the control circuit controls the power stage circuit to be in a stop working state all the time in one power frequency period when the peak value of the alternating current input voltage is in the second state so that the direct current bus voltage is always larger than the expected value of the direct current bus voltage.
Preferably, the control circuit controls the power stage circuit to be in an alternately operating and inactive state in one power frequency period when the peak value of the ac input voltage is between the first state and the second state.
Preferably, the control circuit detects the magnitude of the input ac voltage by acquiring the magnitude of the dc bus voltage.
Preferably, the control circuit determines the enabling state of the power stage circuit in a power frequency period according to the comparison result of the direct current bus voltage and an overvoltage threshold value representing the overvoltage of the direct current bus voltage and/or an expected value of the direct current bus voltage.
Preferably, the control circuit controls the power stage circuit not to be enabled to be in a stop working state when the direct current bus voltage is larger than the overvoltage threshold value; and the power stage circuit is enabled to be in an operating state when the dc bus voltage is less than the desired value.
Preferably, the dc bus voltage is enabled to be in an operating state when it is greater than the desired value and not greater than the overvoltage threshold value, and is brought into a rest state when it is greater than the overvoltage threshold value until it is less than the desired value.
Preferably, the expected value is not greater than a peak value at which the ac input voltage is maximum.
Preferably, a dc bus capacitor is disposed at an output end of the power stage circuit, and a capacitance value of the dc bus capacitor is set so that the dc bus voltage is still greater than the desired value when the load is fully loaded.
Preferably, the control circuit includes an enabling circuit, the enabling circuit includes:
the non-inverting input end of the first comparator receives the expected value, the inverting input end of the first comparator receives the direct current bus voltage or a sampling signal representing the direct current bus voltage, and the output end of the first comparator outputs a first comparison signal;
the non-inverting input end of the second comparator receives the direct current bus voltage or a sampling signal representing the direct current bus voltage, the inverting input end of the second comparator receives the overvoltage threshold value, and the output end of the second comparator outputs a second comparison signal;
a logic circuit that sets an enable signal when the first comparison signal is valid; and resetting the enable signal when the second comparison signal is valid, wherein the enable signal is used for controlling the enable state of the power stage circuit.
Preferably, the control circuit further comprises a driving circuit, and the driving circuit is used for converting a switch control signal for controlling the power switch in the power stage circuit into a driving signal, and the enabling signal controls the enabling state of the power stage circuit by controlling the enabling state of the driving circuit.
Preferably, the control circuit further includes a switch control signal generating circuit, where the switch control signal generating circuit generates a switch control signal according to the dc bus voltage, the expected value, and a switch current sampling signal in the power stage circuit, where the switch control signal is used to control a switching state of a power switch in the power stage circuit, so that the dc bus voltage is maintained at the expected value, and a power factor of the PFC circuit meets a working requirement.
Preferably, the power stage circuit operates in a constant peak current mode.
Preferably, when the power stage circuit is in the stop working state, the power stage circuit provides a through passage, and the direct current input voltage obtained by filtering the alternating current input voltage is directly transmitted to the output end of the power stage circuit to be used as the direct current bus voltage.
Preferably, when the power stage circuit is in the working state, a power switch in the power stage circuit is controlled to switch a switch state, and the direct current input voltage obtained after the alternating current input voltage is filtered is boosted to obtain the expected direct current bus voltage.
Preferably, the capacitance value of the dc bus capacitor is set so that the power stage circuit is always in a stop working state in a power frequency period when the amplitude of the ac input voltage is greater than a predetermined value.
In a second aspect, a PFC circuit is provided, which includes:
a power stage circuit, and,
the control circuit.
The power stage circuit in the PFC circuit is enabled to be in a working state when the amplitude of the alternating current input voltage is low; when the amplitude of the alternating-current input voltage is higher, the PFC circuit is not enabled to be in a stop working state, so that the overall efficiency of the system can be improved, and the capacity of an output capacitor is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a waveform diagram of the operation of a conventional PFC circuit;
fig. 2 is a circuit configuration diagram of a PFC circuit according to a first embodiment of the present invention;
fig. 3 is a circuit configuration diagram of a PFC circuit according to a second embodiment of the present invention;
fig. 4a is a waveform diagram of the PFC circuit according to the second embodiment;
fig. 4b is another operation waveform diagram of the PFC circuit according to the second embodiment;
fig. 4c is a further operational waveform diagram of the PFC circuit according to the second embodiment.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Meanwhile, it should be understood that in the following description, "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
Fig. 2 is a circuit configuration diagram of a PFC circuit according to a first embodiment of the present invention. As shown in fig. 2, the PFC circuit includes a rectifying circuit 21, a power stage circuit 22, and a control circuit 23.
Specifically, the rectifying circuit 21 receives an AC input voltage AC, rectifies the AC input voltage AC, and outputs a dc input voltage V IN . The rectifier circuit 21 may be a full bridge type rectifier bridge or a half bridge type rectifier bridge. The output of the rectifying circuit 21 may be equivalently a direct-current voltage source.
The power stage circuit 22 includes components such as an inductor (or transformer), a power switch, and a diode, and directly receives the dc input voltage V output from the rectifying circuit IN By controlling the conduction state of the power switch, the input current and the input voltage waveforms of the power stage circuit are basically consistent, and the output voltage is basically constant. Here, the power stage circuit 22 is of a boost topology, and the power stage circuit 22 includes an inductor L1 connected to an input terminal thereof, a main power switch Q1 coupled to the inductor L1, a diode D coupled to a common terminal of the inductor L1 and the main power switch Q1, and a dc bus capacitor C connected to an output terminal thereof BUS To be used in DC bus capacitor C BUS Generates a DC bus voltage V across BUS . DC bus voltage V BUS As an input voltage to the subsequent stage converter to power the load.
The control circuit 23 generates a switch control signal to control the switch state of the power switch in the power stage circuit 22 according to the feedback signals of the voltage and the current in the power stage circuit 22 so as to enable the DC bus voltage V BUS Maintained at the desired value V BUS,REG In the vicinity, the control circuit 23 also controls the enabling state of the power stage circuit 22 in one power frequency period by controlling whether the switch control signal acts on the power switch in the power stage circuit 22 according to the magnitude of the alternating input voltage AC, so that the efficiency of the PFC circuit is improved.
Specifically, the control circuit 23 controls the power stage circuit 22 to be enabled to be in an operating state when the amplitude of the alternating input voltage AC is low; is not enabled to be in a deactivated state when the amplitude of the alternating input voltage AC is high.
Further, the control circuit 23 is based on a DC busLine voltage V BUS With an overvoltage threshold V representing the overvoltage of the DC bus voltage BUS,OVP Expected value V of dc bus voltage BUS,REG Determines the enable state of the power stage circuit 22 during a power frequency cycle. Further, the control circuit 23 controls the power stage circuit 22 to control the DC bus voltage V BUS Greater than the overpressure threshold V BUS,OVP Is not enabled to be in a stop working state; and at the power stage circuit 22 at the dc bus voltage V BUS Less than the expected value V BUS,REG When enabled to be in an operative state.
In addition, in the present invention, since the power stage circuit 22 is operated not at all times in one power frequency period but only when the amplitude of the alternating input voltage AC is low, the direct current bus voltage V BUS Is set to the desired value V of BUS,REG Not necessarily higher than the maximum value of the peak value of the alternating input voltage AC, but a lower desired value V than in the prior art can be chosen BUS,REG 。
It should be noted that the control circuit 23 may directly obtain the dc bus voltage V BUS Can also obtain the actual value of the characteristic DC bus voltage V BUS To the actual value or the sampling value and the overpressure threshold V BUS,OVP Desired value V BUS,REG And determines the enable state of the power stage circuit in a power frequency cycle.
It should be further noted that when the power stage circuit 22 is not enabled and is in the inactive state, it means that the power stage circuit 22 provides a through-path in the through state to input the dc input voltage V IN Directly to the output of the power stage circuit 22 as a DC bus voltage V BUS The method comprises the steps of carrying out a first treatment on the surface of the When the power stage circuit 22 is enabled to be in the working state, it means that the power stage circuit 22 is in the PWM state, the power switch is controlled by the switch control signal to switch the switch state, and the dc input voltage V is applied IN Boosting to obtain DC bus voltage V BUS And to make the DC bus voltage V BUS Maintained at the desired value V BUS,REG Nearby.
In addition, it should be specifically noted that the circuit of the PFC circuit of the first embodiment is described by taking the conventional PFC circuit structure having the rectifier circuit 21 as an example, however, in some bridgeless PFC circuits, the structures of the rectifier bridge and the inverter are combined together, and the power stage circuit in the PFC circuit can directly process the AC input voltage AC, in which case a separate rectifier circuit is not required.
The power stage circuit in the PFC circuit is enabled to be in a working state when the amplitude of the alternating current input voltage AC is low; is not enabled to be in a stop working state when the amplitude of the alternating current input voltage AC is higher, thereby leading to the direct current bus voltage V BUS Is set to the desired value V of BUS,REG A lower value can be chosen. In this operating mode, on the one hand, the power stage circuit is enabled to be in operation when the amplitude of the alternating input voltage AC is low, due to the desired value V BUS,REG The duty ratio of the power stage circuit is correspondingly reduced because of the relatively low level, so that the working efficiency of the power stage circuit is improved; on the other hand, when the amplitude of the AC input voltage AC is high, the power stage circuit is not enabled to be in a stop working state, and provides a through passage for the DC input voltage V IN To the output of the power stage circuit as a DC bus voltage V BUS In the process, as no switching action exists in the power stage circuit, the switching loss is reduced, and the PFC circuit can improve the overall efficiency of the system by combining the two reasons.
Fig. 3 is a circuit configuration diagram of a PFC circuit according to a second embodiment of the present invention. The difference from the first embodiment is that the specific structure of the control circuit 33 is disclosed, and other parts of the circuit, such as the rectifying circuit 31 and the power stage circuit 32, are the same as the circuit structure and the operation principle of the rectifying circuit 21 and the power stage circuit 22 in the first embodiment, and are not described herein.
The control circuit 33 is arranged to control the AC input voltage AC at a peak value significantly lower than the desired value V of the dc bus voltage BUS,REG In a first state, the power stage circuit 32 is controlled to be always in an operating state in one power frequency periodThe method comprises the steps of carrying out a first treatment on the surface of the The control circuit 33 is substantially higher than the desired value V of the dc bus voltage at the peak of the AC input voltage AC BUS,REG In a second state, the control power stage circuit 32 is always in a stop state in one power frequency period; the control circuit 33 controls the power stage circuit 32 to be alternately operated and deactivated during one power frequency period when the peak value of the alternating input voltage AC is between the first state and the second state.
Preferably, the control circuit 33 includes an enable circuit 331, a switch control signal generating circuit 332, and a driving circuit 333.
Specifically, the enable circuit 331 obtains the dc bus voltage V BUS To detect the amplitude of the input AC voltage AC and further to apply the DC bus voltage V BUS Or its sampling value and desired value V BUS,REG Over-pressure threshold V BUS,OVP The enable signal EN is compared to control the enable state of the power stage circuit 32.
In an embodiment of the present invention, the enabling circuit 331 includes: a first comparator CMP1 having a non-inverting input receiving the desired value V BUS,REG The inverting input terminal receives the DC bus voltage V BUS Or to characterize the dc bus voltage V BUS Is a sampled signal V of (1) SAM In the embodiment of the invention, the DC bus voltage V is selected to be represented BUS Is a sampled signal V of (1) SAM An inverting input terminal of the first comparator CMP1 is connected to sample the signal V SAM Voltage dividing circuit composed of two resistors connected in series for dividing DC bus voltage V BUS Obtained after voltage division in a certain proportion to fit other parameters in the circuit, and the switch control signal generating circuit 332 in the control circuit 33 also needs to generate the voltage V according to the DC bus BUS Or to characterize the dc bus voltage V BUS Is a sampled signal V of (1) SAM Generates a switch control signal, so that the sampling signal V SAM Can be provided for multiplexing of two-part circuit modules. The output end of the first comparator CMP1 outputs a first comparison signal V1; a second comparator CMP2 having a non-inverting input receiving the DC bus voltage V BUS Or to characterize the dc bus voltage V BUS Is of the (a)The signal, here too, is chosen to characterize the DC bus voltage V BUS Is a sampled signal V of (1) SAM Connected to the non-inverting input of the second comparator CMP2, the inverting input of which receives the overvoltage threshold V BUS,OVP The output end outputs a second comparison signal V2; the logic circuit, here an SR flip-flop, has a set terminal S receiving the first comparison signal V1, sets the enable signal EN when the first comparison signal V1 is valid, has a reset terminal R receiving the second comparison signal V2, resets the enable signal EN when the second comparison signal V2 is valid, and outputs the enable signal EN at an output terminal Q of the SR flip-flop, wherein the enable signal EN is used to control the enable state of the power stage circuit 32.
The control circuit 33 further comprises a switch control signal generating circuit 332, wherein the switch control signal generating circuit 332 generates the DC bus voltage V according to the DC bus voltage BUS Expected value V BUS,REG And a switching current sampling signal V in the power stage circuit 32 I Generating a switch control signal V Q To control the switching state of the power switches in the power stage circuit 32, wherein the rectifier power switches in the boost converter are diodes D, so that the main power switch Q1 is controlled to make the DC bus voltage V BUS Maintained at a characteristic DC bus voltage V BUS Desired value V of desired amplitude of (2) BUS,REG Nearby, and such that the input current and input voltage waveforms of the power stage circuit 32 are substantially identical, i.e., the power factor PF of the PFC circuit meets the operating requirements. In the present embodiment, the current flowing through the main power switch Q1 is sampled by a resistor connected between the main power switch Q1 and the reference ground to obtain a switch current sampling signal V I 。
In an embodiment of the present invention, power stage circuit 32 operates in a constant peak current mode. The switch control signal generation circuit 332 includes an error amplifier EA, the input of which characterizes the dc bus voltage V BUS Is a sampled signal V of (1) SAM And an expected value V BUS,REG Output error compensation signal V C Wherein the output end of the error amplifier EA is provided with a compensation capacitor V C . In the present embodiment, the signal V is sampled SAM Inverting input to error amplifier EAInput end, expected value V BUS,REG Is input to the non-inverting input of the error amplifier EA. The switch control signal generating circuit 332 further comprises a comparator CMP3 for comparing the error compensation signal V C And a switching current sampling signal V I And outputs a control signal V for enabling the switch Q Reset signal V for reset R In the present embodiment, the error compensation signal V C Input to the inverting input of comparator CMP3, switching current sampling signal V I Is input to the non-inverting input of comparator CMP 3. Such a circuit configuration may enable the switching current to sample the signal V I Reaching the error compensation signal V C When the main power switch Q1 is turned off, so that the peak value of the switching current is maintained near the error compensation signal. So that the switch control signal V Q Set signal V of set S The set signal V for setting can be a clock signal or generated by other control modes S Set signal V S And reset signal V R Respectively connected to the set terminal S and the reset terminal R of the SR trigger to generate a switch control signal V at the output terminal Q thereof Q . Of course, those skilled in the art will appreciate that in other embodiments, the switching current may be sinusoidal.
The control circuit 33 further comprises a driving circuit 333, the driving circuit 333 is used for controlling the switch control signal V of the power switch in the power stage circuit 32 Q Converted into a driving signal V Q1 The enable signal EN generated by the enable circuit 331 controls the enable state of the power stage circuit 32 by controlling the enable state of the drive circuit 333. That is, when the enable signal EN is active, the driving circuit 333 is enabled to output the driving signal V Q1 The method comprises the steps of carrying out a first treatment on the surface of the When the enable signal EN is inactive, the driving circuit 333 is not enabled and does not output the driving signal V Q1 Thereby the PFC circuit can control the signal V by controlling the switch according to the amplitude of the input voltage AC Q Whether to act on the main power switch Q1 in the power stage circuit 32 to control the enabling state of the power stage circuit 32 in one power frequency period, so that the efficiency of the PFC circuit is improved. It should be appreciated that the control switch control signal V Q Whether to act on a master in the power stage circuit 32The power switch Q1 can be provided in more than one way, and the enable signal EN can be applied to the control switch control signal V Q Is generated, i.e. when the enable signal EN is active, by switching the control signal V Q Normally transferred to the driving circuit 333, when the enable signal EN is inactive, the switch control signal V is enabled Q Are all inactive, so that the driving circuit 333 outputs an inactive driving signal V Q1 The power switches in the power stage circuit 32 are likewise deactivated.
Further, the output end of the power stage circuit 32 is provided with a DC bus capacitor C BUS DC bus capacitor C BUS The capacity value of the capacitor is set to meet the voltage V of the direct current bus when the load is fully loaded BUS Still greater than the desired value V BUS,REG And at a preset input voltage V ACR The PFC circuit is not operated at all, here, the input voltage V ACR Is the effective value of the alternating current input voltage AC, T AC Is a power frequency period.
In one particular application, assume an output power of 120W, V BUS,REG 250V and is at the effective value V of the alternating input voltage AC ACR When the voltage is more than 210V, the power stage circuit is not operated, and in the scheme of the invention, the direct current bus capacitor C BUS In the prior art, the capacitance of (C) is 19uF, whereas in the prior art scheme, the dc bus capacitor C BUS The capacitance of (2) is approximately between 100uF and 120 uF. Therefore, the technical scheme of the invention not only can improve the overall efficiency of the PFC circuit, but also can reduce the capacity of the output capacitor.
Fig. 4a is a waveform diagram of the PFC circuit according to the second embodiment when the AC input voltage AC is low; fig. 4b shows the PFC circuit according to the second embodiment when the AC input voltage AC approaches the dc bus voltage V BUS An operating waveform diagram at a desired amplitude; fig. 4c is a waveform diagram of the PFC circuit according to the second embodiment when the AC input voltage AC is high. The following describes the working principle of the PFC circuit according to the present invention with reference to the working waveform diagram:
as shown in fig. 4a, when the peak value of the alternating input voltage AC is lower than the desired value V BUS,REG When, i.e. DC input voltage V IN Peak value lower than desired value V BUS,REG At the time, the DC bus voltage V BUS Will not be higher than the overpressure threshold V BUS,OVP The power stage circuit 32 is therefore always in an enabled operating state for one power frequency period. At this time, the boost converter continuously works in a constant peak current control mode, and can also work in a sinusoidal current envelope mode of the traditional PFC. Voltage threshold V of output voltage of boost converter at the same time BUS,REG I.e. the desired value V BUS,REG The boost voltage of the boost converter is much lower than that of the boost converter in a common PFC circuit, so that the boost converter has higher efficiency when the AC input voltage AC is lower;
as shown in fig. 4b, when the peak value of the alternating input voltage AC is close to the desired value V BUS,REG When, i.e. DC input voltage V IN The peak value of the signal is close to the expected value V BUS,REG At the time, the DC bus voltage V BUS Will be between the expected value V BUS,REG Over-pressure threshold V BUS,OVP And therefore the power stage circuit 32 is in intermittent operation during one power frequency cycle. When the direct current is input to voltage V IN The boost converter is operated at all times near the valley, when the DC input voltage V IN When rising, due to the DC bus capacitor C BUS Smaller and slower control loop, DC bus voltage V BUS Will also continuously rise above the desired value V BUS,REG . Further, if the DC bus voltage V BUS Exceeding the overpressure threshold V BUS,OVP When the boost converter stops switching until the DC bus voltage V BUS And is lower than the expected value V BUS,REG Until that point.
As shown in fig. 4c, when the peak value of the alternating input voltage AC is higher than the desired value V BUS,REG At a certain threshold value, i.e. the DC input voltage V IN Peak value higher than desired value V BUS,REG At the time, and the DC bus voltage V BUS Is also higher than the desired value V BUS,REG At the same time, i.e. DC bus voltage V BUS Is not lower than the expected value V BUS,REG The power stage circuit 32 is therefore always disabled for one power frequency cycle, i.e. the entire power frequency cycle boost converter is not operating. Therefore, the automatic transition to a non-working state is realized, high efficiency is realized when the alternating current input voltage AC is higher, and the output end of the power stage circuit is allowed to have larger ripple waves, so that compared with the traditional PFC circuit, the capacitance value of the output capacitor required by the traditional PFC circuit is smaller, and the capacity and the volume of the output capacitor of the power stage circuit are reduced.
In summary, the power stage circuit in the PFC circuit is enabled to be in a working state when the amplitude of the AC input voltage AC is low; when the amplitude of the alternating current input voltage AC is higher, the PFC circuit is not enabled to be in a stop working state, so that the overall efficiency of the system can be improved, and the capacity of an output capacitor is reduced.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (16)
1. A control circuit is applied to a PFC circuit, the PFC circuit also comprises a power stage circuit, the PFC circuit converts an alternating current input voltage into a direct current bus voltage and outputs the direct current bus voltage, and is characterized in that,
the control circuit controls the enabling state of the power stage circuit in one power frequency period according to the amplitude of the alternating current input voltage so as to improve the efficiency of the PFC circuit, and controls the power stage circuit to be always in a working state in one power frequency period when the peak value of the alternating current input voltage is in a first state so that the direct current bus voltage is always smaller than an overvoltage threshold value; when the peak value of the alternating current input voltage is in a second state so that the direct current bus voltage is always larger than the expected value of the direct current bus voltage, controlling the power stage circuit to be always in a stop working state in one power frequency period, wherein the overvoltage threshold value is larger than the expected value;
when the power stage circuit is not enabled to be in a stop working state, the power stage circuit provides a through passage, and the direct current input voltage obtained by rectifying and filtering the alternating current input voltage is directly transmitted to the output end of the power stage circuit to serve as the direct current bus voltage.
2. The control circuit of claim 1, wherein the control circuit controls the power stage circuit to be enabled to be in an operating state when the magnitude of the ac input voltage is low; is not enabled to be in a stop operation state when the amplitude of the alternating input voltage is high.
3. The control circuit of claim 1, wherein the control circuit controls the power stage circuit to be alternately operated and deactivated during one power frequency cycle when the peak value of the ac input voltage is between the first state and the second state.
4. A control circuit according to claim 3, wherein the control circuit detects the magnitude of the ac input voltage by obtaining the magnitude of the dc bus voltage.
5. Control circuit according to claim 1, characterized in that the control circuit decides the enabling state of the power stage circuit in one power frequency cycle on the basis of the comparison of the dc bus voltage with an overvoltage threshold value representing the overvoltage of the dc bus voltage and/or an expected value of the dc bus voltage.
6. The control circuit of claim 5, wherein the control circuit controls the power stage circuit not to be enabled to be in a deactivated state when the dc bus voltage is greater than the overvoltage threshold; and the power stage circuit is enabled to be in an operating state when the dc bus voltage drops to the desired value.
7. The control circuit of claim 5, wherein the dc bus voltage is enabled to be in an operating state when the dc bus voltage is greater than the desired value and not greater than the overvoltage threshold value, and wherein the off-operating state is entered when the dc bus voltage is greater than the overvoltage threshold value until the dc bus voltage is less than the desired value.
8. The control circuit of claim 5, wherein the desired value is not greater than a peak value at which the ac input voltage is maximum.
9. The control circuit of claim 5, wherein the output of the power stage circuit is provided with a dc bus capacitor, and the capacitance of the dc bus capacitor is set such that the dc bus voltage is still greater than the desired value when the load is fully loaded.
10. The control circuit of claim 5, wherein the control circuit comprises an enable circuit, the enable circuit comprising:
the non-inverting input end of the first comparator receives the expected value, the inverting input end of the first comparator receives the direct current bus voltage or a sampling signal representing the direct current bus voltage, and the output end of the first comparator outputs a first comparison signal;
the non-inverting input end of the second comparator receives the direct current bus voltage or a sampling signal representing the direct current bus voltage, the inverting input end of the second comparator receives the overvoltage threshold value, and the output end of the second comparator outputs a second comparison signal;
a logic circuit that sets an enable signal when the first comparison signal is valid; and resetting the enable signal when the second comparison signal is valid, wherein the enable signal is used for controlling the enable state of the power stage circuit.
11. The control circuit of claim 10, further comprising a driver circuit for converting a switch control signal for controlling a power switch in the power stage circuit into a drive signal, the enable signal controlling an enable state of the power stage circuit by controlling an enable state of the driver circuit.
12. The control circuit of claim 5, further comprising a switch control signal generating circuit configured to generate a switch control signal according to the dc bus voltage, the desired value, and a switch current sampling signal in the power stage circuit, the switch control signal configured to control a switching state of a power switch in the power stage circuit so that the dc bus voltage is maintained at the desired value and so that a power factor of the PFC circuit meets an operating requirement.
13. The control circuit of claim 1, wherein the power stage circuit operates in a constant peak current mode.
14. The control circuit of claim 1, wherein a power switch in the power stage circuit is controlled to switch state when the power stage circuit is in the operating state, and wherein the dc input voltage obtained after filtering the ac input voltage is boosted to obtain a desired dc bus voltage.
15. The control circuit of claim 9, wherein the capacitance of the dc bus capacitor is set such that the power stage circuit is always inactive during a power frequency cycle when the magnitude of the ac input voltage is greater than a predetermined value.
16. A PFC circuit, comprising:
a power stage circuit, and,
the control circuit of any one of claims 1-15.
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| CN114337265B (en) * | 2021-12-03 | 2023-10-03 | 深圳科士达新能源有限公司 | Inverter system control method and device, electronic equipment and readable storage medium |
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