CN111651373A

CN111651373A - Message receiving method, device, terminal and storage medium

Info

Publication number: CN111651373A
Application number: CN202010414697.2A
Authority: CN
Inventors: 仲浩; 文继锋; 周强; 李响; 卢宇; 赵天恩; 顾浩; 周谷庆; 许宗光; 李彦
Original assignee: NR Electric Co Ltd; NR Engineering Co Ltd; State Grid Electric Power Research Institute
Current assignee: NR Electric Co Ltd; NR Engineering Co Ltd; State Grid Electric Power Research Institute
Priority date: 2020-05-15
Filing date: 2020-05-15
Publication date: 2020-09-11

Abstract

The embodiment of the application provides a message receiving method, a message receiving device, a terminal and a storage medium, wherein the method comprises the following steps: responding to the acquired message receiving instruction, and determining the characteristic information of the message to be received carried in the message receiving instruction; determining a first address of a circular buffer area matched with the message to be received in a preset mapping table according to the characteristic information; pushing the message to be received to a circular buffer area corresponding to the first address; when a scanning instruction sent by a target core processor is received, feeding the message to be received back to the target core processor; wherein the scan instruction is to instruct scanning of the circular buffer.

Description

Message receiving method, device, terminal and storage medium

Technical Field

The present application relates to a multi-core real-time control system network communication technology, and relates to, but is not limited to, a message receiving method, apparatus, terminal, and storage medium.

Background

With the development and application of multi-core processor technology, multi-core processors have been increasingly applied to power system control and protection devices. The advantage of parallel processing of the multi-core processor can enable a plurality of programs to run simultaneously, and greatly improves the running period of the protection and control programs. On the occasion with high requirement on the performance of the control protection host, the number of messages processed by each core processor in the multi-core real-time control system is different, some messages may be required to be received by a plurality of core processors, and some messages only have one core processor. The message quantity which some core processors need to process can be very large, but the requirement on the program running period is not high. The running period of some core processor programs may be as fast as 10 microseconds, and there is a demand for message processing within 10 microseconds, but the messages to be processed may be only specified messages. Under the condition of large message flow, the efficiency of reading and processing the message by each core processor is not high.

Disclosure of Invention

In order to solve the above technical problem, embodiments of the present application provide a message receiving method, an apparatus, a terminal, and a storage medium.

The embodiment of the application provides a message receiving method, which comprises the following steps:

responding to the acquired message receiving instruction, and determining the characteristic information of the message to be received carried in the message receiving instruction;

determining a first address of a circular buffer area matched with the message to be received in a preset mapping table according to the characteristic information;

pushing the message to be received to a circular buffer area corresponding to the first address;

when a scanning instruction sent by a target core processor is received, feeding the message to be received back to the target core processor; wherein the scan instruction is to instruct scanning of the circular buffer.

An embodiment of the present application provides a packet receiving apparatus, where the apparatus includes:

the first determining module is used for responding to the acquired message receiving instruction and determining the characteristic information of the message to be received carried in the message receiving instruction;

a second determining module, configured to determine, according to the feature information, a first address of a circular buffer that matches the packet to be received in a preset mapping table;

the pushing module is used for pushing the message to be received to a circular buffer area corresponding to the first address;

the feedback module is used for feeding back the message to be received to the target core processor when receiving a scanning instruction sent by the target core processor; wherein the scan instruction is to instruct scanning of the circular buffer.

The embodiment of the present application provides a message receiving terminal, where the message receiving terminal at least includes: a controller and a storage medium configured to store executable instructions, wherein:

the controller is configured to execute stored executable instructions configured to perform the message receiving method provided above.

An embodiment of the present application provides a computer-readable storage medium, where a computer-executable instruction is stored in the computer-readable storage medium, and the computer-executable instruction is configured to execute the above-mentioned message receiving method.

The embodiment of the application provides a message receiving method, a message receiving device, a terminal and a storage medium, wherein the address of a circular buffer area of a message to be received is determined by acquiring characteristic information of the message to be received, the message is pushed to the corresponding circular buffer area, and the message to be received is fed back to a target core processor when a scanning instruction which is sent by the target core processor and used for scanning the circular buffer area is received; therefore, the message to be received can be pushed to the corresponding circular buffer area according to the characteristic information of the message to be received, each core processor of the multi-core implementation control system only reads the message from the message circular buffer area needing to be received, and all messages in the memory space do not need to be traversed, so that the reading and processing efficiency of the message is improved.

Drawings

Fig. 1 is a schematic flowchart of a message receiving method according to an embodiment of the present application;

fig. 2 is a schematic flowchart of another process of a message receiving method according to an embodiment of the present application;

fig. 3 is a schematic diagram of a network message information configuration process according to an embodiment of the present application;

fig. 4 is an application scenario diagram of a message receiving method according to an embodiment of the present application;

fig. 5 is a schematic diagram of a composition structure of a message receiving apparatus according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a terminal according to an embodiment of the present application.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning by themselves. Thus, "module", "component" or "unit" may be used mixedly.

The terminal may be implemented in various forms. For example, the terminal described in the present application may include a mobile terminal such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable terminal, a smart band, a pedometer, and the like, and a fixed terminal such as a Digital TV, a desktop computer, and the like.

The following description will be given taking a mobile terminal as an example, and it will be understood by those skilled in the art that the configuration according to the embodiment of the present application can be applied to a fixed type terminal in addition to elements particularly used for mobile purposes.

In order to facilitate understanding of the technical solutions of the embodiments of the present application, the following description is made of related art of the embodiments of the present application.

The extra-high voltage direct current transmission control protection system is composed of various hosts which realize different functions, and communication between the hosts can be realized through Ethernet messages. Some electrical quantities required by the control protection of the power system are collected by Input/Output (IO) devices, the communication between the host and the IO devices also adopts an ethernet message mode, and the ethernet message is widely applied to a direct-current power transmission control protection system. With the development and application of multi-core processor technology, multi-core processors have been increasingly applied to power system control and protection devices. The advantage of parallel processing of the multi-core processor can enable a plurality of programs to run simultaneously, and greatly improves the running period of the protection and control programs.

In the processor message receiving method of the multi-core real-time control system in the related art, generally, a certain core processor directly distributes a message to be processed to each core processor, or each core processor reads a message from a message receiving buffer area and sorts the message required by the core processor. Under the condition of large message flow, the message processing efficiency of each core processor is not high.

A network message Processing method for balancing loads among multi-CPU core processors, which fully utilizes the resources of a Central Processing Unit (CPU) and can realize automatic balancing, is provided in the related technology. The patent needs to set a CPU for receiving messages and then distributing the messages to other cores, the receiving speed of the core processor directly influences the speed of the other core processors for receiving the messages, and the other core processors cannot obtain the messages at the first time. And the message processing capacity of the whole multi-core real-time control system is limited under the influence of the processing capacity of the core processor.

According to the embodiment of the application, each core processor of the multi-core processor can only receive the message required by the multi-core processor, each core processor can efficiently receive and process the message required by the core processor, and meanwhile, the message processing of one core processor is not easily influenced by the message flow of other core processors.

So that the manner in which the features and aspects of the present application can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.

Fig. 1 is a schematic flow chart of the message receiving method according to the embodiment of the present application, and the following steps are described with reference to fig. 1:

step S101: and responding to the acquired message receiving instruction, and determining the characteristic information of the message to be received carried in the message receiving instruction.

Here, the embodiments of the present application are applied to a power system, in particular, a multi-core real-time control system. The characteristic information of the message includes information such as a message type, a destination geographic Address (MAC Address), and an optical port number, but is not limited to the above-mentioned message characteristic information. The message characteristic information may be used to distinguish the categories of the messages. The extra-high voltage direct current transmission control protection system is composed of various hosts which realize different functions, and communication between the hosts can be realized through Ethernet messages. Some electrical quantities required by the control protection of the power system are collected by the IO device, the communication between the host and the IO device also adopts an Ethernet message mode, and the Ethernet message is widely applied to the direct-current transmission control protection system. When the host may send a message to obtain the electrical quantity to the IO device. And the IO device in the multi-core real-time control system acquires the message receiving instruction and responds.

Step S102: and determining a first address of a circular buffer zone matched with the message to be received in a preset mapping table according to the characteristic information.

Here, the preset mapping table stores the correspondence between the feature information of the different types of messages and the first addresses of the storage circular buffers corresponding to the different types of messages. A circular buffer (also called a ring buffer) is a fixed size buffer that works as if the memory is continuous and circular. When the memory space is allocated and used, the original data does not need to be cleaned up again, and only a head/tail pointer is adjusted. In some possible implementations, a circular buffer is used to store message data.

Step S103: and pushing the message to be received to a circular buffer area corresponding to the first address.

Here, according to the first address of the circular buffer, the circular buffer corresponding to the first address may be determined in the memory space of each core processor in the multi-core real-time control system. The multi-core real-time control system allocates a sharable network message configuration memory space for each core processor of the multi-core processor, and each core processor can configure network message characteristic information in the memory space. And determining a circular buffer area corresponding to the message according to the characteristic information of the message, and pushing the message to the circular buffer area corresponding to the address through a high-speed bus.

Step S104: and when receiving a scanning instruction sent by a target core processor, feeding back the message to be received to the target core processor.

Here, the scan instruction is to instruct scanning of the circular buffer. And the target core processor is a core processor which can read and process the message to be received in the multi-core real-time control system. The target core processor scans a circular buffer area of a message which needs to be received by the core processor regularly, for example, every 5 seconds, when the message is received, the message is pushed to the corresponding circular buffer area, so that when the target core processor scans the circular buffer area, the message can be acquired, namely the message which needs to be received by the target core processor is acquired, and the message which needs to be acquired is not acquired until other applications send feedback information of the message. When a scanning instruction of the circular buffer area sent by the target core processor is received, the message stored in the circular buffer area can be fed back to the target core processor, so that the target core processor reads and processes the message.

The embodiment of the application provides a message receiving method, a message receiving device, a terminal and a storage medium, wherein the address of a circular buffer area of a message to be received is determined by acquiring characteristic information of the message to be received, the message is pushed to the corresponding circular buffer area, and the message to be received is fed back to a target core processor when a scanning instruction which is sent by the target core processor and used for scanning the circular buffer area is received; therefore, the message to be received can be pushed to the corresponding circular buffer area according to the characteristic information of the message, each processor of the multi-core processor only reads the message from the message circular buffer area needing to be received, and all messages in the memory space do not need to be traversed, so that the reading and processing efficiency of the message is improved.

On the basis of the embodiment shown in fig. 1, in order to determine the address of the circular buffer of the packet to be received, before responding to the acquired packet receiving instruction, a preset mapping table may be established by the following steps to perform a query in the mapping table, and determine the address of the circular buffer of the packet to be received, which includes the following steps:

the method comprises the following steps: determining the characteristic information of each category of messages in the newspaper library; wherein, the newspaper library comprises at least one type of newspaper.

Here, the packet library stores the types of packets that can be received by all core processors of the multi-core real-time control system. The characteristic information of the message includes information such as a message type, a destination MAC address, and an optical port number, but is not limited to the above message characteristic information.

Step two: and determining a second address of a circular buffer area of each category of message according to the characteristic information of each category of message so as to create the preset mapping table.

Here, the preset mapping table is used to represent a correspondence between feature information of each category packet and an address of a circular buffer storing the category packet.

The network message transmitting and receiving controller in the multi-core real-time control system is configured with the characteristic information of each type of message and a circular buffer area for storing each type of message. Because the characteristic information of different types of messages is different and the addresses of the circular buffer areas of different types of messages are also different, the address of the circular buffer area of each type of message can be determined according to the characteristic information of each type of message, and the characteristic information of each type of message and the address of the corresponding circular buffer area of the message are written into a message receiving information list of the network message transceiver controller to establish a preset mapping table.

Therefore, a mapping table of the corresponding relation between the characteristic information of each type of message and the address of the circular buffer area storing the same type of message can be established, so that the address of the circular buffer area of the message to be received can be quickly determined according to the mapping table.

In some embodiments, in the multi-core real-time control system, a core processor may be determined as a proxy core processor, and a message to be received is preprocessed before a message receiving instruction is received. The proxy core processor may be determined by the following process.

Step S1001: at least two core processors capable of receiving the message are determined.

Here, the multi-core real-time control system includes at least two core processors. The multi-core processor can process a plurality of programs in parallel, and can improve the running period of the protection and control programs. In the multi-core real-time control system, the number of messages processed by each core processor is different, and the classes of the messages to be processed by each core processor are possibly repeated.

Step S1002: and determining the configuration time length required by each core processor for configuring the characteristic information capable of receiving the message in the at least two core processors.

When the multi-core real-time control system is initialized, a plurality of core processors in the multi-core real-time control system are initialized at the same time, and in the program initialization stage, feature information capable of receiving a message needs to be configured for each core processor. Because the number of the messages which can be received by each core processor is different, the configuration time for configuring the message characteristic information for each core processor is also different. And after the message characteristic information configuration of all the core processors is completed, counting the time length of the message characteristic information configuration of each core processor.

Step S1003: and determining the core processor with the longest configuration time as the proxy core processor.

And comparing the time lengths of the message characteristic information which can be received by all the core processors in configuration, and determining the core processor with the longest configuration time length as a proxy core processor. And reselecting the proxy core processor in the multi-core processor each time the program initialization is carried out on the multi-core real-time control system.

Step S1004: and determining a second address of the circular buffer area of each type of message by adopting the proxy core processor according to the characteristic information of each type of message.

Here, each type of packet refers to that the packet is classified into different types according to different destination MAC addresses of the packet, packet types, or data types carried in the packet. The proxy core processor is used for counting the configuration information of the messages which can be received by all the core processors in the multi-core real-time control system. The configuration information of the message includes: characteristic information of the message and the address of a circular buffer where the message is stored. By adopting the agent core processor, the characteristic information of the message which can be received by each core processor in the multi-core real-time control system can be read, and the message characteristic information which can be received by each core processor is counted according to the time sequence of the message characteristic information configured by each core processor and the sequence from short to long. If repeated message characteristic information exists, namely two or more core processors receive the same message, the proxy core processor only counts the characteristic information of the same message once. And the proxy core processor obtains the categories of the messages which can be received by all the core processors according to the obtained characteristic information of each category of messages, and stores all the categories of the messages into a report library.

For example, taking a control system with a processor as a quad core as an example, the configuration durations of the packet feature information configured by the core processor 1 to the core processor 4 are sorted from short to long as: the core processor 1 sequentially reaches the core processor 4, the proxy core processor respectively reads the message characteristic information which can be processed by the core processor 1 to the core processor 4 from the memory space in the multi-core control system, and sequentially summarizes the message characteristic information according to the sequence from the core processor 1 to the core processor 4. If the core processor 1 receives the message A, and the core processor 2 and the core processor 3 also receive the message A, the proxy core processor only records the message characteristic information of the message A once.

And after the proxy core processor counts the message types which can be processed by all the core processors, configuring a circular buffer area for storing the corresponding type message for each type message. Therefore, the second address of the circular buffer of each category of message can be determined according to the characteristic information of each category of message.

Therefore, the proxy core processor can be determined in the multi-core real-time control system, the message types which can be received by all the core processors in the multi-core real-time control system are collected by the proxy core processor, the address of the circular buffer area for storing the message of each message type is determined, and the corresponding relation between each message type and the address of the circular buffer area for storing the message of the type can be established.

In some embodiments, a sharable memory space needs to be allocated for each core processor in the multi-core real-time control system to store the received message data, and the process is as follows:

the method comprises the following steps: and determining the message types which can be received by each core processor.

Here, in the multi-core real-time control system, the number of messages that each core processor can receive and process is different, some messages may be all received by a plurality of core processors, or some messages may only have one core processor to receive. In addition, the types and the number of messages to be transmitted are set when the host communicates with the host and when the host communicates with the IO device in the electric power multi-core real-time control system. The message types which can be received and processed by each core processor can be distributed to each core processor according to the application scene of the electric power multi-core real-time control system and the message types in the report library of the electric power multi-core real-time control system.

Step two: and determining the memory space of each core processor for storing message data according to the message types which can be received by each core processor.

Here, in the multi-core real-time control system, the types of messages that can be received and processed by each core processor are different, and a memory space is allocated to each core processor at the code loading stage according to the types of messages that can be received by each core processor, and the memory space is a sharable memory space for storing message data. In some embodiments, the memory space of each core processor may be divided into two parts, one part is used for storing the characteristic information of the message that can be received by the core processor, and the other part is used for storing the message that can be received by the core processor.

In some implementable embodiments, the memory space used by each of the core processors to store message data may also be determined in the following manner.

And determining the memory space of each core processor for storing message data according to the data volume of the message which can be received by each core processor.

Here, since the data length of each type of packet is different, the data amount of the packet that can be received by each core processor is also different, and the space occupied by the packet data is also different. Therefore, according to the data volume of the message which can be received by each core processor, the memory space matched with the data volume of the message which can be received can be distributed to each core processor. This memory space is a sharable memory space for storing message data. In some embodiments, the memory space of each core processor may be divided into two parts, one part is used for storing the characteristic information of the message that can be received by the core processor, and the other part is used for storing the message that can be received by the core processor.

Therefore, the memory space matched with the message type or the message data volume can be distributed to each core processor in the multi-core real-time control system, and the waste of the memory is avoided.

In some embodiments, in the step S1004, "determining the second address of the circular buffer of each type of packet according to the characteristic information of each type of packet by using the proxy core processor" may be implemented by steps S201 to S203, as shown in fig. 2, the following steps are described as follows:

step S201: and reading the characteristic information of the message which can be received by each core processor in the memory space of each core processor by adopting the proxy core processor.

The proxy core processor is used for counting configuration information of messages which can be received by all core processors in the multi-core real-time control system, wherein the configuration information of the messages comprises characteristic information of the messages and addresses of circular buffer areas for storing the messages. Therefore, the proxy core processors can be adopted to read the characteristic information of the messages which can be received by each core processor in the memory space of each core processor in the multi-core real-time control system, and count the message characteristic information which can be received by each core processor according to the time length sequence of the message characteristic information configured by each core processor and the sequence from short to long.

Step S202: and determining the type of the message which can be received by the corresponding core processor according to the characteristic information of the message which can be received by each core processor.

After reading the characteristic information of the message which can be received by each core processor, the proxy core processor determines the type of the message which can be received by the corresponding core processor according to parameters such as a destination MAC address or a message type in the message characteristic information which can be received by each core processor.

In some embodiments, after the proxy core processor determines the types of the messages that can be received by each core processor, the types of the messages that can be received by each core processor are counted in sequence according to the time length sequence of the configuration message characteristic information of each core processor, such as the sequence from short to long.

If repeated message types exist, namely two or more core processors receive the same message, the proxy core processor only counts the characteristic information of the same message once. The proxy core processor obtains the types of the messages which can be received by all the core processors according to the obtained types of the messages which can be received by each core processor, and stores the messages of all the types into a message library.

Step S203: and determining a second address of a circular buffer area for storing each class of messages according to a preset message arrangement sequence.

Here, the preset message arrangement order may be determined according to a type of the message or a destination MAC address of the message feature information.

In some implementation manners, the preset message arrangement order may be an order of message categories that can be processed by different core processors in the multi-core real-time control system. In some embodiments, each core processor is sequenced according to the characteristic time length of the message characteristic information configured by each core processor, the message characteristic information which can be received by each core processor is counted in sequence, the message types which can be received by each core processor are counted and sequenced, and for repeated message characteristic information among different core processors, the message characteristic information is counted only once, that is, the message types are counted only once, so that the arrangement sequence of the messages can be obtained. Such as: the configuration time length of the message feature information configured by the core processor 1, the core processor 2 and the core processor 3 is as follows from short to long respectively: the core processor 2, the core processor 1 and the core processor 3 sequentially count the characteristic information that the core processor 2, the core processor 1 and the core processor 3 can receive the messages, the core processor 2 correspondingly receives the characteristic information of the messages A and D, the core processor 1 correspondingly receives the characteristic information of the messages A and C, the core processor 3 correspondingly receives the characteristic information of the messages A, B and C, and the obtained message arrangement sequence is as follows: ADCB. And according to the arrangement sequence of the messages, configuring a corresponding circular buffer area for each type of message in sequence, and reading the address of the circular buffer area, namely the second address of the circular buffer area.

Each circular buffer area is composed of a plurality of data blocks, the number of the data blocks can be set according to the specific application occasion of the system, and the size of each data block can be set according to the maximum length of the message to be received.

Therefore, the proxy core processor can be adopted to collect the message types which can be received by all the core processors in the multi-core real-time control system, determine the addresses of the circular buffer areas for storing the messages of each message type, and establish the corresponding relation between each message type and the addresses of the circular buffer areas for storing the messages of each message type.

In some embodiments, after the step S203, the method further comprises the steps of:

step S204: and establishing a corresponding relation between each core processor and a second address of a circular buffer area for storing the same type of message according to the characteristic information of each type of message.

Here, since the types of messages that can be received by each core processor are different, the characteristic information of each type of message is different. The messages stored in each circular buffer area are different, and the corresponding message characteristic information is also different. According to the characteristic information of each type of message, the core processors receiving the same type of message can be determined, and meanwhile, the second addresses of the circular buffer areas storing the same type of message can be determined, so that the corresponding relation between each core processor and the second addresses of the circular buffer areas storing the same type of message can be established.

Step S205: and writing the second address of each category message into the memory space of the core processor capable of receiving the category message according to the corresponding relation.

Here, according to the correspondence between each core processor and the second address of the circular buffer storing the same type of packet, the core processor corresponding to the second address of the same type of packet can be determined, and further, the memory space corresponding to the core processor receiving the same type of packet is determined, and then the second address of each type of packet is written into the memory space of the core processor capable of receiving the type of packet.

Therefore, the configuration information of each type of message can be stored in the memory space of each core processor, so that the type of the message to be received can be quickly determined.

In some embodiments, after the step S1004 "determining, by using the proxy core processor, the second address of the circular buffer of each class packet according to the characteristic information of each class packet", the method further includes:

and reporting the second address of the circular buffer area of each type of message and the mapping table to a network message transceiving controller, so that the network message transceiving controller pushes the message to be received to a matched circular buffer area when receiving a message receiving instruction.

Here, the network messaging controller may be implemented by a field programmable gate array. And taking the message types which can be received by all the core processors and the second addresses of the circular buffer areas of the messages of each type, which are counted by the proxy core processor, as the message receiving configuration information of all the core processors, and configuring the message configuration information into a message receiving information list of the network message receiving and sending controller.

The network message receiving and sending controller is used for receiving the message and pushing the received message to the corresponding circular buffer area. When a message receiving instruction is received, the network message receiving and transmitting controller obtains the characteristic information of the message, determines the address of a circular buffer area corresponding to the message in a message receiving information list, namely a preset mapping table, and pushes the message to the circular buffer area matched with the message through a high-speed bus.

Therefore, the network message receiving and transmitting controller can identify the type of the message according to the received message characteristic information, and push the message to the message circular buffer zone of the matched address, so that the message receiving efficiency is improved.

The embodiment of the application provides a message receiving method, a proxy core processor is used for collecting characteristic information of messages to be received of all core processors, a circular buffer area is uniformly distributed to each type of messages, message configuration information and addresses of the circular buffer areas corresponding to the messages are configured to a network message receiving and sending controller, the network message receiving controller pushes the received messages to the circular buffer areas corresponding to the message characteristic information, each core processor only scans the message buffer areas needing to be received by the core processors to receive the messages, each core processor of a multi-core real-time control system only receives the messages needing to be processed by the core processor, and message processing efficiency is improved.

Therefore, the application provides a message receiving method, which comprises the following specific steps:

the method comprises the following steps: the multi-core real-time control system allocates memory space for each core processor of the multi-core processor.

Here, the memory space configures a memory space for the shared network information corresponding to each core processor. Each core processor can configure network message characteristic information in the memory space, and configure a plurality of groups of circular buffer areas in the memory space for the multi-core processor, each circular buffer area is composed of a plurality of data blocks, the number of the data blocks can be set according to the specific application occasion of the system, and the size of each data block can be set according to the maximum length of the message to be received.

Step two: in the program initialization stage of the multi-core real-time control system, each core processor writes characteristic information of a message required to be received into a memory space corresponding to each core processor.

Here, the characteristic information of the packet includes a packet type, a MAC address, and an optical port number, but is not limited to the above-mentioned packet characteristic information.

Step three: and the agent core processor counts the message characteristic information of all the core processors and the corresponding circular buffer area addresses.

Here, the proxy core processor is a core processor which is initialized by the multi-core real-time control system processor. The agent core processor counts the message configuration information of all the core processors, configures a circular buffer area address for each type of message, and only allocates the circular buffer area address once for the characteristic information of the same message. And the proxy core processor writes the allocated addresses of the circular buffer areas into the memory space of each core processor.

Therefore, the same type of messages can be received among the core processors, and the messages can be shared among the core processors while the customization is carried out.

Step four: and the proxy core processor configures the collected received message configuration information of all the core processors to the network message receiving and transmitting controller.

Here, the received packet configuration information of all the core processors includes feature information of the packet and an address of a circular buffer of the packet. The agent core processor configures the message configuration information which needs to be received by all the core processors to a network message receiving and transmitting controller realized by a programmable device.

Step five: when receiving the message, the network message receiving and sending controller sends the message to the memory space of the designated address.

Here, the network messaging controller will push the message to the memory space of the designated address through a high-speed bus including but not limited to a high-speed serial component interconnect express (PCIE) bus according to the message information. Each core processor of the multi-core processor responsible for message processing can periodically scan the address space of the message circular buffer area which needs to be received by the core processor, and extract and further process the message from the buffer area.

Therefore, the customization of the message received by each core processor in the multi-core real-time control system is realized, each core processor only processes the message required to be received, the message processing efficiency of each core processor is improved, the message receiving of each core processor is not influenced by the messages of other core processors, and the stability of the whole multi-core real-time control system is greatly improved.

The embodiment of the application provides a message receiving method. Fig. 3 is a schematic diagram of a network packet information configuration process according to an embodiment of the present application, and the network packet information configuration process is described with reference to fig. 3:

step S301: and configuring the characteristic information of the message to be received for each core processor in the process of initializing the processor program.

Here, taking a control system with four cores as an example, in a code loading phase, each core processor of the multi-core processor allocates one memory space. In the initialization stage, each core processor writes characteristic information of a message to be received, including message characteristic information such as a message type, a destination MAC address and an optical port number, into a memory space allocated to each core processor.

In some implementation manners, the multi-core real-time control system allocates a sharable network packet configuration memory space for each core processor of the multi-core processor, and each core processor can configure network packet feature information in the memory space.

As shown in fig. 3, the four-core control system includes a core processor 0, a core processor 1, a core processor 2, and a core processor 3, where 31 is a memory space of the core processor 0, 32 is a memory space of the core processor 1, 33 is a memory space of the core processor 2, and 34 is a memory space of the core processor 3. Respectively storing the characteristic information of the message to be received by each core processor in each memory space, such as storing the characteristic information of the message 1, the characteristic information of the message 2 and the characteristic information of the message 3 in 31; storing message 1 characteristic information, message 3 characteristic information and message 4 characteristic information in 32; storing message 1 characteristic information, message 4 characteristic information and message 5 characteristic information in 33; message 1, message 3 and message 6 characteristic information are stored at 34.

Step S302: and counting and sequencing the message characteristic information of all the core processors by adopting the proxy core processor.

Here, the proxy core processor is a core processor whose initialization is completed at the last of the initialization phase of the multi-core real-time control system, and as shown in fig. 3, the core processor 2 in fig. 3 may be set as the proxy core processor. The agent core processor can count the message information to be received by each core processor from the core processor 0 to the network information configuration memory space corresponding to the core processor 3, then sort the message information according to the registration sequence from the core processor 0 to the core processor 3, and gather the message characteristic information in sequence. If two or more core processors receive the same message, namely a repeated message, if the core processor 0 receives the message 1, and the core processor 1, the core processor 2 and the core processor 3 also all receive the message 1, the proxy core processor only records the message characteristic information of the message 1 once.

In some realizable embodiments, the proxy core processor may count the packet configuration information of all the core processors, configure an address of a circular buffer for each packet, and allocate the address of the circular buffer only once for the configuration information of the same packet. And the proxy core processor writes the distributed addresses of the circular buffer areas into the network configuration information memory space of each core processor.

Step S303: and configuring addresses of a circular buffer area for all messages by adopting a proxy core processor.

Here, the proxy core processor sequentially configures a circular buffer area for the message to be received according to the registration sequence from the core processor 0 to the core processor 3, and records the address of the circular buffer area. The multi-core processor real-time control system is characterized in that a plurality of groups of circular buffer areas are configured in a memory space for the multi-core processor, each circular buffer area is composed of a plurality of data blocks, the number of the data blocks can be set according to the specific application occasion of the system, and the size of each data block can be set according to the maximum length of a message to be received.

Step S304: and adopting the proxy core processors to write the address of the circular buffer area corresponding to the message of each core processor into the memory space of the corresponding core processor.

Here, the proxy core processor is adopted to inform each core processor of the push address of the message to be received, namely the message circular buffer area address of each core processor, through the memory space.

Step S305: and configuring the configuration information of all messages to a network message receiving and transmitting controller by adopting the agent core processor.

Here, the network packet transceiver controller 35 may be implemented by a Field Programmable Gate Array (FPGA), but is not limited to the FPGA, and the proxy core processor configures configuration information of packets that all the core processors need to receive to the network packet transceiver controller implemented by a Programmable device, so that the network packet transceiver controller can classify the received packets according to the configured packet feature information and push the packets to a specified circular buffer.

And the proxy core processor configures the network message configuration information configured by all the core processors into a message receiving information list of the network message receiving and transmitting controller. Therefore, when receiving the message, the network message receiving and transmitting controller can search the address of the circular buffer zone corresponding to the message in the information list according to the message characteristic information and push the frame message to the circular buffer zone.

Therefore, the customization of the message received by each core processor of the multi-core controller is realized, and each core processor only processes the message required to be received, so that the message processing efficiency of each core processor is improved; the same type of messages can be received among the core processors, and the sharing among the message core processors can be realized while customizing; the message receiving of each core processor is not influenced by the messages of other core processors, so that the stability of the whole multi-core processor control system is greatly improved.

After network message information is configured, each core processor periodically scans a circular buffer area pushed by a message which needs to be received by the core processor, and takes out the message from the circular buffer area.

Fig. 4 is an application scenario diagram of a message receiving method according to an embodiment of the present application, and as shown in fig. 4, each message circular buffer has a plurality of data blocks, and the size of each data block can be configured according to the size of a message to be received. As shown, the core processor 0 may receive the message 1, the message 2, and the message 3, and then read the message 1 in the message 1 buffer 41, read the message 2 in the message 2 buffer 42, and read the message 3 in the message 2 buffer 43. The core processor 1 may receive the message 1, the message 3, and the message 4, and then read the message 1 in the message 1 buffer 31, read the message 3 in the message 3 buffer 43, and read the message 4 in the message 4 buffer 44. The core processor 2 may receive the message 1, the message 4, and the message 5, and then read the message 1 in the message 1 buffer 41, read the message 4 in the message 4 buffer 44, and read the message 5 in the message 5 buffer 45. The core processor 3 may receive message 1, message 3, and message 6, and then read message 1 in the message 1 buffer 41, read message 3 in the message 3 buffer 43, and read message 6 in the message 6 buffer 46.

In some realizable embodiments, when receiving a message, the network message transceiving controller pushes the message to a memory space of a designated address through a high-speed bus according to message information, and each core processor responsible for message processing periodically scans an address space of a message circular buffer area which the core processor needs to receive, extracts the message from the buffer area, and then further processes the message.

Therefore, each core processor only processes the message required to be received, and the message processing efficiency of each core processor is improved; and the message receiving of each core processor is not influenced by the messages of other core processors, so that the stability of the whole multi-core processor control system is greatly improved.

An embodiment of the present application provides a message receiving apparatus, and fig. 5 is a schematic diagram of a composition structure of the message receiving apparatus according to the embodiment of the present application. As shown in fig. 5, the message receiving apparatus 500 includes: a first determining module 501, a second determining module 502, a pushing module 503, and a feedback module 504, wherein:

the first determining module 501 is configured to determine, in response to an obtained message receiving instruction, feature information of a message to be received, which is carried in the message receiving instruction;

the second determining module 502 is configured to determine, according to the feature information, a first address of a circular buffer matched with the packet to be received in a preset mapping table;

the pushing module 503 is configured to push the packet to be received to a circular buffer corresponding to the first address;

the feedback module 504 is configured to feed back the message to be received to a target core processor when receiving a scan instruction sent by the target core processor; wherein the scan instruction is to instruct scanning of the circular buffer.

In the above apparatus, the apparatus further comprises:

the third determining module is used for determining the characteristic information of each category of messages in the message library; wherein, the newspaper library comprises at least one type of newspaper;

a fourth determining module, configured to determine, according to the feature information of each category packet, a second address of a circular buffer of each category packet to create the preset mapping table; the preset mapping table is used for representing the corresponding relation between the characteristic information of each category message and the address of the circular buffer area for storing the category message.

In the above apparatus, the apparatus further comprises:

the fifth determining module is used for determining at least two core processors capable of receiving the messages;

a sixth determining module, configured to determine, in the at least two core processors, a configuration time required by each core processor to configure feature information of a message that can be received by the core processor;

a seventh determining module, configured to determine the core processor with the longest configuration time as the proxy core processor;

and the eighth determining module is used for determining the second address of the circular buffer area of each type of message according to the characteristic information of each type of message by adopting the proxy core processor.

In the above apparatus, the apparatus further comprises:

a ninth determining module, configured to determine a packet type that each of the core processors can receive;

and the tenth determining module is used for determining the memory space of each core processor for storing message data according to the message types which can be received by each core processor.

In the apparatus, the tenth determining module is further configured to determine, according to a data amount of a packet that can be received by each of the core processors, a memory space in which each of the core processors stores packet data.

In the above apparatus, the tenth determining module includes:

and the reading submodule is used for reading the characteristic information of the message which can be received by each core processor in the memory space of each core processor by adopting the proxy core processor.

The first determining submodule is used for determining the types of the messages which can be received by the corresponding core processors according to the characteristic information of the messages which can be received by each core processor;

and the second determining submodule is used for determining a second address of the circular buffer area for storing each class of messages according to the preset message arrangement sequence.

In the above apparatus, the tenth determining module further includes:

the establishing submodule is used for establishing a corresponding relation between each core processor and a second address of a circular buffer area for storing the same type of messages according to the characteristic information of each type of messages;

and the writing sub-module is used for writing the second address of each category message into the memory space of the core processor capable of receiving the category message according to the corresponding relation.

In the above apparatus, the apparatus further comprises:

and the reporting module is used for reporting the second address of the circular buffer area of each type of message and the mapping table to a network message transceiving controller so that the network message transceiving controller pushes the message to be received to the matched circular buffer area when receiving a message receiving instruction.

The embodiment of the present application further provides a message receiving apparatus, where the apparatus includes modules, and sub-modules and units included in the modules, and may be implemented by a processor in a terminal; of course, the implementation can also be realized through a specific logic circuit; in implementation, the processor may be a Central Processing Unit (CPU), a Microprocessor (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like.

Correspondingly, an embodiment of the present application provides a terminal, fig. 6 is a schematic view of a composition structure of the terminal according to the embodiment of the present application, and as shown in fig. 6, the terminal 600 at least includes: a controller 601 and a storage medium 602 configured to store executable instructions, wherein:

the controller 601 is configured to execute stored executable instructions for implementing the provided message receiving method.

It should be noted that the above description of the terminal embodiment is similar to the description of the method embodiment, and has similar beneficial effects to the method embodiment. For technical details not disclosed in the embodiments of the terminal of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.

Correspondingly, an embodiment of the present application provides a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and the computer-executable instructions are configured to execute the message receiving method provided in other embodiments of the present application.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, etc.) to execute the method described in the embodiments of the present application.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, terminals (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. A method for receiving a message, the method comprising:

2. The method according to claim 1, wherein before determining, according to the characteristic information and in a preset mapping table, a first address of a circular buffer matching the packet to be received, the method further comprises:

determining the characteristic information of each category of messages in the newspaper library; wherein, the newspaper library comprises at least one type of newspaper;

determining a second address of a circular buffer area of each category of message according to the characteristic information of each category of message to create the preset mapping table; the preset mapping table is used for representing the corresponding relation between the characteristic information of each category message and the address of the circular buffer area for storing the category message.

3. The method according to claim 2, wherein before the determining, in response to the obtained message receiving instruction, the feature information of the message to be received carried in the message receiving instruction, the method further comprises:

determining at least two core processors capable of receiving messages;

determining the configuration time required by each core processor to configure the characteristic information capable of receiving the message in the at least two core processors;

determining a core processor with the longest configuration time as an agent core processor;

and determining a second address of the circular buffer area of each type of message by adopting the proxy core processor according to the characteristic information of each type of message.

4. The method of claim 1, further comprising:

determining the message types which can be received by each core processor;

and determining the memory space of each core processor for storing message data according to the message types which can be received by each core processor.

5. The method of claim 4, wherein the determining a memory space for each of the core processors to store message data comprises:

6. The method according to any one of claims 3 to 5, wherein the determining, with the proxy core processor, the second address of the circular buffer for each class of packet according to the characteristic information of each class of packet comprises:

adopting the proxy core processors to read the characteristic information of the message which can be received by each core processor in the memory space of each core processor;

determining the type of the message which can be received by the corresponding core processor according to the characteristic information of the message which can be received by each core processor;

and determining a second address of a circular buffer area for storing each class of messages according to a preset message arrangement sequence.

7. The method of claim 6, wherein after determining the second address of the circular buffer for storing each class of packets according to the predetermined packet ordering, the method further comprises:

establishing a corresponding relation between each core processor and a second address of a circular buffer area for storing the same type of message according to the characteristic information of each type of message;

and writing the second address of each category message into the memory space of the core processor capable of receiving the category message according to the corresponding relation.

8. The method of claim 2, wherein after determining the second address of the circular buffer of each packet type according to the characteristic information of each packet type to create the preset mapping table, the method further comprises:

9. A message receiving apparatus, the apparatus comprising:

and the feedback module is used for feeding back the message to be received to the target core processor when receiving a scanning instruction which is sent by the target core processor and used for scanning the circular buffer area.

10. A message receiving terminal, characterized in that the terminal at least comprises: a controller and a storage medium configured to store executable instructions, wherein:

the controller is configured to execute stored executable instructions configured to perform the message receiving method as provided in any of the preceding claims 1 to 8.

11. A computer-readable storage medium having computer-executable instructions stored thereon, the computer-executable instructions being configured to perform the message receiving method as provided in any one of claims 1 to 8.