CN111650425A - Alternating current zero-crossing detection circuit and chip - Google Patents

Abstract

The invention discloses an alternating current zero crossing point detection circuit and a chip, wherein the alternating current zero crossing point detection circuit comprises: the power taking and alternating current shaping unit is used for generating square waves with the same frequency and phase based on alternating current; the edge pulse generating unit is electrically connected with the power taking and alternating current shaping unit and is used for generating edge pulses at the alternating current zero crossing points based on the square waves; a zero-crossing pulse generating unit electrically connected to the edge pulse generating unit for generating a zero-crossing pulse based on the edge pulse. The invention can simultaneously detect the zero crossing point of the rising edge and the zero crossing point of the falling edge of the alternating current, and improves the precision of detecting the zero crossing point.

Description

Alternating current zero-crossing detection circuit and chip

Technical Field

The invention relates to the technical field of alternating current zero crossing point detection, in particular to an alternating current zero crossing point detection circuit and a chip.

Background

The alternating current zero crossing point detection circuit is a common circuit in the fields of silicon controlled control circuits, high-power equipment or electrical appliance access, power carrier communication, illumination control and the like. In these fields, accurate detection of the voltage zero crossing point of the alternating current is required, a zero-crossing pulse or a level signal is generated at the zero crossing point as a reference signal for system control, or relevant information such as an alternating current period, voltage fluctuation, a phase and the like of the alternating current is acquired based on a zero-crossing detection signal.

The current alternating current zero crossing point detection circuits are all zero crossing point detection circuits based on discrete components, the circuit structure is complex, and zero crossing point signals can be generated only at the rising edge or the falling edge of alternating current, such as patent numbers: CN103063904A and CN 102508014A. However, the system usually needs the zero-crossing signals of the rising edge and the falling edge of the alternating current, and one way is that the system obtains the virtual zero-crossing detection signal of the other edge in a calculation mode according to the zero-crossing detection signal of a single edge. However, the virtually obtained zero-crossing detection signal of the other edge does not actually detect another zero-crossing point, so that information carried by a part of the zero-crossing points, such as zero-crossing point jitter caused by voltage fluctuation, is lost. Another approach is to use two identical circuits to detect the zero-crossing of the rising and falling edges, respectively, but the cost, power consumption and complexity of the system are doubled.

In addition, the zero crossing point detection circuit based on discrete components has a large number of peripheral devices, and because more current control devices such as diodes and triodes are adopted, the power consumption of the self-loss is large, and about 50-100mW is generally required. Another problem caused by many peripheral devices is that the detection accuracy is also impaired, and the error between the detected zero-crossing point and the actual zero-crossing point is usually over 20 us.

Therefore, how to design a high-precision zero-crossing detection circuit capable of simultaneously detecting zero-crossing points of a rising edge and a falling edge is an urgent technical problem to be solved in the industry.

Disclosure of Invention

In order to solve the technical problem that zero crossing points of rising edges and falling edges are detected inaccurately simultaneously in the prior art, the invention provides an alternating current zero crossing point detection circuit and a chip.

The technical scheme adopted by the invention is to firstly provide an alternating current zero crossing detection circuit, which comprises: the power taking and alternating current shaping unit is used for generating square waves with the same frequency and phase based on alternating current; the edge pulse generating unit is electrically connected with the power taking and alternating current shaping unit and is used for generating edge pulses at the alternating current zero crossing points based on the square waves; a zero-crossing pulse generating unit electrically connected to the edge pulse generating unit for generating a zero-crossing pulse based on the edge pulse.

In one embodiment, the zero-crossing pulse generating unit includes: the pulse extension unit is electrically connected with the edge pulse generation unit, the bias circuit unit is electrically connected with the pulse extension unit, and the optocoupler driving unit is electrically connected with the bias circuit unit and the pulse extension unit.

In one embodiment, the zero-crossing pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8, resistors R2, R3 and R4, capacitors C2 and C3, NOT gates U2 and U3; the MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3 and R3 form a pulse extension unit; the MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2 and R4 form a bias circuit unit; MN4, MN5 and MN6 constitute an optocoupler drive unit.

In one embodiment, the pulse extension unit includes: the edge pulse circuit is electrically connected with the grid of MN7 and the grid of MN9, the drain of MN7 is electrically connected with the grid of MN8, the drain of MN7 is also electrically connected with one end of C2, the drain of MN9 is electrically connected with one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input terminal of U2, the output terminal of U2 is electrically connected to the input terminal of U3, and the output terminal of U3 is electrically connected to the gate of MP 6.

In one embodiment, the bias circuit unit includes: the source electrode of the MP, the source electrode of the MP and the source electrode of the MP are electrically connected, the drain electrode of the MP, the grid electrode of the MP are electrically connected, the grid electrode of the MP is electrically connected with the output end of the U, the drain electrode of the MP is electrically connected with the drain electrode of the MN, the drain electrode of the MP is electrically connected with the grid electrode of the MN, the drain electrode of the MN is electrically connected with the drain electrode of the MN, the source electrode of the MN is electrically connected with the grid electrode of the MN, the source electrode of the MN is also electrically connected with one end of the R, the other end.

In one embodiment, the optocoupler driving unit comprises a drain electrode of MN5 electrically connected to a gate electrode of MN5, a gate electrode of MN6, a drain electrode of MN4 and a drain electrode of MP4, a source electrode of MN5, a source electrode of MN6, a source electrode of MN4 and a source electrode of MN7 are electrically connected, a gate electrode of MN4 is electrically connected to an output end of U2, and a drain electrode of MN6 outputs the zero-crossing pulse.

In one embodiment, the power-taking and ac-shaping unit includes: the circuit comprises a resistor R1, diodes D1 and D2, a capacitor C1 and a comparator U1; one end of R1 is used for electrically connecting the alternating current, the other end of R1 is electrically connected with the non-inverting input end of U1, the non-inverting input end of U1 is also electrically connected with the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected with the power supply end of U1, the anode of D2, the grounding end of U1 and the inverting input end of U1 are electrically connected with each other and grounded, C1 is electrically connected between the power supply end and the grounding end of U1, and the output end of U1 outputs square waves with the same frequency and phase as the.

In one embodiment, the edge pulse generating unit includes: an INV, a delay unit and an XOR; INV is electrically connected to the output end of the U1, the output ends of the INV are electrically connected to the first input end of the XOR and the input end of the delay unit respectively, the output end of the delay unit is electrically connected to the second input end of the XOR, and the output end of the XOR outputs the edge pulse.

In one embodiment, R1 in the power-taking and ac-shaping unit is an external resistor, and C1 is an external capacitor.

In one embodiment, the optical coupler further comprises an external optical coupler, wherein an anode of the light emitting diode in the optical coupler is electrically connected to a power supply end of the U1, and a cathode of the light emitting diode is electrically connected to a drain of the MN 6.

The invention also provides a chip which adopts the alternating current zero-crossing detection circuit.

Compared with the prior art, the invention has at least the following advantages.

The square waves with the same frequency and the same phase as the alternating current are generated by the power taking and alternating current shaping unit, and the edge pulse is generated by the edge pulse generating circuit, so that the zero crossing point of the rising edge and the zero crossing point of the falling edge of the alternating current are detected simultaneously, and the precision of detecting the zero crossing point is improved. By arranging the zero-crossing pulse generating circuit, the width of the edge pulse is extended to generate the zero-crossing pulse with the required width, so that the width of the zero-crossing pulse is adjusted. Furthermore, the alternating current zero-crossing detection circuit is integrated in one chip, so that the complexity of a peripheral circuit is reduced, the application is simpler and more convenient, and the energy consumption is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.

FIG. 1 is a block diagram of an AC zero crossing detection circuit according to an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of the power-taking and AC shaping unit shown in FIG. 1;

FIG. 3 is a circuit diagram of the edge pulse generating unit in FIG. 1;

FIG. 4 is a circuit schematic diagram of the zero-crossing pulse generating unit of FIG. 1;

FIG. 5 is a schematic diagram of an application of a chip integrated with an AC zero crossing detection circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating a detection effect of detecting a zero-crossing point of an alternating current according to an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Thus, a feature indicated in this specification will serve to explain one of the features of one embodiment of the invention, and does not imply that every embodiment of the invention must have the stated feature. Further, it should be noted that this specification describes many features. Although some features may be combined to show a possible system design, these features may also be used in other combinations not explicitly described. Thus, the combinations illustrated are not intended to be limiting unless otherwise specified.

The principles and construction of the present invention will be described in detail below with reference to the drawings and examples.

As shown in fig. 1, the present invention provides an alternating current zero-crossing detection circuit for obtaining information of an alternating current zero-crossing. The alternating current zero crossing point detection circuit includes: the device comprises a power taking and alternating current shaping unit, an edge pulse generating unit and a zero-crossing pulse generating unit which are sequentially and electrically connected. The power taking and alternating current shaping unit is used for electrically connecting alternating current to be detected and generating square waves with the same frequency and phase based on the alternating current. The edge pulse generating unit is used for generating edge pulses at the zero crossing points of the alternating current based on square waves. The zero-crossing pulse generating unit is used for generating a zero-crossing pulse based on the edge pulse, and the zero-crossing pulse is information about the zero crossing point of the alternating current, which is required to be obtained through the technical scheme of the invention.

Compared with the traditional zero-crossing detection scheme based on discrete components, the technical scheme of the invention can simultaneously detect the zero-crossing point of the rising edge and the zero-crossing point of the falling edge of the alternating current (please refer to the detection effect schematic diagram of fig. 6), and has the advantages of simple circuit structure, low cost and high detection precision.

The following describes each part of the alternating current zero-crossing detection circuit of the present invention.

As shown in fig. 2, the power-taking and ac-shaping unit includes: the circuit comprises a resistor R1, diodes D1 and D2, a capacitor C1 and a comparator U1. One end of the R1 is used for being electrically connected with alternating current to be detected, and the other end of the R1 is electrically connected with the non-inverting input end of the U1. The non-inverting input terminal of the U1 is further electrically connected to the anode of the D1 and the cathode of the D2, the cathode of the D1 is electrically connected to the power supply terminal of the U1, the anode of the D2, the ground terminal of the U1, and the inverting input terminal of the U1 are electrically connected to each other and grounded, and the D1 and the D2 are ESD protection diodes of the input port, so that ESD protection of the port is realized, and half-wave rectification is realized. The C1 is electrically connected between the power supply terminal and the ground terminal of the U1, and the output terminal of the U1 outputs square waves with the same frequency and phase as the alternating current. R1 can be a series or parallel connection of multiple resistors. Preferably, D2 is a zener diode. The comparison threshold of U1 is set to 0V. When the input alternating current passes through zero, the level output by the output end of the comparator is turned over, so that the alternating current is shaped, and square wave output with the same frequency and phase as the input alternating current is generated. Since the comparison threshold of U1 is 0V, there is almost no delay between the zero-crossing pulse and the actual zero-crossing point, and thus extremely high detection accuracy is achieved.

As shown in fig. 3, the edge pulse generating unit is electrically connected to the power-taking and ac shaping unit, and is configured to receive the square wave and generate the edge pulse based on the square wave. The edge pulse generating unit includes: an INV, a delay unit and an XOR; INV is electrically connected to the output end of the U1, the output ends of the INV are electrically connected to the first input end of the XOR and the input end of the delay unit respectively, the output end of the delay unit is electrically connected to the second input end of the XOR, and the output end of the XOR outputs the edge pulse. The delay unit is composed of an even number of NOT gates which are connected in series, and is used for delaying the square wave at the output end of the U1. When the level of the input square wave is inverted, the first input end and the second input end of the XOR gate XOR generate an edge pulse with the same width as the delay time generated by the delay unit at the output end due to different delays. The width of the edge pulse is in the nanosecond range, while the width of the zero-crossing pulse is generally required to be in the microsecond range to the millisecond range, so that the width of the edge pulse needs to be extended to meet the requirement.

As shown in fig. 4, the zero-crossing pulse generating unit is connected to the edge pulse generating unit, and is configured to receive the edge pulse and perform width extension on the edge pulse to generate the zero-crossing pulse. The zero-crossing pulse generating unit includes: the pulse extension unit is electrically connected with the edge pulse generation unit, the bias circuit unit is electrically connected with the pulse extension unit, and the optical coupler driving unit is electrically connected with the bias circuit unit and the pulse extension unit.

Specifically, the zero-cross pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8, resistors R2, R3 and R4, capacitors C2 and C3, NOT gates U2 and U3; MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3 and R3 form a pulse extension unit; MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2 and R4 form a bias circuit unit; MN4, MN5 and MN6 constitute an optocoupler drive unit. The source electrodes of the NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9 are connected, and the source electrodes of the PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8 are connected. More specific circuit connection relationships are as follows:

more specifically, the pulse extension unit implements width extension of the edge pulse, and includes: the edge pulse circuit is electrically connected with the grid of MN7 and the grid of MN9, the drain of MN7 is electrically connected with the grid of MN8, the drain of MN7 is also electrically connected with one end of C2, the drain of MN9 is electrically connected with one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input terminal of U2, the output terminal of U2 is electrically connected to the input terminal of U3, and the output terminal of U3 is electrically connected to the gate of MP 6.

The bias circuit unit provides current bias for pulse extension unit and opto-coupler drive unit, and the bias circuit unit includes: the source electrode of the MP, the source electrode of the MP and the source electrode of the MP are electrically connected, the drain electrode of the MP, the grid electrode of the MP are electrically connected, the grid electrode of the MP is electrically connected with the output end of the U, the drain electrode of the MP is electrically connected with the drain electrode of the MN, the drain electrode of the MP is electrically connected with the grid electrode of the MN, the drain electrode of the MN is electrically connected with the drain electrode of the MN, the source electrode of the MN is electrically connected with the grid electrode of the MN, the source electrode of the MN is also electrically connected with one end of the R, the other end.

The optical coupling drive unit is used for as optical coupling driven constant current source output circuit, and optical coupling drive unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, the source of MN5, the source of MN6, the source of MN4 and the source of MN7 are electrically connected, the gate of MN4 is electrically connected to the output end of U2, and the drain of MN6 outputs zero-crossing pulse. The drain electrode of MN6 is constant current output port, adopts constant current source output can realize the quick opening of opto-coupler, reduces the opto-coupler delay.

The alternating current zero crossing point detection circuit further comprises an external optical coupler U4, and the optical coupler U4 is composed of a light emitting diode and a triode. The anode of the LED is electrically connected to the power supply terminal of U1, and the cathode of the LED is electrically connected to the drain of MN 6. The emitter of the triode is grounded, and the collector of the triode is electrically connected with the resistor R5 and then connected with the power supply.

The operation of the zero-crossing pulse generating unit will be briefly described below.

When the input edge pulse is at high level, MN7 will quickly discharge the charge in C2, and make the ENB signal output from the not gate U2 low and the EN signal output from the not gate U3 high. The EN signal and the ENB signal are enable signals of the entire circuit. When the EN signal is at a high level, the bias circuit unit starts to operate to provide bias for the whole circuit, and the driving optical coupling unit outputs a current in milliampere level from the drain of MN6 to drive the light emitting diode of the optical coupler to emit light. At this time, MP1, MN1, and MN2 are on, and MP2, MN3, and MN4 are off. R4 provides uA (microampere) level current for MN2, and the width and length of MN2 are large, so that the VGS voltage of the MN is approximately equal to the threshold voltage VTH of the MN, thereby stabilizing the current passing through R2 to be about VTH/R2. The current passing through R2 is independent of the supply voltage and serves as a current reference for the entire circuit. The current mirror formed by MP3, MP4, and MP5 directly copies the current of R2, and the current mirror formed by MN5 and MN6 copies the current of MP 4.

When the input edge pulse is low, MN7 will turn off, but since the voltage of the C2 capacitor is 0 at this time, the EN signal and the ENB signal do not immediately change state when MN7 just starts to turn off. At this time, the voltage of C2 is a nanoamp charging current provided by MP5, the voltage of C2 gradually rises with time, when the voltage rises to the on voltage of MN8, MN8 starts to be turned on, so MP8 is turned on, MP8 starts to charge C3, when the level of C3 gradually rises, MP7 is turned off, and the levels of the ENB signal output by U2 and the EN signal output by U3 are inverted, so that the working state is restored to before the edge pulse is input.

After the EN and ENB state is recovered, the bias current and the optocoupler constant current driving output are closed, at the moment, MP1 is closed, MP2, MN3 and MN4 are switched on, and the gate voltages of MN1, MN5 and MN6 are pulled low to realize closing. The gate voltages of MP3, MP4, and MP5 are pulled up to VDD to turn off, and MP6 is turned on at the same time, so that the level of C2, MP6 and R3, are pulled up to VDD, and no indeterminate state occurs. Therefore, the whole circuit reenters the low power consumption state.

In the operation process, the pulse extension unit is used for extending the width of the input nanosecond-level edge pulse to generate microsecond-level zero-crossing pulse, and the optocoupler driving unit is used for outputting the pulse current of the constant current source. The extension width is determined by the bias current of MP5 and the capacitance values of C2 and C3, and the width of the zero-cross pulse can be adjusted by adjusting the bias current of MP5 and the capacitance values of C2 and C3.

In a preferred embodiment, R1 in the power-taking and ac-shaping unit is an external resistor, and C1 is an external capacitor.

In a preferred embodiment, the optical coupler U4 is an external optical coupler.

As shown in fig. 5, a chip employs the alternating current zero crossing point detection circuit.

In a preferred embodiment, the chip employs the alternating current zero crossing point detection circuit, but the circuit does not include the resistor R1, the capacitor C1, the optocoupler U4 and the resistor R5, and the resistor R1, the capacitor C1, the optocoupler U4 and the resistor R5 are electrically connected to the chip as peripheral elements. Specifically, the chip includes an input terminal IN, a power terminal VDD, a ground terminal VSS, and an output terminal OUT. The input terminal IN is the non-inverting input terminal of U1 IN the alternating current zero crossing detection circuit, the power supply terminal VDD is the power supply terminal of U1 and the sources of MP 1-MP 8 IN the zero crossing pulse generation unit, the ground terminal VSS is the ground terminal of U1 and the sources of MN 2-MN 9 IN the zero crossing pulse generation unit, and the output terminal OUT is the drain of MN6 IN the zero crossing pulse generation unit. One end of the resistor R1 is electrically connected to the input end IN of the chip, one end of the capacitor C1 is electrically connected to the power supply end VDD, the other end of the capacitor C1 is electrically connected to the ground end VSS, the anode of the light emitting diode of the optical coupler U4 is electrically connected to the power supply end VDD, the cathode of the light emitting diode is electrically connected to the output end OUT, the emitter of the triode of the optical coupler U4 is grounded, the source of the triode is electrically connected to one end of the resistor R5, the other end of the resistor R5 is connected to the power supply of the low-voltage system, and zero-.

In an alternative embodiment, the resistance of R1 is 500K-3M Ω, the capacitance of C1 is 100 nF-470 nF, and the larger the value of C1, the smaller the resistance of R1 is.

In one embodiment, R1 is taken to be 2M Ω and C1 is taken to be 220 nF.

In the technical scheme of the invention, on the basis of a chip, a peripheral circuit only needs 1 optocoupler, 2 resistors and 1 capacitor. The peripheral circuit is very concise, convenient to connect during use and extremely low in power consumption. Taking R1 as 2M omega as an example, the power consumption of the alternating current zero-crossing detection circuit is about: 220V/2M =24.2mW, the overall power consumption is lower.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. An alternating current zero-crossing detection circuit, characterized by comprising:

the power taking and alternating current shaping unit is used for generating square waves with the same frequency and phase based on alternating current;

the edge pulse generating unit is electrically connected with the power taking and alternating current shaping unit and is used for generating edge pulses at the alternating current zero crossing points based on the square waves;

a zero-crossing pulse generating unit electrically connected to the edge pulse generating unit for generating a zero-crossing pulse based on the edge pulse.

2. The alternating current zero-crossing detection circuit according to claim 1, wherein the zero-crossing pulse generating unit includes: the pulse extension unit is electrically connected with the edge pulse generation unit, the bias circuit unit is electrically connected with the pulse extension unit, and the optocoupler driving unit is electrically connected with the bias circuit unit and the pulse extension unit.

3. The alternating current zero-crossing detection circuit according to claim 2, wherein the zero-crossing pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8, resistors R2, R3 and R4, capacitors C2 and C3, NOT gates U2 and U3; the MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3 and R3 form a pulse extension unit; the MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2 and R4 form a bias circuit unit; MN4, MN5 and MN6 constitute an optocoupler drive unit.

4. The alternating current zero-crossing detection circuit according to claim 3, wherein the pulse extension unit comprises: the edge pulse circuit is electrically connected with the grid of MN7 and the grid of MN9, the drain of MN7 is electrically connected with the grid of MN8, the drain of MN7 is also electrically connected with one end of C2, the drain of MN9 is electrically connected with one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input terminal of U2, the output terminal of U2 is electrically connected to the input terminal of U3, and the output terminal of U3 is electrically connected to the gate of MP 6.

5. The alternating current zero-crossing detection circuit according to claim 4, wherein the bias circuit unit includes: the source electrode of the MP, the source electrode of the MP and the source electrode of the MP are electrically connected, the drain electrode of the MP, the grid electrode of the MP are electrically connected, the grid electrode of the MP is electrically connected with the output end of the U, the drain electrode of the MP is electrically connected with the drain electrode of the MN, the drain electrode of the MP is electrically connected with the grid electrode of the MN, the drain electrode of the MN is electrically connected with the drain electrode of the MN, the source electrode of the MN is electrically connected with the grid electrode of the MN, the source electrode of the MN is also electrically connected with one end of the R, the other end.

6. The alternating current zero crossing detection circuit of claim 5, wherein the optocoupler drive unit comprises a drain electrode of MN5 electrically connected to a gate electrode of MN5, a gate electrode of MN6, a drain electrode of MN4 and a drain electrode of MP4, a source electrode of MN5, a source electrode of MN6, a source electrode of MN4 and a source electrode of MN7, a gate electrode of MN4 electrically connected to an output terminal of U2, and a drain electrode of MN6 outputting the zero crossing pulse.

7. The alternating current zero-crossing detection circuit according to claim 1, wherein the power-taking and alternating current shaping unit comprises: the circuit comprises a resistor R1, diodes D1 and D2, a capacitor C1 and a comparator U1; one end of R1 is used for electrically connecting the alternating current, the other end of R1 is electrically connected with the non-inverting input end of U1, the non-inverting input end of U1 is also electrically connected with the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected with the power supply end of U1, the anode of D2, the grounding end of U1 and the inverting input end of U1 are electrically connected with each other and grounded, C1 is electrically connected between the power supply end and the grounding end of U1, and the output end of U1 outputs square waves with the same frequency and phase as the.

8. The alternating current zero-crossing detection circuit according to claim 7, wherein the edge pulse generating unit includes: an INV, a delay unit and an XOR; INV is electrically connected to the output end of the U1, the output ends of the INV are electrically connected to the first input end of the XOR and the input end of the delay unit respectively, the output end of the delay unit is electrically connected to the second input end of the XOR, and the output end of the XOR outputs the edge pulse.

9. The alternating current zero-crossing detection circuit of claim 1, further comprising an external optocoupler, wherein an anode of the light emitting diode in the optocoupler is electrically connected to a power supply terminal of U1, and a cathode of the light emitting diode is electrically connected to a drain of MN 6.

10. A chip, characterized in that, the alternating current zero crossing detection circuit of any one of claims 1 to 9 is adopted, wherein R1 in the electricity taking and alternating current shaping unit is an external resistor, and C1 is an external capacitor.

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