CN111650425A - A kind of alternating current zero-crossing detection circuit and chip - Google Patents

A kind of alternating current zero-crossing detection circuit and chip Download PDF

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CN111650425A
CN111650425A CN202010676237.7A CN202010676237A CN111650425A CN 111650425 A CN111650425 A CN 111650425A CN 202010676237 A CN202010676237 A CN 202010676237A CN 111650425 A CN111650425 A CN 111650425A
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electrically connected
alternating current
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CN111650425B (en
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曾明辉
黄威盛
毛锴
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Shenzhen Lanchao Technology Co ltd
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Shenzhen Silandtech Electronic Technology Co ltd
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Abstract

The invention discloses an alternating current zero crossing point detection circuit and a chip, wherein the alternating current zero crossing point detection circuit comprises: the power taking and alternating current shaping unit is used for generating square waves with the same frequency and phase based on alternating current; the edge pulse generating unit is electrically connected with the power taking and alternating current shaping unit and is used for generating edge pulses at the alternating current zero crossing points based on the square waves; a zero-crossing pulse generating unit electrically connected to the edge pulse generating unit for generating a zero-crossing pulse based on the edge pulse. The invention can simultaneously detect the zero crossing point of the rising edge and the zero crossing point of the falling edge of the alternating current, and improves the precision of detecting the zero crossing point.

Description

一种交流电过零点检测电路及芯片A kind of alternating current zero-crossing detection circuit and chip

技术领域technical field

本发明涉及交流电过零点检测技术领域,特别是涉及一种交流电过零点检测电路及芯片。The invention relates to the technical field of alternating current zero-cross detection, in particular to an alternating current zero-cross detection circuit and a chip.

背景技术Background technique

交流电过零点检测电路在可控硅控制电路、大功率设备或者电器接入、电力载波通信、照明控制等领域是一种常见的电路。这些领域均需要对交流电的电压过零点进行准确的检测,在过零点产生过零脉冲或者电平信号作为系统控制的参考信号,或者基于过零检测信号获取交流电的交流周期、电压波动、相位等相关信息。The AC zero-crossing detection circuit is a common circuit in the fields of thyristor control circuit, high-power equipment or electrical appliance access, power carrier communication, and lighting control. In these fields, it is necessary to accurately detect the voltage zero-crossing point of the alternating current, generate a zero-crossing pulse or level signal at the zero-crossing point as a reference signal for system control, or obtain the alternating current cycle, voltage fluctuation, phase, etc. of the alternating current based on the zero-crossing detection signal. Related Information.

当前的交流电过零点检测电路,都是基于分立元器件的过零点检测电路,电路结构复杂,并且只能在交流电的上升沿或者下降沿产生的过零点信号,如专利号:CN103063904A和CN102508014A。但通常系统对交流电的上升沿和下降沿的过零信号均有需要,一种做法是根据单一沿的过零检测信号,系统通过计算的方式获得另一个沿的虚拟过零检测信号。但是这种虚拟获得的另一个沿的过零检测信号,实际上并未对另一过零点进行检测,从而丢失了一部分过零点所携带的信息,如电压波动导致的过零点抖动。另一种做法是采用两个相同的电路分别去检测上升沿和下降沿的过零点,但是系统的成本、功耗和复杂度都加倍。The current AC zero-crossing detection circuits are all based on discrete components. The circuit structure is complex, and the zero-crossing signal can only be generated on the rising or falling edge of the AC, such as patent numbers: CN103063904A and CN102508014A. But usually the system needs the zero-crossing signal of the rising edge and the falling edge of the alternating current. One way is to obtain the virtual zero-crossing detection signal of the other edge by calculation according to the zero-crossing detection signal of a single edge. However, the zero-crossing detection signal of another edge obtained by this kind of virtual does not actually detect another zero-crossing point, thus losing part of the information carried by the zero-crossing point, such as the zero-crossing point jitter caused by voltage fluctuation. Another approach is to use two identical circuits to detect the zero-crossing of the rising and falling edges respectively, but the cost, power consumption and complexity of the system are doubled.

另外基于分立元器件的过零点检测电路的外围器件数量多,由于采用了较多的二极管和三极管等流控器件,在自身损耗的功耗方面也较大,普遍需要50-100mW左右。而外围器件多导致的另一个方面问题是检测精度也受损,一般检测到的过零点通常与实际过零点的误差都在20us以上。In addition, the number of peripheral devices of the zero-crossing detection circuit based on discrete components is large. Due to the use of more current control devices such as diodes and triodes, the power consumption of its own loss is also large, generally requiring about 50-100mW. Another problem caused by many peripheral devices is that the detection accuracy is also damaged. Generally, the error between the detected zero-crossing point and the actual zero-crossing point is more than 20us.

因此,如何设计一种高精度的能够同时检测上升沿和下降沿的过零点的过零点检测电路是业界亟待解决的技术问题。Therefore, how to design a high-precision zero-crossing detection circuit capable of simultaneously detecting the zero-crossing points of the rising edge and the falling edge is a technical problem to be solved urgently in the industry.

发明内容SUMMARY OF THE INVENTION

为了解决上述现有技术中关于同时检测上升沿和下降沿的过零点不精确的技术问题,本发明提出一种交流电过零点检测电路及芯片。In order to solve the technical problem of inaccurate detection of the zero-crossing points of the rising edge and the falling edge in the above-mentioned prior art, the present invention provides an alternating current zero-crossing point detection circuit and a chip.

本发明采用的技术方案是首先提供一种交流电过零点检测电路,包括:取电与交流整形单元,其用于基于交流电生成同频同相的方波;边缘脉冲产生单元,其电连接于所述取电与交流整形单元,用于基于所述方波生成在所述交流电过零点的边缘脉冲;过零脉冲产生单元,其电连接于所述边缘脉冲产生单元,用于基于所述边缘脉冲生成过零脉冲。The technical solution adopted in the present invention is to first provide an alternating current zero-crossing point detection circuit, including: a power taking and alternating current shaping unit, which is used for generating square waves of the same frequency and phase based on alternating current; an edge pulse generating unit, which is electrically connected to the a power taking and alternating current shaping unit for generating an edge pulse at the zero-crossing point of the alternating current based on the square wave; a zero-crossing pulse generating unit, which is electrically connected to the edge pulse generating unit for generating based on the edge pulse zero-crossing pulse.

在一实施方式中,所述过零脉冲产生单元包括:电连接于所述边缘脉冲产生单元的脉冲延展单元、电连接于所述脉冲延展单元的偏置电路单元、及电连接于所述偏置电路单元和所述脉冲延展单元的光耦驱动单元。In one embodiment, the zero-crossing pulse generating unit includes: a pulse stretching unit electrically connected to the edge pulse generating unit, a bias circuit unit electrically connected to the pulse stretching unit, and a bias circuit unit electrically connected to the biasing unit. The circuit unit and the optocoupler driving unit of the pulse stretching unit are arranged.

在一实施方式中,所述过零脉冲产生单元包括:NMOS管MN1、MN2、MN3、MN4、MN5、MN6、MN7、MN8、MN9,PMOS管MP1、MP2、MP3、MP4、MP5、MP6、MP7、MP8,电阻R2、R3、R4,电容C2、C3,非门U2、U3;所述MN7、MN8、MN9、MP6、MP7、MP8、C2、C3、U2、U3、R3构成脉冲延展单元;所述MN1、MN2、MN3、MP1、MP2、MP3、MP4、MP5、R2、R4构成偏置电路单元;MN4、MN5、MN6构成光耦驱动单元。In one embodiment, the zero-crossing pulse generating unit includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7 , MP8, resistors R2, R3, R4, capacitors C2, C3, NOT gates U2, U3; the MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3, R3 constitute a pulse stretching unit; The MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2, R4 constitute the bias circuit unit; MN4, MN5, MN6 constitute the optocoupler driving unit.

在一实施方式中,所述脉冲延展单元包括:所述边缘脉冲电路电连接于MN7的栅极及MN9的栅极,MN7的漏极电连接于MN8的栅极,MN7的漏极还电连接于C2的一端,MN9的漏极电连接于C3的一端,MN7的源极、MN8的源极、MN9的源极、C2的另一端及C3的另一端相电连接且接地;MP6的漏极通过电阻R3电连接于MN7的漏极,MP7的漏极电连接于MP8的栅极和MN8的漏极,MP8的漏极电连接于MP7的栅极和MN9的漏极,MP6的源极、MP7的源极、MP8的源极相电连接,MP7的漏极还电连接于U2的输入端,U2的输出端电连接U3的输入端,U3的输出端电连接MP6的栅极。In one embodiment, the pulse stretching unit includes: the edge pulse circuit is electrically connected to the gate of MN7 and the gate of MN9, the drain of MN7 is electrically connected to the gate of MN8, and the drain of MN7 is also electrically connected At one end of C2, the drain of MN9 is electrically connected to one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 The resistor R3 is electrically connected to the drain of MN7, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, The source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input of U2, the output of U2 is electrically connected to the input of U3, and the output of U3 is electrically connected to the gate of MP6.

在一实施方式中,所述偏置电路单元包括:MP1的源极、MP2的源极、MP3的源极、MP4的源极、MP5的源极与MP6的源极相电连接, MP2的漏极、MP3的漏极、MP3的栅极、MP4的栅极、MP5的栅极相电连接,MP1的栅极电连接于U2的输出端,MP2的栅极电连接于U3的输出端,MP5的漏极电连接于MN7的漏极,MP1的漏极通过电阻R4电连接于MN1的栅极、MN2的漏极及MN3的漏极,MN1的漏极电连接于MP3的漏极,MN1的源极电连接于MN2的栅极,MN1的源极还电连接于R2的一端,R2的另一端、MN2的源极、MN3的源极电连接于MN7的源极,MN3的栅极电连接于U2的输出端。In one embodiment, the bias circuit unit includes: the source of MP1, the source of MP2, the source of MP3, the source of MP4, the source of MP5 and the source of MP6 are electrically connected, and the drain of MP2 is electrically connected to the source of MP6. The pole, the drain of MP3, the gate of MP3, the gate of MP4, the gate of MP5 are electrically connected to each other, the gate of MP1 is electrically connected to the output terminal of U2, the gate of MP2 is electrically connected to the output terminal of U3, and the gate of MP5 is electrically connected to the output terminal of U2. The drain of MN1 is electrically connected to the drain of MN7, the drain of MP1 is electrically connected to the gate of MN1, the drain of MN2 and the drain of MN3 through the resistor R4, the drain of MN1 is electrically connected to the drain of MP3, and the drain of MN1 is electrically connected to the drain of MP3. The source is electrically connected to the gate of MN2, the source of MN1 is also electrically connected to one end of R2, the other end of R2, the source of MN2, and the source of MN3 are electrically connected to the source of MN7, and the gate of MN3 is electrically connected at the output of U2.

在一实施方式中,所述光耦驱动单元包括:MN5的漏极电连接于MN5的栅极、MN6的栅极、MN4的漏极及MP4的漏极,MN5的源极、MN6的源极、MN4的源极及MN7的源极相电连接,MN4的栅极电连接U2的输出端,MN6的漏极输出所述过零脉冲。In one embodiment, the optocoupler driving unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, the source of MN5 and the source of MN6 The source of MN4 and the source of MN7 are electrically connected, the gate of MN4 is electrically connected to the output terminal of U2, and the drain of MN6 outputs the zero-crossing pulse.

在一实施方式中,所述取电与交流整形单元包括:电阻R1、二极管D1、D2,电容C1及比较器U1;R1的一端用以电连接所述交流电,R1的另一端电连接U1的同相输入端,U1的同相输入端还电连接于D1的阳极及D2的阴极,D1的阴极电连接于U1的电源端,D2的阳极、U1的接地端及U1的反相输入端相互电连接且接地,C1电连接于U1的电源端和接地端之间,U1的输出端输出与所述交流电同频同相的方波。In one embodiment, the power taking and AC shaping unit includes: a resistor R1, diodes D1, D2, a capacitor C1 and a comparator U1; one end of R1 is electrically connected to the AC power, and the other end of R1 is electrically connected to U1. Non-inverting input terminal, the non-inverting input terminal of U1 is also electrically connected to the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected to the power supply terminal of U1, the anode of D2, the ground terminal of U1 and the inverting input terminal of U1 are electrically connected to each other And grounded, C1 is electrically connected between the power supply terminal and the ground terminal of U1, and the output terminal of U1 outputs a square wave of the same frequency and phase as the alternating current.

在一实施方式中,所述边缘脉冲产生单元包括:非门INV、延迟单元及异或门XOR;INV电连接于U1的输出端,INV的输出端分别电连接于XOR的第一输入端及延迟单元的输入端,延迟单元的输出端电连接于XOR的第二输入端,XOR的输出端输出所述边缘脉冲。In one embodiment, the edge pulse generating unit includes: an invertor INV, a delay unit and an exclusive OR gate XOR; INV is electrically connected to the output end of U1, and the output end of INV is electrically connected to the first input end of XOR and the XOR respectively. The input end of the delay unit and the output end of the delay unit are electrically connected to the second input end of the XOR, and the output end of the XOR outputs the edge pulse.

在一实施方式中,所述取电与交流整形单元中的R1为外接电阻,C1为外接电容。In one embodiment, R1 in the power taking and AC shaping unit is an external resistor, and C1 is an external capacitor.

在一实施方式中,还包括外接光耦合器,所述光耦合器中的发光二极管的阳极电连接于U1的电源端,发光二极管的阴极电连接于MN6的漏极。In one embodiment, an external optocoupler is further included, wherein the anode of the light-emitting diode in the optocoupler is electrically connected to the power supply terminal of U1, and the cathode of the light-emitting diode is electrically connected to the drain of MN6.

本发明还提供一种芯片,采用上述的交流电过零点检测电路。The present invention also provides a chip, which adopts the above-mentioned alternating current zero-crossing detection circuit.

与现有技术比较,本发明至少具有如下优点。Compared with the prior art, the present invention has at least the following advantages.

通过设置取电与交流整形单元生成与交流电同频同相的方波,通过边缘脉冲产生电路生成边缘脉冲,使得同时检测到交流电上升沿的过零点和下降沿的过零点,且提升了检测过零点的精度。通过设置过零脉冲产生电路,对边缘脉冲进行宽度延展生成需要宽度的过零脉冲,实现了对过零脉冲宽度的调节。进一步的,将交流电过零点检测电路集成在一个芯片中,减少了外围电路的复杂度,使得应用时更加简便,且降低了能耗。By setting the power taking and AC shaping unit to generate a square wave with the same frequency and phase as the AC power, and generating the edge pulse through the edge pulse generating circuit, the zero-crossing point of the rising edge and the zero-crossing point of the falling edge of the AC power are detected at the same time, and the detection of the zero-crossing point is improved. accuracy. By setting the zero-crossing pulse generating circuit, the width of the edge pulse is extended to generate the zero-crossing pulse with the required width, and the adjustment of the zero-crossing pulse width is realized. Further, the AC zero-crossing detection circuit is integrated into one chip, which reduces the complexity of the peripheral circuit, makes the application more convenient, and reduces the energy consumption.

附图说明Description of drawings

为了更清楚地说明本发明实施例中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以如这些附图获得其他的附图。In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for the present invention. In some embodiments, for those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

图1为本发明一实施例中交流电过零点检测电路的框架示意图;1 is a schematic diagram of a frame of an alternating current zero-crossing detection circuit according to an embodiment of the present invention;

图2为图1中取电与交流整形单元的电路示意图;Fig. 2 is the circuit schematic diagram of the power taking and AC shaping unit in Fig. 1;

图3为图1中边缘脉冲产生单元的电路示意图;3 is a schematic circuit diagram of an edge pulse generating unit in FIG. 1;

图4为图1中过零脉冲产生单元的电路示意图;Fig. 4 is the circuit schematic diagram of the zero-crossing pulse generating unit in Fig. 1;

图5为本发明一实施例中集成交流电过零点检测电路的芯片的应用示意图;5 is an application schematic diagram of a chip integrating an alternating current zero-crossing detection circuit according to an embodiment of the present invention;

图6为本发明一实施例中检测交流电过零点的检测效果的示意图。FIG. 6 is a schematic diagram of a detection effect of detecting an alternating current zero-crossing point according to an embodiment of the present invention.

具体实施方式Detailed ways

为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

由此,本说明书中所指出的一个特征将用于说明本发明的一个实施方式的其中一个特征,而不是暗示本发明的每个实施方式必须具有所说明的特征。此外,应当注意的是本说明书描述了许多特征。尽管某些特征可以组合在一起以示出可能的系统设计,但是这些特征也可用于其他的未明确说明的组合。由此,除非另有说明,所说明的组合并非旨在限制。Thus, a reference to a feature in this specification will be used to describe one of the features of an embodiment of the invention and not to imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes a number of features. Although certain features may be combined together to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Thus, unless otherwise stated, the combinations described are not intended to be limiting.

下面结合附图以及实施例对本发明的原理及结构进行详细说明。The principle and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

如图1所示,本发明提供一种交流电过零点检测电路,其用于获得交流电过零点的信息。该交流电过零点检测电路包括:依次电连接的取电与交流整形单元、边缘脉冲产生单元、过零脉冲产生单元。其中,取电与交流整形单元用于电连接待检测的交流电,并基于交流电生成同频同相的方波。边缘脉冲产生单元用于基于方波生成在交流电过零点的边缘脉冲。过零脉冲产生单元用于基于边缘脉冲生成过零脉冲,过零脉冲即是通过本发明技术方案需要得到的关于该交流电过零点的信息。As shown in FIG. 1 , the present invention provides an alternating current zero-crossing detection circuit, which is used to obtain the information of alternating current zero-crossing. The alternating current zero-crossing point detection circuit includes: a power-taking and alternating-current shaping unit, an edge pulse generating unit, and a zero-crossing pulse generating unit that are electrically connected in sequence. Wherein, the power taking and AC shaping unit is used to electrically connect the AC power to be detected, and generate square waves of the same frequency and phase based on the AC power. The edge pulse generating unit is used for generating edge pulses at the zero-crossing point of the alternating current based on the square wave. The zero-crossing pulse generating unit is used for generating a zero-crossing pulse based on the edge pulse, and the zero-crossing pulse is the information about the zero-crossing point of the alternating current that needs to be obtained through the technical solution of the present invention.

相比于传统的基于分立元器件的过零检测方案,本发明的技术方案能够同时检测交流上升沿的过零点和下降沿的过零点(请参阅图6的检测效果示意图),电路结构简单,成本低,且检测精度高。Compared with the traditional zero-crossing detection scheme based on discrete components, the technical scheme of the present invention can simultaneously detect the zero-crossing point of the rising edge of the AC and the zero-crossing point of the falling edge (refer to the schematic diagram of the detection effect in FIG. 6 ), and the circuit structure is simple, Low cost and high detection accuracy.

下面分别详述本发明交流电过零点检测电路的各个部分。Each part of the AC zero-crossing detection circuit of the present invention will be described in detail below.

如图2所示,取电与交流整形单元包括:电阻R1、二极管D1、D2,电容C1及比较器U1。R1的一端用以电连接待检测的交流电,R1的另一端电连接U1的同相输入端。U1的同相输入端还电连接于D1的阳极及D2的阴极,D1的阴极电连接于U1的电源端,D2的阳极、U1的接地端及U1的反相输入端相互电连接且接地,D1与D2为输入端口的ESD保护二极管,实现对端口的ESD保护,同时实现半波整流。C1电连接于U1的电源端和接地端之间,U1的输出端输出与交流电同频同相的方波。R1可以是多颗电阻的串联或并联。优选的,D2为齐纳二极管。U1的比较阈值设为0V。当输入的交流电过零时,比较器输出端输出的电平翻转,从而实现了对交流电的整形,产生与输入的交流电同频同相的方波输出。由于U1的比较阈值为0V,过零脉冲与实际过零点之间几乎没有延迟,因此具有极高的检测精度。As shown in Figure 2, the power taking and AC shaping unit includes: resistor R1, diodes D1, D2, capacitor C1 and comparator U1. One end of R1 is used to electrically connect the alternating current to be detected, and the other end of R1 is electrically connected to the non-inverting input end of U1. The non-inverting input terminal of U1 is also electrically connected to the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected to the power supply terminal of U1, the anode of D2, the ground terminal of U1 and the inverting input terminal of U1 are electrically connected to each other and grounded, D1 With D2 as the ESD protection diode of the input port, the ESD protection of the port is realized, and half-wave rectification is realized at the same time. C1 is electrically connected between the power supply terminal and the ground terminal of U1, and the output terminal of U1 outputs a square wave with the same frequency and phase as the alternating current. R1 can be a series or parallel connection of multiple resistors. Preferably, D2 is a Zener diode. The comparison threshold of U1 is set to 0V. When the input AC power crosses zero, the output level of the comparator output is reversed, thereby realizing the shaping of the AC power and generating a square wave output with the same frequency and phase as the input AC power. Since the comparison threshold of U1 is 0V, there is almost no delay between the zero-crossing pulse and the actual zero-crossing point, so it has extremely high detection accuracy.

如图3所示,边缘脉冲产生单元电连接于取电与交流整形单元,用于接收方波,并基于方波生成边缘脉冲。边缘脉冲产生单元包括:非门INV、延迟单元及异或门XOR; INV电连接于U1的输出端,INV的输出端分别电连接于XOR的第一输入端及延迟单元的输入端,延迟单元的输出端电连接于XOR的第二输入端,XOR的输出端输出边缘脉冲。延迟单元由偶数个非门串联组成,延迟单元用于对U1输出端的方波进行延迟。当输入方波的电平发生翻转时,异或门XOR的第一输入端与第二输入端由于延迟不同,会在输出端产生与延迟单元产生的延迟时间相同宽度的一个边缘脉冲。该边缘脉冲的宽度为纳秒级,而对过零脉冲的宽度的一般要求为微秒级到毫秒级,因此需要对边缘脉冲进行宽度延展以满足需求。As shown in FIG. 3 , the edge pulse generating unit is electrically connected to the power taking and AC shaping unit, and is used for receiving square waves and generating edge pulses based on the square waves. The edge pulse generating unit includes: a NOT gate INV, a delay unit and an exclusive OR gate XOR; INV is electrically connected to the output end of U1, and the output end of INV is electrically connected to the first input end of XOR and the input end of the delay unit respectively, and the delay unit The output terminal of the XOR is electrically connected to the second input terminal of the XOR, and the output terminal of the XOR outputs the edge pulse. The delay unit is composed of an even number of NOT gates in series, and the delay unit is used to delay the square wave at the output end of U1. When the level of the input square wave is inverted, the first input terminal and the second input terminal of the exclusive OR gate XOR will generate an edge pulse with the same width as the delay time generated by the delay unit at the output terminal due to different delays. The width of the edge pulse is in nanoseconds, and the general requirement for the width of the zero-crossing pulse is in the order of microseconds to milliseconds, so the width of the edge pulse needs to be extended to meet the requirements.

如图4所示,过零脉冲产生单元连接于边缘脉冲产生单元,用于接收边缘脉冲,并对边缘脉冲进行宽度延展以生成过零脉冲。过零脉冲产生单元包括:电连接于边缘脉冲产生单元的脉冲延展单元、电连接于脉冲延展单元的偏置电路单元、及电连接于偏置电路单元和脉冲延展单元的光耦驱动单元。As shown in FIG. 4 , the zero-crossing pulse generating unit is connected to the edge pulse generating unit, and is used for receiving the edge pulse and extending the width of the edge pulse to generate the zero-crossing pulse. The zero-crossing pulse generating unit includes: a pulse extending unit electrically connected to the edge pulse generating unit, a bias circuit unit electrically connected to the pulse extending unit, and an optocoupler driving unit electrically connected to the bias circuit unit and the pulse extending unit.

具体地,过零脉冲产生单元包括:NMOS管MN1、MN2、MN3、MN4、MN5、MN6、MN7、MN8、MN9,PMOS管MP1、MP2、MP3、MP4、MP5、MP6、MP7、MP8,电阻R2、R3、R4,电容C2、C3,非门U2、U3;MN7、MN8、MN9、MP6、MP7、MP8、C2、C3、U2、U3、R3构成脉冲延展单元;MN1、MN2、MN3、MP1、MP2、MP3、MP4、MP5、R2、R4构成偏置电路单元;MN4、MN5、MN6构成光耦驱动单元。其中,NMOS管MN1、MN2、MN3、MN4、MN5、MN6、MN7、MN8、MN9的源极相连接,PMOS管MP1、MP2、MP3、MP4、MP5、MP6、MP7、MP8的源极相连接。更具体的电路连接关系如下:Specifically, the zero-crossing pulse generating unit includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, and resistor R2 , R3, R4, capacitors C2, C3, NOT gates U2, U3; MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3, R3 constitute a pulse extension unit; MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2, R4 constitute the bias circuit unit; MN4, MN5, MN6 constitute the optocoupler drive unit. The sources of NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9 are connected to each other, and the sources of PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8 are connected to each other. The more specific circuit connection relationship is as follows:

更具体地,脉冲延展单元实现边缘脉冲的宽度延展,脉冲延展单元包括:边缘脉冲电路电连接于MN7的栅极及MN9的栅极,MN7的漏极电连接于MN8的栅极,MN7的漏极还电连接于C2的一端,MN9的漏极电连接于C3的一端,MN7的源极、MN8的源极、MN9的源极、C2的另一端及C3的另一端相电连接且接地;MP6的漏极通过电阻R3电连接于MN7的漏极,MP7的漏极电连接于MP8的栅极和MN8的漏极,MP8的漏极电连接于MP7的栅极和MN9的漏极,MP6的源极、MP7的源极、MP8的源极相电连接,MP7的漏极还电连接于U2的输入端,U2的输出端电连接U3的输入端,U3的输出端电连接MP6的栅极。More specifically, the pulse stretching unit realizes the width extension of the edge pulse, and the pulse stretching unit includes: the edge pulse circuit is electrically connected to the gate of MN7 and the gate of MN9, the drain of MN7 is electrically connected to the gate of MN8, and the drain of MN7 is electrically connected to the gate of MN8. The pole is also electrically connected to one end of C2, the drain of MN9 is electrically connected to one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; The drain of MP6 is electrically connected to the drain of MN7 through resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, MP6 The source of MP7 and the source of MP8 are electrically connected to each other, the drain of MP7 is also electrically connected to the input of U2, the output of U2 is electrically connected to the input of U3, and the output of U3 is electrically connected to the gate of MP6 pole.

偏置电路单元为脉冲延展单元和光耦驱动单元提供电流偏置,偏置电路单元包括:MP1的源极、MP2的源极、MP3的源极、MP4的源极、MP5的源极与MP6的源极相电连接, MP2的漏极、MP3的漏极、MP3的栅极、MP4的栅极、MP5的栅极相电连接,MP1的栅极电连接于U2的输出端,MP2的栅极电连接于U3的输出端,MP5的漏极电连接于MN7的漏极,MP1的漏极通过电阻R4电连接于MN1的栅极、MN2的漏极及MN3的漏极,MN1的漏极电连接于MP3的漏极,MN1的源极电连接于MN2的栅极,MN1的源极还电连接于R2的一端,R2的另一端、MN2的源极、MN3的源极电连接于MN7的源极,MN3的栅极电连接于U2的输出端。The bias circuit unit provides current bias for the pulse extension unit and the optocoupler drive unit. The bias circuit unit includes: the source of MP1, the source of MP2, the source of MP3, the source of MP4, the source of MP5 and the source of MP6. The source is electrically connected, the drain of MP2, the drain of MP3, the gate of MP3, the gate of MP4, the gate of MP5 are electrically connected, the gate of MP1 is electrically connected to the output terminal of U2, the gate of MP2 is electrically connected It is electrically connected to the output terminal of U3, the drain of MP5 is electrically connected to the drain of MN7, the drain of MP1 is electrically connected to the gate of MN1, the drain of MN2 and the drain of MN3 through the resistor R4, and the drain of MN1 is electrically connected to the drain of MN1. It is connected to the drain of MP3, the source of MN1 is electrically connected to the gate of MN2, the source of MN1 is also electrically connected to one end of R2, the other end of R2, the source of MN2 and the source of MN3 are electrically connected to the source of MN7. The source, the gate of MN3 is electrically connected to the output terminal of U2.

光耦驱动单元用于作为光耦驱动的恒流源输出电路,光耦驱动单元包括:MN5的漏极电连接于MN5的栅极、MN6的栅极、MN4的漏极及MP4的漏极,MN5的源极、MN6的源极、MN4的源极及MN7的源极相电连接,MN4的栅极电连接U2的输出端,MN6的漏极输出过零脉冲。MN6的漏极为恒流输出端口,采用恒流源输出可以实现光耦的快速开启,减小光耦延迟。The optocoupler drive unit is used as a constant current source output circuit driven by the optocoupler. The optocoupler drive unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, The source of MN5, the source of MN6, the source of MN4 and the source of MN7 are electrically connected to each other, the gate of MN4 is electrically connected to the output terminal of U2, and the drain of MN6 outputs a zero-crossing pulse. The drain of MN6 is the constant current output port, and the constant current source output can realize the fast opening of the optocoupler and reduce the delay of the optocoupler.

交流电过零点检测电路还包括外接光耦合器U4,光耦合器U4由发光二极管及三极管组成。发光二极管的阳极电连接于U1的电源端,发光二极管的阴极电连接于MN6的漏极。三极管的发射极接地,三极管的集电极电连接电阻R5后接电源。The AC zero-crossing detection circuit also includes an external optical coupler U4, which is composed of light-emitting diodes and triodes. The anode of the light-emitting diode is electrically connected to the power supply terminal of U1, and the cathode of the light-emitting diode is electrically connected to the drain of MN6. The emitter of the triode is grounded, and the collector of the triode is electrically connected to the resistor R5 and then connected to the power supply.

下面对上述过零脉冲产生单元的运行过程作简要说明。The operation process of the above zero-crossing pulse generating unit is briefly described below.

当输入的边缘脉冲为高电平时,MN7会快速释放掉C2中的电荷,并使非门U2的输出ENB信号为低电平,非门U3的输出EN信号为高电平。EN信号和ENB信号是整个电路的使能信号。EN信号为高电平的情况下,偏置电路单元开始工作,为整个电路提供偏置,同时驱动光耦合单元从MN6的漏极开始输出毫安级电流以驱动光耦合器的发光二极管发光。此时MP1、MN1、MN2导通,MP2、MN3、MN4关闭。R4为MN2提供uA(微安)级电流,MN2的宽长比较大,因此其VGS电压约等于其阈值电压VTH,从而使R2上经过的电流稳定在约为VTH/R2的大小。R2上经过的电流与电源电压无关,作为整个电路的电流基准。MP3、MP4、MP5构成的电流镜直接复制了R2的电流,MN5、MN6构成的电流镜则复制了MP4的电流。When the input edge pulse is high level, MN7 will quickly release the charge in C2, and make the output ENB signal of NOT gate U2 be low level, and the output EN signal of NOT gate U3 will be high level. The EN signal and the ENB signal are the enable signals of the entire circuit. When the EN signal is at high level, the bias circuit unit starts to work, provides bias for the entire circuit, and drives the optocoupler unit to output milliamp current from the drain of MN6 to drive the light-emitting diode of the optocoupler to emit light. At this time, MP1, MN1, and MN2 are turned on, and MP2, MN3, and MN4 are turned off. R4 provides uA (microampere) level current for MN2. The width and length of MN2 are relatively large, so its VGS voltage is approximately equal to its threshold voltage VTH, so that the current passing through R2 is stabilized at about VTH/R2. The current through R2 is independent of the supply voltage and serves as the current reference for the entire circuit. The current mirror composed of MP3, MP4, and MP5 directly replicates the current of R2, and the current mirror composed of MN5 and MN6 replicates the current of MP4.

当输入的边缘脉冲为低电平时,MN7会关闭,但是由于C2电容此时的电压为0,MN7刚开始关闭时EN信号和ENB信号并不会立即改变状态。此时C2的电压由于MP5提供纳安级充电电流,C2的电压会随着时间逐渐上升,当上升到MN8的导通电压时,MN8开始导通,从而开启了MP8,MP8开始给C3进行充电,当C3电平逐渐升高,关闭MP7,并使U2输出ENB信号和U3输出EN信号的电平翻转,恢复至边缘脉冲未输入前的工作状态。When the input edge pulse is low, MN7 will be turned off, but because the voltage of C2 capacitor is 0 at this time, the EN signal and ENB signal will not change state immediately when MN7 starts to turn off. At this time, the voltage of C2 is due to the nanoamp charging current provided by MP5, and the voltage of C2 will gradually increase with time. When it rises to the turn-on voltage of MN8, MN8 starts to conduct, thus turning on MP8, and MP8 starts to charge C3. , when C3 level rises gradually, close MP7, and make U2 output ENB signal and U3 output EN signal level inversion, restore to the working state before edge pulse is not input.

当EN和ENB的状态恢复之后,关闭偏置电流和光耦恒流驱动输出,此时MP1关闭,MP2、MN3、MN4导通,MN1、MN5、MN6的栅极电压被拉低,实现关闭。而MP3、MP4、MP5的栅极电压则被上拉至VDD,实现关闭,同时开启了MP6,使C2的电平有MP6和R3上拉至VDD电平,不出现不确定状态。从而实现了整个电路重新进入了低功耗状态。When the states of EN and ENB are restored, the bias current and the optocoupler constant current drive output are turned off. At this time, MP1 is turned off, MP2, MN3, and MN4 are turned on, and the gate voltages of MN1, MN5, and MN6 are pulled down to realize shutdown. The gate voltages of MP3, MP4, and MP5 are pulled up to VDD to achieve shutdown, and MP6 is turned on at the same time, so that the level of C2 is pulled up to VDD level by MP6 and R3, and there is no uncertain state. Thus, the entire circuit is re-entered into a low power consumption state.

以上运行过程通过脉冲延展单元实现了将输入的纳秒级的边缘脉冲的宽度延展生成微秒级的过零脉冲,以及通过光耦驱动单元实现了恒流源脉冲电流输出。需要说明的是,该延展宽度由MP5的偏置电流以及C2、C3的容值决定,调节MP5的偏置电流以及C2、C3的容值即可调节过零脉冲的宽度。The above operation process realizes that the width of the input nanosecond edge pulse is extended to generate a microsecond zero-crossing pulse through the pulse extension unit, and the constant current source pulse current output is realized through the optocoupler drive unit. It should be noted that the extension width is determined by the bias current of MP5 and the capacitances of C2 and C3, and the width of the zero-crossing pulse can be adjusted by adjusting the bias current of MP5 and the capacitances of C2 and C3.

在一优选实施例中,上述取电与交流整形单元中的R1为外接电阻,C1为外接电容。In a preferred embodiment, R1 in the above-mentioned power taking and AC shaping unit is an external resistor, and C1 is an external capacitor.

在一优选实施例中,上述光耦合器U4为外接光耦合器。In a preferred embodiment, the above-mentioned optical coupler U4 is an external optical coupler.

如图5所示,一种芯片,采用上述交流电过零点检测电路。As shown in FIG. 5 , a chip adopts the above-mentioned zero-crossing detection circuit of alternating current.

在一优选实施例中,该芯片采用上述交流电过零点检测电路,但该电路不包含上述的电阻R1、电容C1、光耦合器U4及电阻R5,电阻R1、电容C1、光耦合器U4及电阻R5作为外围元件电连接于该芯片。具体地,该芯片包括输入端IN、电源端VDD、接地端VSS及输出端OUT。该输入端IN即为上述交流电过零点检测电路中的U1的同相输入端,该电源端VDD即为U1的电源端及过零脉冲产生单元中MP1—MP8的源极,该接地端VSS即为U1的接地端及过零脉冲产生单元中MN2—MN9的源极,该输出端OUT即为过零脉冲产生单元中MN6的漏极。电阻R1的一端电连接于此芯片的输入端IN,电容C1的一端电连接于电源端VDD,电容C1的另一端电连接于接地端VSS,光耦合器U4的发光二极管的阳极电连接于电源端VDD,发光二极管的阴极电连接于输出端OUT,光耦合器U4的三极管的发射极接地,三极管的源极电连接电阻R5的一端,电阻R5另一端接低压系统的电源,三极管的源极与电阻R5之间用于输出过零脉冲。In a preferred embodiment, the chip adopts the above-mentioned alternating current zero-crossing detection circuit, but the circuit does not include the above-mentioned resistor R1, capacitor C1, optocoupler U4 and resistor R5, resistor R1, capacitor C1, optocoupler U4 and resistor. R5 is electrically connected to the chip as a peripheral element. Specifically, the chip includes an input terminal IN, a power supply terminal VDD, a ground terminal VSS and an output terminal OUT. The input terminal IN is the non-inverting input terminal of U1 in the above-mentioned AC zero-crossing point detection circuit, the power supply terminal VDD is the power supply terminal of U1 and the source of MP1-MP8 in the zero-crossing pulse generating unit, and the ground terminal VSS is The ground terminal of U1 and the source of MN2-MN9 in the zero-crossing pulse generating unit, the output terminal OUT is the drain of MN6 in the zero-crossing pulse generating unit. One end of the resistor R1 is electrically connected to the input terminal IN of the chip, one end of the capacitor C1 is electrically connected to the power supply terminal VDD, the other end of the capacitor C1 is electrically connected to the ground terminal VSS, and the anode of the light-emitting diode of the optocoupler U4 is electrically connected to the power supply Terminal VDD, the cathode of the light-emitting diode is electrically connected to the output terminal OUT, the emitter of the triode of the optocoupler U4 is grounded, the source of the triode is electrically connected to one end of the resistor R5, the other end of the resistor R5 is connected to the power supply of the low-voltage system, and the source of the triode It is used to output the zero-crossing pulse between it and the resistor R5.

在可选实施例中,R1的阻值为500K-3MΩ之间,C1的容值为100nF至470nF之间,C1取值越大,相应需要减小R1的阻值。In an optional embodiment, the resistance value of R1 is between 500K-3MΩ, and the capacitance value of C1 is between 100nF and 470nF. The larger the value of C1 is, the resistance value of R1 needs to be reduced accordingly.

在一实施例中,R1取2MΩ,C1取220nF。In one embodiment, R1 is 2MΩ, and C1 is 220nF.

在本发明的技术方案中,在芯片的基础上,外围电路仅需1个光耦,2个电阻和1个电容。外围电路极为简洁,使用时连接方便,且外围电路的功耗极低。以R1为2MΩ为例,本发明交流电过零点检测电路的功耗约为:220V*220V/2M=24.2mW,整体功耗较低。In the technical solution of the present invention, on the basis of the chip, the peripheral circuit only needs one optocoupler, two resistors and one capacitor. The peripheral circuit is extremely simple, the connection is convenient during use, and the power consumption of the peripheral circuit is extremely low. Taking R1 as 2MΩ as an example, the power consumption of the AC zero-crossing detection circuit of the present invention is about 220V*220V/2M=24.2mW, and the overall power consumption is low.

以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (10)

1. An alternating current zero-crossing detection circuit, characterized by comprising:
the power taking and alternating current shaping unit is used for generating square waves with the same frequency and phase based on alternating current;
the edge pulse generating unit is electrically connected with the power taking and alternating current shaping unit and is used for generating edge pulses at the alternating current zero crossing points based on the square waves;
a zero-crossing pulse generating unit electrically connected to the edge pulse generating unit for generating a zero-crossing pulse based on the edge pulse.
2. The alternating current zero-crossing detection circuit according to claim 1, wherein the zero-crossing pulse generating unit includes: the pulse extension unit is electrically connected with the edge pulse generation unit, the bias circuit unit is electrically connected with the pulse extension unit, and the optocoupler driving unit is electrically connected with the bias circuit unit and the pulse extension unit.
3. The alternating current zero-crossing detection circuit according to claim 2, wherein the zero-crossing pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8, resistors R2, R3 and R4, capacitors C2 and C3, NOT gates U2 and U3; the MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3 and R3 form a pulse extension unit; the MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2 and R4 form a bias circuit unit; MN4, MN5 and MN6 constitute an optocoupler drive unit.
4. The alternating current zero-crossing detection circuit according to claim 3, wherein the pulse extension unit comprises: the edge pulse circuit is electrically connected with the grid of MN7 and the grid of MN9, the drain of MN7 is electrically connected with the grid of MN8, the drain of MN7 is also electrically connected with one end of C2, the drain of MN9 is electrically connected with one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input terminal of U2, the output terminal of U2 is electrically connected to the input terminal of U3, and the output terminal of U3 is electrically connected to the gate of MP 6.
5. The alternating current zero-crossing detection circuit according to claim 4, wherein the bias circuit unit includes: the source electrode of the MP, the source electrode of the MP and the source electrode of the MP are electrically connected, the drain electrode of the MP, the grid electrode of the MP are electrically connected, the grid electrode of the MP is electrically connected with the output end of the U, the drain electrode of the MP is electrically connected with the drain electrode of the MN, the drain electrode of the MP is electrically connected with the grid electrode of the MN, the drain electrode of the MN is electrically connected with the drain electrode of the MN, the source electrode of the MN is electrically connected with the grid electrode of the MN, the source electrode of the MN is also electrically connected with one end of the R, the other end.
6. The alternating current zero crossing detection circuit of claim 5, wherein the optocoupler drive unit comprises a drain electrode of MN5 electrically connected to a gate electrode of MN5, a gate electrode of MN6, a drain electrode of MN4 and a drain electrode of MP4, a source electrode of MN5, a source electrode of MN6, a source electrode of MN4 and a source electrode of MN7, a gate electrode of MN4 electrically connected to an output terminal of U2, and a drain electrode of MN6 outputting the zero crossing pulse.
7. The alternating current zero-crossing detection circuit according to claim 1, wherein the power-taking and alternating current shaping unit comprises: the circuit comprises a resistor R1, diodes D1 and D2, a capacitor C1 and a comparator U1; one end of R1 is used for electrically connecting the alternating current, the other end of R1 is electrically connected with the non-inverting input end of U1, the non-inverting input end of U1 is also electrically connected with the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected with the power supply end of U1, the anode of D2, the grounding end of U1 and the inverting input end of U1 are electrically connected with each other and grounded, C1 is electrically connected between the power supply end and the grounding end of U1, and the output end of U1 outputs square waves with the same frequency and phase as the.
8. The alternating current zero-crossing detection circuit according to claim 7, wherein the edge pulse generating unit includes: an INV, a delay unit and an XOR; INV is electrically connected to the output end of the U1, the output ends of the INV are electrically connected to the first input end of the XOR and the input end of the delay unit respectively, the output end of the delay unit is electrically connected to the second input end of the XOR, and the output end of the XOR outputs the edge pulse.
9. The alternating current zero-crossing detection circuit of claim 1, further comprising an external optocoupler, wherein an anode of the light emitting diode in the optocoupler is electrically connected to a power supply terminal of U1, and a cathode of the light emitting diode is electrically connected to a drain of MN 6.
10. A chip, characterized in that, the alternating current zero crossing detection circuit of any one of claims 1 to 9 is adopted, wherein R1 in the electricity taking and alternating current shaping unit is an external resistor, and C1 is an external capacitor.
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