CN111650425A - A kind of alternating current zero-crossing detection circuit and chip - Google Patents

Abstract

The invention discloses an alternating current zero crossing point detection circuit and a chip, wherein the alternating current zero crossing point detection circuit comprises: the power taking and alternating current shaping unit is used for generating square waves with the same frequency and phase based on alternating current; the edge pulse generating unit is electrically connected with the power taking and alternating current shaping unit and is used for generating edge pulses at the alternating current zero crossing points based on the square waves; a zero-crossing pulse generating unit electrically connected to the edge pulse generating unit for generating a zero-crossing pulse based on the edge pulse. The invention can simultaneously detect the zero crossing point of the rising edge and the zero crossing point of the falling edge of the alternating current, and improves the precision of detecting the zero crossing point.

Description

A kind of alternating current zero-crossing detection circuit and chip

technical field

The invention relates to the technical field of alternating current zero-cross detection, in particular to an alternating current zero-cross detection circuit and a chip.

Background technique

The AC zero-crossing detection circuit is a common circuit in the fields of thyristor control circuit, high-power equipment or electrical appliance access, power carrier communication, and lighting control. In these fields, it is necessary to accurately detect the voltage zero-crossing point of the alternating current, generate a zero-crossing pulse or level signal at the zero-crossing point as a reference signal for system control, or obtain the alternating current cycle, voltage fluctuation, phase, etc. of the alternating current based on the zero-crossing detection signal. Related Information.

The current AC zero-crossing detection circuits are all based on discrete components. The circuit structure is complex, and the zero-crossing signal can only be generated on the rising or falling edge of the AC, such as patent numbers: CN103063904A and CN102508014A. But usually the system needs the zero-crossing signal of the rising edge and the falling edge of the alternating current. One way is to obtain the virtual zero-crossing detection signal of the other edge by calculation according to the zero-crossing detection signal of a single edge. However, the zero-crossing detection signal of another edge obtained by this kind of virtual does not actually detect another zero-crossing point, thus losing part of the information carried by the zero-crossing point, such as the zero-crossing point jitter caused by voltage fluctuation. Another approach is to use two identical circuits to detect the zero-crossing of the rising and falling edges respectively, but the cost, power consumption and complexity of the system are doubled.

In addition, the number of peripheral devices of the zero-crossing detection circuit based on discrete components is large. Due to the use of more current control devices such as diodes and triodes, the power consumption of its own loss is also large, generally requiring about 50-100mW. Another problem caused by many peripheral devices is that the detection accuracy is also damaged. Generally, the error between the detected zero-crossing point and the actual zero-crossing point is more than 20us.

Therefore, how to design a high-precision zero-crossing detection circuit capable of simultaneously detecting the zero-crossing points of the rising edge and the falling edge is a technical problem to be solved urgently in the industry.

SUMMARY OF THE INVENTION

In order to solve the technical problem of inaccurate detection of the zero-crossing points of the rising edge and the falling edge in the above-mentioned prior art, the present invention provides an alternating current zero-crossing point detection circuit and a chip.

The technical solution adopted in the present invention is to first provide an alternating current zero-crossing point detection circuit, including: a power taking and alternating current shaping unit, which is used for generating square waves of the same frequency and phase based on alternating current; an edge pulse generating unit, which is electrically connected to the a power taking and alternating current shaping unit for generating an edge pulse at the zero-crossing point of the alternating current based on the square wave; a zero-crossing pulse generating unit, which is electrically connected to the edge pulse generating unit for generating based on the edge pulse zero-crossing pulse.

In one embodiment, the zero-crossing pulse generating unit includes: a pulse stretching unit electrically connected to the edge pulse generating unit, a bias circuit unit electrically connected to the pulse stretching unit, and a bias circuit unit electrically connected to the biasing unit. The circuit unit and the optocoupler driving unit of the pulse stretching unit are arranged.

In one embodiment, the zero-crossing pulse generating unit includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7 , MP8, resistors R2, R3, R4, capacitors C2, C3, NOT gates U2, U3; the MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3, R3 constitute a pulse stretching unit; The MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2, R4 constitute the bias circuit unit; MN4, MN5, MN6 constitute the optocoupler driving unit.

In one embodiment, the pulse stretching unit includes: the edge pulse circuit is electrically connected to the gate of MN7 and the gate of MN9, the drain of MN7 is electrically connected to the gate of MN8, and the drain of MN7 is also electrically connected At one end of C2, the drain of MN9 is electrically connected to one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 The resistor R3 is electrically connected to the drain of MN7, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, The source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input of U2, the output of U2 is electrically connected to the input of U3, and the output of U3 is electrically connected to the gate of MP6.

In one embodiment, the bias circuit unit includes: the source of MP1, the source of MP2, the source of MP3, the source of MP4, the source of MP5 and the source of MP6 are electrically connected, and the drain of MP2 is electrically connected to the source of MP6. The pole, the drain of MP3, the gate of MP3, the gate of MP4, the gate of MP5 are electrically connected to each other, the gate of MP1 is electrically connected to the output terminal of U2, the gate of MP2 is electrically connected to the output terminal of U3, and the gate of MP5 is electrically connected to the output terminal of U2. The drain of MN1 is electrically connected to the drain of MN7, the drain of MP1 is electrically connected to the gate of MN1, the drain of MN2 and the drain of MN3 through the resistor R4, the drain of MN1 is electrically connected to the drain of MP3, and the drain of MN1 is electrically connected to the drain of MP3. The source is electrically connected to the gate of MN2, the source of MN1 is also electrically connected to one end of R2, the other end of R2, the source of MN2, and the source of MN3 are electrically connected to the source of MN7, and the gate of MN3 is electrically connected at the output of U2.

In one embodiment, the optocoupler driving unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, the source of MN5 and the source of MN6 The source of MN4 and the source of MN7 are electrically connected, the gate of MN4 is electrically connected to the output terminal of U2, and the drain of MN6 outputs the zero-crossing pulse.

In one embodiment, the power taking and AC shaping unit includes: a resistor R1, diodes D1, D2, a capacitor C1 and a comparator U1; one end of R1 is electrically connected to the AC power, and the other end of R1 is electrically connected to U1. Non-inverting input terminal, the non-inverting input terminal of U1 is also electrically connected to the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected to the power supply terminal of U1, the anode of D2, the ground terminal of U1 and the inverting input terminal of U1 are electrically connected to each other And grounded, C1 is electrically connected between the power supply terminal and the ground terminal of U1, and the output terminal of U1 outputs a square wave of the same frequency and phase as the alternating current.

In one embodiment, the edge pulse generating unit includes: an invertor INV, a delay unit and an exclusive OR gate XOR; INV is electrically connected to the output end of U1, and the output end of INV is electrically connected to the first input end of XOR and the XOR respectively. The input end of the delay unit and the output end of the delay unit are electrically connected to the second input end of the XOR, and the output end of the XOR outputs the edge pulse.

In one embodiment, R1 in the power taking and AC shaping unit is an external resistor, and C1 is an external capacitor.

In one embodiment, an external optocoupler is further included, wherein the anode of the light-emitting diode in the optocoupler is electrically connected to the power supply terminal of U1, and the cathode of the light-emitting diode is electrically connected to the drain of MN6.

The present invention also provides a chip, which adopts the above-mentioned alternating current zero-crossing detection circuit.

Compared with the prior art, the present invention has at least the following advantages.

By setting the power taking and AC shaping unit to generate a square wave with the same frequency and phase as the AC power, and generating the edge pulse through the edge pulse generating circuit, the zero-crossing point of the rising edge and the zero-crossing point of the falling edge of the AC power are detected at the same time, and the detection of the zero-crossing point is improved. accuracy. By setting the zero-crossing pulse generating circuit, the width of the edge pulse is extended to generate the zero-crossing pulse with the required width, and the adjustment of the zero-crossing pulse width is realized. Further, the AC zero-crossing detection circuit is integrated into one chip, which reduces the complexity of the peripheral circuit, makes the application more convenient, and reduces the energy consumption.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for the present invention. In some embodiments, for those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of a frame of an alternating current zero-crossing detection circuit according to an embodiment of the present invention;

Fig. 2 is the circuit schematic diagram of the power taking and AC shaping unit in Fig. 1;

3 is a schematic circuit diagram of an edge pulse generating unit in FIG. 1;

Fig. 4 is the circuit schematic diagram of the zero-crossing pulse generating unit in Fig. 1;

5 is an application schematic diagram of a chip integrating an alternating current zero-crossing detection circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a detection effect of detecting an alternating current zero-crossing point according to an embodiment of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

Thus, a reference to a feature in this specification will be used to describe one of the features of an embodiment of the invention and not to imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes a number of features. Although certain features may be combined together to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Thus, unless otherwise stated, the combinations described are not intended to be limiting.

The principle and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

As shown in FIG. 1 , the present invention provides an alternating current zero-crossing detection circuit, which is used to obtain the information of alternating current zero-crossing. The alternating current zero-crossing point detection circuit includes: a power-taking and alternating-current shaping unit, an edge pulse generating unit, and a zero-crossing pulse generating unit that are electrically connected in sequence. Wherein, the power taking and AC shaping unit is used to electrically connect the AC power to be detected, and generate square waves of the same frequency and phase based on the AC power. The edge pulse generating unit is used for generating edge pulses at the zero-crossing point of the alternating current based on the square wave. The zero-crossing pulse generating unit is used for generating a zero-crossing pulse based on the edge pulse, and the zero-crossing pulse is the information about the zero-crossing point of the alternating current that needs to be obtained through the technical solution of the present invention.

Compared with the traditional zero-crossing detection scheme based on discrete components, the technical scheme of the present invention can simultaneously detect the zero-crossing point of the rising edge of the AC and the zero-crossing point of the falling edge (refer to the schematic diagram of the detection effect in FIG. 6 ), and the circuit structure is simple, Low cost and high detection accuracy.

Each part of the AC zero-crossing detection circuit of the present invention will be described in detail below.

As shown in Figure 2, the power taking and AC shaping unit includes: resistor R1, diodes D1, D2, capacitor C1 and comparator U1. One end of R1 is used to electrically connect the alternating current to be detected, and the other end of R1 is electrically connected to the non-inverting input end of U1. The non-inverting input terminal of U1 is also electrically connected to the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected to the power supply terminal of U1, the anode of D2, the ground terminal of U1 and the inverting input terminal of U1 are electrically connected to each other and grounded, D1 With D2 as the ESD protection diode of the input port, the ESD protection of the port is realized, and half-wave rectification is realized at the same time. C1 is electrically connected between the power supply terminal and the ground terminal of U1, and the output terminal of U1 outputs a square wave with the same frequency and phase as the alternating current. R1 can be a series or parallel connection of multiple resistors. Preferably, D2 is a Zener diode. The comparison threshold of U1 is set to 0V. When the input AC power crosses zero, the output level of the comparator output is reversed, thereby realizing the shaping of the AC power and generating a square wave output with the same frequency and phase as the input AC power. Since the comparison threshold of U1 is 0V, there is almost no delay between the zero-crossing pulse and the actual zero-crossing point, so it has extremely high detection accuracy.

As shown in FIG. 3 , the edge pulse generating unit is electrically connected to the power taking and AC shaping unit, and is used for receiving square waves and generating edge pulses based on the square waves. The edge pulse generating unit includes: a NOT gate INV, a delay unit and an exclusive OR gate XOR; INV is electrically connected to the output end of U1, and the output end of INV is electrically connected to the first input end of XOR and the input end of the delay unit respectively, and the delay unit The output terminal of the XOR is electrically connected to the second input terminal of the XOR, and the output terminal of the XOR outputs the edge pulse. The delay unit is composed of an even number of NOT gates in series, and the delay unit is used to delay the square wave at the output end of U1. When the level of the input square wave is inverted, the first input terminal and the second input terminal of the exclusive OR gate XOR will generate an edge pulse with the same width as the delay time generated by the delay unit at the output terminal due to different delays. The width of the edge pulse is in nanoseconds, and the general requirement for the width of the zero-crossing pulse is in the order of microseconds to milliseconds, so the width of the edge pulse needs to be extended to meet the requirements.

As shown in FIG. 4 , the zero-crossing pulse generating unit is connected to the edge pulse generating unit, and is used for receiving the edge pulse and extending the width of the edge pulse to generate the zero-crossing pulse. The zero-crossing pulse generating unit includes: a pulse extending unit electrically connected to the edge pulse generating unit, a bias circuit unit electrically connected to the pulse extending unit, and an optocoupler driving unit electrically connected to the bias circuit unit and the pulse extending unit.

Specifically, the zero-crossing pulse generating unit includes: NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, and resistor R2 , R3, R4, capacitors C2, C3, NOT gates U2, U3; MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3, R3 constitute a pulse extension unit; MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2, R4 constitute the bias circuit unit; MN4, MN5, MN6 constitute the optocoupler drive unit. The sources of NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9 are connected to each other, and the sources of PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8 are connected to each other. The more specific circuit connection relationship is as follows:

More specifically, the pulse stretching unit realizes the width extension of the edge pulse, and the pulse stretching unit includes: the edge pulse circuit is electrically connected to the gate of MN7 and the gate of MN9, the drain of MN7 is electrically connected to the gate of MN8, and the drain of MN7 is electrically connected to the gate of MN8. The pole is also electrically connected to one end of C2, the drain of MN9 is electrically connected to one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; The drain of MP6 is electrically connected to the drain of MN7 through resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, MP6 The source of MP7 and the source of MP8 are electrically connected to each other, the drain of MP7 is also electrically connected to the input of U2, the output of U2 is electrically connected to the input of U3, and the output of U3 is electrically connected to the gate of MP6 pole.

The bias circuit unit provides current bias for the pulse extension unit and the optocoupler drive unit. The bias circuit unit includes: the source of MP1, the source of MP2, the source of MP3, the source of MP4, the source of MP5 and the source of MP6. The source is electrically connected, the drain of MP2, the drain of MP3, the gate of MP3, the gate of MP4, the gate of MP5 are electrically connected, the gate of MP1 is electrically connected to the output terminal of U2, the gate of MP2 is electrically connected It is electrically connected to the output terminal of U3, the drain of MP5 is electrically connected to the drain of MN7, the drain of MP1 is electrically connected to the gate of MN1, the drain of MN2 and the drain of MN3 through the resistor R4, and the drain of MN1 is electrically connected to the drain of MN1. It is connected to the drain of MP3, the source of MN1 is electrically connected to the gate of MN2, the source of MN1 is also electrically connected to one end of R2, the other end of R2, the source of MN2 and the source of MN3 are electrically connected to the source of MN7. The source, the gate of MN3 is electrically connected to the output terminal of U2.

The optocoupler drive unit is used as a constant current source output circuit driven by the optocoupler. The optocoupler drive unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, The source of MN5, the source of MN6, the source of MN4 and the source of MN7 are electrically connected to each other, the gate of MN4 is electrically connected to the output terminal of U2, and the drain of MN6 outputs a zero-crossing pulse. The drain of MN6 is the constant current output port, and the constant current source output can realize the fast opening of the optocoupler and reduce the delay of the optocoupler.

The AC zero-crossing detection circuit also includes an external optical coupler U4, which is composed of light-emitting diodes and triodes. The anode of the light-emitting diode is electrically connected to the power supply terminal of U1, and the cathode of the light-emitting diode is electrically connected to the drain of MN6. The emitter of the triode is grounded, and the collector of the triode is electrically connected to the resistor R5 and then connected to the power supply.

The operation process of the above zero-crossing pulse generating unit is briefly described below.

When the input edge pulse is high level, MN7 will quickly release the charge in C2, and make the output ENB signal of NOT gate U2 be low level, and the output EN signal of NOT gate U3 will be high level. The EN signal and the ENB signal are the enable signals of the entire circuit. When the EN signal is at high level, the bias circuit unit starts to work, provides bias for the entire circuit, and drives the optocoupler unit to output milliamp current from the drain of MN6 to drive the light-emitting diode of the optocoupler to emit light. At this time, MP1, MN1, and MN2 are turned on, and MP2, MN3, and MN4 are turned off. R4 provides uA (microampere) level current for MN2. The width and length of MN2 are relatively large, so its VGS voltage is approximately equal to its threshold voltage VTH, so that the current passing through R2 is stabilized at about VTH/R2. The current through R2 is independent of the supply voltage and serves as the current reference for the entire circuit. The current mirror composed of MP3, MP4, and MP5 directly replicates the current of R2, and the current mirror composed of MN5 and MN6 replicates the current of MP4.

When the input edge pulse is low, MN7 will be turned off, but because the voltage of C2 capacitor is 0 at this time, the EN signal and ENB signal will not change state immediately when MN7 starts to turn off. At this time, the voltage of C2 is due to the nanoamp charging current provided by MP5, and the voltage of C2 will gradually increase with time. When it rises to the turn-on voltage of MN8, MN8 starts to conduct, thus turning on MP8, and MP8 starts to charge C3. , when C3 level rises gradually, close MP7, and make U2 output ENB signal and U3 output EN signal level inversion, restore to the working state before edge pulse is not input.

When the states of EN and ENB are restored, the bias current and the optocoupler constant current drive output are turned off. At this time, MP1 is turned off, MP2, MN3, and MN4 are turned on, and the gate voltages of MN1, MN5, and MN6 are pulled down to realize shutdown. The gate voltages of MP3, MP4, and MP5 are pulled up to VDD to achieve shutdown, and MP6 is turned on at the same time, so that the level of C2 is pulled up to VDD level by MP6 and R3, and there is no uncertain state. Thus, the entire circuit is re-entered into a low power consumption state.

The above operation process realizes that the width of the input nanosecond edge pulse is extended to generate a microsecond zero-crossing pulse through the pulse extension unit, and the constant current source pulse current output is realized through the optocoupler drive unit. It should be noted that the extension width is determined by the bias current of MP5 and the capacitances of C2 and C3, and the width of the zero-crossing pulse can be adjusted by adjusting the bias current of MP5 and the capacitances of C2 and C3.

In a preferred embodiment, R1 in the above-mentioned power taking and AC shaping unit is an external resistor, and C1 is an external capacitor.

In a preferred embodiment, the above-mentioned optical coupler U4 is an external optical coupler.

As shown in FIG. 5 , a chip adopts the above-mentioned zero-crossing detection circuit of alternating current.

In a preferred embodiment, the chip adopts the above-mentioned alternating current zero-crossing detection circuit, but the circuit does not include the above-mentioned resistor R1, capacitor C1, optocoupler U4 and resistor R5, resistor R1, capacitor C1, optocoupler U4 and resistor. R5 is electrically connected to the chip as a peripheral element. Specifically, the chip includes an input terminal IN, a power supply terminal VDD, a ground terminal VSS and an output terminal OUT. The input terminal IN is the non-inverting input terminal of U1 in the above-mentioned AC zero-crossing point detection circuit, the power supply terminal VDD is the power supply terminal of U1 and the source of MP1-MP8 in the zero-crossing pulse generating unit, and the ground terminal VSS is The ground terminal of U1 and the source of MN2-MN9 in the zero-crossing pulse generating unit, the output terminal OUT is the drain of MN6 in the zero-crossing pulse generating unit. One end of the resistor R1 is electrically connected to the input terminal IN of the chip, one end of the capacitor C1 is electrically connected to the power supply terminal VDD, the other end of the capacitor C1 is electrically connected to the ground terminal VSS, and the anode of the light-emitting diode of the optocoupler U4 is electrically connected to the power supply Terminal VDD, the cathode of the light-emitting diode is electrically connected to the output terminal OUT, the emitter of the triode of the optocoupler U4 is grounded, the source of the triode is electrically connected to one end of the resistor R5, the other end of the resistor R5 is connected to the power supply of the low-voltage system, and the source of the triode It is used to output the zero-crossing pulse between it and the resistor R5.

In an optional embodiment, the resistance value of R1 is between 500K-3MΩ, and the capacitance value of C1 is between 100nF and 470nF. The larger the value of C1 is, the resistance value of R1 needs to be reduced accordingly.

In one embodiment, R1 is 2MΩ, and C1 is 220nF.

In the technical solution of the present invention, on the basis of the chip, the peripheral circuit only needs one optocoupler, two resistors and one capacitor. The peripheral circuit is extremely simple, the connection is convenient during use, and the power consumption of the peripheral circuit is extremely low. Taking R1 as 2MΩ as an example, the power consumption of the AC zero-crossing detection circuit of the present invention is about 220V*220V/2M=24.2mW, and the overall power consumption is low.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (10)

1. An alternating current zero-crossing detection circuit, characterized by comprising:

the power taking and alternating current shaping unit is used for generating square waves with the same frequency and phase based on alternating current;

the edge pulse generating unit is electrically connected with the power taking and alternating current shaping unit and is used for generating edge pulses at the alternating current zero crossing points based on the square waves;

a zero-crossing pulse generating unit electrically connected to the edge pulse generating unit for generating a zero-crossing pulse based on the edge pulse.

2. The alternating current zero-crossing detection circuit according to claim 1, wherein the zero-crossing pulse generating unit includes: the pulse extension unit is electrically connected with the edge pulse generation unit, the bias circuit unit is electrically connected with the pulse extension unit, and the optocoupler driving unit is electrically connected with the bias circuit unit and the pulse extension unit.

3. The alternating current zero-crossing detection circuit according to claim 2, wherein the zero-crossing pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 and MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8, resistors R2, R3 and R4, capacitors C2 and C3, NOT gates U2 and U3; the MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3 and R3 form a pulse extension unit; the MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2 and R4 form a bias circuit unit; MN4, MN5 and MN6 constitute an optocoupler drive unit.

4. The alternating current zero-crossing detection circuit according to claim 3, wherein the pulse extension unit comprises: the edge pulse circuit is electrically connected with the grid of MN7 and the grid of MN9, the drain of MN7 is electrically connected with the grid of MN8, the drain of MN7 is also electrically connected with one end of C2, the drain of MN9 is electrically connected with one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input terminal of U2, the output terminal of U2 is electrically connected to the input terminal of U3, and the output terminal of U3 is electrically connected to the gate of MP 6.

5. The alternating current zero-crossing detection circuit according to claim 4, wherein the bias circuit unit includes: the source electrode of the MP, the source electrode of the MP and the source electrode of the MP are electrically connected, the drain electrode of the MP, the grid electrode of the MP are electrically connected, the grid electrode of the MP is electrically connected with the output end of the U, the drain electrode of the MP is electrically connected with the drain electrode of the MN, the drain electrode of the MP is electrically connected with the grid electrode of the MN, the drain electrode of the MN is electrically connected with the drain electrode of the MN, the source electrode of the MN is electrically connected with the grid electrode of the MN, the source electrode of the MN is also electrically connected with one end of the R, the other end.

6. The alternating current zero crossing detection circuit of claim 5, wherein the optocoupler drive unit comprises a drain electrode of MN5 electrically connected to a gate electrode of MN5, a gate electrode of MN6, a drain electrode of MN4 and a drain electrode of MP4, a source electrode of MN5, a source electrode of MN6, a source electrode of MN4 and a source electrode of MN7, a gate electrode of MN4 electrically connected to an output terminal of U2, and a drain electrode of MN6 outputting the zero crossing pulse.

7. The alternating current zero-crossing detection circuit according to claim 1, wherein the power-taking and alternating current shaping unit comprises: the circuit comprises a resistor R1, diodes D1 and D2, a capacitor C1 and a comparator U1; one end of R1 is used for electrically connecting the alternating current, the other end of R1 is electrically connected with the non-inverting input end of U1, the non-inverting input end of U1 is also electrically connected with the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected with the power supply end of U1, the anode of D2, the grounding end of U1 and the inverting input end of U1 are electrically connected with each other and grounded, C1 is electrically connected between the power supply end and the grounding end of U1, and the output end of U1 outputs square waves with the same frequency and phase as the.

8. The alternating current zero-crossing detection circuit according to claim 7, wherein the edge pulse generating unit includes: an INV, a delay unit and an XOR; INV is electrically connected to the output end of the U1, the output ends of the INV are electrically connected to the first input end of the XOR and the input end of the delay unit respectively, the output end of the delay unit is electrically connected to the second input end of the XOR, and the output end of the XOR outputs the edge pulse.

9. The alternating current zero-crossing detection circuit of claim 1, further comprising an external optocoupler, wherein an anode of the light emitting diode in the optocoupler is electrically connected to a power supply terminal of U1, and a cathode of the light emitting diode is electrically connected to a drain of MN 6.

10. A chip, characterized in that, the alternating current zero crossing detection circuit of any one of claims 1 to 9 is adopted, wherein R1 in the electricity taking and alternating current shaping unit is an external resistor, and C1 is an external capacitor.

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