CN111628793B - UWB ultra wide band receiving baseband SOC system on chip based on ASIP - Google Patents
UWB ultra wide band receiving baseband SOC system on chip based on ASIP Download PDFInfo
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- H—ELECTRICITY
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
Abstract
The invention discloses an SOC (system on chip) of an UWB (ultra wideband) receiving baseband based on ASIP (advanced application protocol), which comprises a data processing system jointly constructed by a front-end data flow co-processing unit and an ASIP (advanced application protocol) processing unit, wherein the front-end data flow co-processing unit acquires an UWB signal data flow, a lead code preprocessing module in the front-end data flow co-processing unit calculates the data flow to obtain a maximum correlation value, a minimum correlation value and a maximum correlation value position, and a data decoding preprocessing module decodes PHR (phase shift register) and PSDU (Power System Unit) parts of data frames in the data flow; and the scalar processing unit and the vector processing unit of the ASIP decode the decoded preprocessed data to obtain PHR and PSDU parts of data frames in the data stream. The invention ensures the high performance and low power consumption of the chip and can be quickly and flexibly realized in ASIP.
Description
Technical Field
The invention relates to the field of UWB baseband chip data processing systems, in particular to an SOC (system on chip) of a UWB (ultra wide band) receiving baseband based on ASIP (advanced application protocol).
Background
With the development of UWB technology, UWB technology is becoming the mainstream technical solution for indoor high-precision positioning. The industry standard of UWB has also changed, and IEEE 802.15.4z agreement has defined new characteristic on original standard basis, can promote safety, the consumption is lower, and transmission distance is farther. The new protocol puts higher demands on the design of the UWB receiver, higher speed and lower power consumption, and simultaneously, due to the continuous development of the UWB industry standard, the design flexibility of the new receiver is also required to be higher.
The existing UWB receiver architecture is generally a data stream processing system formed by a front-end data stream co-processing unit and an MCU or DSP. ASICs are computationally efficient but are not flexible enough to quickly support iterative updates of new algorithms. On the other hand, the flexibility of the MCU or DSP is high and programmable, but it is difficult to achieve high performance and low power consumption at the same time.
An ASIP processing unit (Application Specific Instruction set Processor) is used as a programmable and customizable Processor architecture, and compared with a general MCU or DSP, the ASIP processing unit can customize and clip a Processor according to algorithm requirements and expand or delete an Instruction set aiming at a Specific Application scene of a UWB receiving baseband, so that the ASIP processing unit consumes lower power while obtaining higher performance than a general MCU or DSP; compared with ASIC, ASIP is used as a processor, the algorithm can be realized by software, compared with ASIC, RTL development is faster and more flexible, and the requirement of UWB new protocol can be supported quickly. The baseband chip of the UWB receiver can thus be constructed using ASIP.
Disclosure of Invention
The invention aims to provide an SOC (system on chip) of an ASIP (application specific integrated circuit) UWB (ultra-wideband) receiving baseband, which aims to solve the problem that a UWB receiver baseband chip with an ASIC (application specific integrated circuit) plus MCU (micro control unit) or DSP (digital signal processor) framework in the prior art is difficult to realize both flexible algorithm realization and low power consumption.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
UWB ultra wide band receiving baseband SOC system on chip based on ASIP, its characterized in that: the ultra-wideband signal preprocessing method comprises a front-end data flow co-processing unit constructed by an ASIC (application specific integrated circuit) processing unit, wherein the data input end of the front-end data flow co-processing unit is connected with the radio frequency analog front end of an ultra-wideband receiver through a high-speed serial-parallel conversion interface, and the front-end data flow co-processing unit acquires and preprocesses ultra-wideband signal data flow from the radio frequency analog front end of the ultra-wideband receiver;
the front-end data flow co-processing unit is internally programmed with a preamble detection preprocessing module and a data decoding preprocessing module, wherein the preamble detection preprocessing module presets a preamble, and the preamble detection preprocessing module in the front-end data flow co-processing unit carries out correlation operation preprocessing on the ultra-wideband signal data flow and the preset preamble to obtain the positions of a maximum correlation value, a minimum correlation value and a maximum correlation value; the data decoding preprocessing module carries out decoding preprocessing on a physical layer header and a physical layer service data unit part of a data frame in the ultra-wideband signal data stream;
the data output end of the front-end data flow co-processing unit is also connected with an FIFO memory, and the preprocessing result data of the front-end data flow co-processing unit, the data decoding preprocessing module and the front-end data flow co-processing unit are respectively written into and stored in the FIFO memory;
the system also comprises a back-end data stream processing unit constructed by the ASIP processing unit, wherein the data input end of the ASIP processing unit is connected with the FIFO memory, the interrupt signal input end of the ASIP processing unit is connected with the interrupt signal output end of the front-end data stream co-processing unit, the ASIP processing unit is additionally provided with a vector processing unit and a scalar processing unit, a vector instruction set is added on the basis of the original RISC instruction set of the ASIP processing unit through the vector processing unit, and a scalar instruction set is added on the basis of the original RISC instruction set of the ASIP processing unit through the scalar processing unit;
the ASIP processing unit is internally programmed with a UWB MAC layer scheduling module, a lead code detection post-processing module and a data decoding post-processing module, receives interrupt signals from a lead detection preprocessing module and a data decoding preprocessing module in the front-end data flow co-processing unit and enters an interrupt service program, and reads the positions of the maximum correlation value, the minimum correlation value and the maximum correlation value which are obtained by preprocessing the lead detection preprocessing module and the physical layer header and the physical layer service data unit part of a data frame which is obtained by decoding preprocessing of the data decoding preprocessing module from an FIFO memory; a lead code detection post-processing module in the ASIP processing unit calls a scalar instruction set of a scalar processing unit through a UWB MAC layer scheduling module to calculate time information, signal-to-noise ratio information and signal pulse information of the ultra-wideband signal according to the maximum correlation value, the minimum correlation value and the position of the maximum correlation value; and a data decoding post-processing module in the ASIP processing unit calls a scalar instruction set of the scalar processing unit and a vector instruction set of the vector processing unit simultaneously through a UWB MAC layer scheduling module so as to decode a physical layer header and a physical layer service data unit part of the data frame subjected to decoding preprocessing, and further obtain the physical layer header and the physical layer service data unit part of the data frame in the ultra-wideband signal data stream.
The UWB ultra wide band receiving baseband SOC system on chip based on the ASIP is characterized in that: the clock input end of the ASIP processing unit is connected with the clock output end of the front-end data flow co-processing unit, and the ASIP processing unit receives the clock signal of the front-end data flow co-processing unit so as to realize the clock synchronization of the front-end data flow co-processing unit and the ASIP processing unit.
The UWB ultra wide band receiving baseband SOC system on chip based on the ASIP is characterized in that: the front-end data flow co-processing unit comprises a front detection preprocessing module, a front detection preprocessing module and a position acquisition module, wherein the front detection preprocessing module comprises a correlation operation submodule and a position acquisition submodule, the correlation operation submodule carries out correlation operation preprocessing on the ultra-wideband signal data flow and a preset lead code to obtain a maximum correlation value and a minimum correlation value, and the position acquisition submodule acquires the position of the maximum correlation value so as to finish the correlation operation preprocessing.
The UWB ultra wide band receiving baseband SOC system on chip based on the ASIP is characterized in that: the data decoding preprocessing module in the front-end data stream co-processing unit consists of an accumulation operation submodule and a rake submodule, wherein the accumulation operation submodule accumulates a physical layer header of a data frame in the ultra-wideband signal data stream and a physical layer service data unit part, and the rake submodule performs rake receiver processing for resisting multipath fading on an accumulation result so as to finish decoding preprocessing.
The UWB ultra wide band receiving baseband SOC system on chip based on the ASIP is characterized in that: scalar processing units in the ASIP processing units comprise arithmetic logic units, multiply-accumulate processing units, SECDED processing units, CORDIC processing units and finite field operation units, arithmetic logic instructions are added to the scalar processing units through the arithmetic logic units, multiply-accumulate instructions are added through the multiply-accumulate processing units, SECDED instructions are added through the SECDED processing units, CORDIC instructions are added through the CORDIC processing units, finite field operation instructions are added through the finite field operation units, and scalar instruction sets are formed by the arithmetic logic instructions, the multiply-accumulate instructions, the SECDED instructions, the CORDIC instructions and the finite field operation instructions;
and a lead code detection post-processing module in the ASIP processing unit calls a CORDIC instruction, a multiply-accumulate instruction and an arithmetic logic instruction of a scalar processing unit through a UWB MAC layer scheduling module so as to calculate the maximum correlation value, the minimum correlation value and the position of the maximum correlation value, and obtain time information, signal-to-noise ratio information and signal pulse information of the ultra-wideband signal.
The UWB ultra wide band receiving baseband SOC system on chip based on the ASIP is characterized in that: the Vector processing unit in the ASIP processing unit comprises an 8-bit arithmetic logic unit ALU, a 16-bit arithmetic logic unit ALU, a 128-bit arithmetic logic unit ALU and a Vector finite field processing unit, wherein the Vector processing unit adds an 8-bit arithmetic logic instruction through the 8-bit arithmetic logic unit ALU, adds a 16-bit arithmetic logic instruction through the 16-bit arithmetic logic unit ALU, adds a 128-bit arithmetic logic instruction through the 128-bit arithmetic logic unit ALU and adds a Vector finite field processing instruction through the Vector finite field processing unit, and a Vector instruction set is formed by the 8-bit arithmetic logic instruction, the 16-bit arithmetic logic instruction, the 128-bit arithmetic logic instruction and the Vector finite field processing instruction;
a data decoding post-processing module in the ASIP processing unit calls an SECDED instruction of a scalar processing unit through a UWB MAC layer scheduling module so as to perform SECDED decoding on a physical layer header and a physical layer service data unit part of a data frame subjected to decoding preprocessing; a data decoding post-processing module in the ASIP processing unit calls a finite field operation instruction of a scalar processing unit through a UWB MAC layer scheduling module, and an 8-bit arithmetic logic instruction, a 16-bit arithmetic logic instruction, a 128-bit arithmetic logic instruction and a vector finite field processing instruction in a vector processing unit so as to perform viterbi decoding and Reed-Solomon decoding on a physical layer header and a physical layer service data unit part of a data frame subjected to decoding preprocessing; and obtaining a physical layer header and a physical layer service data unit part of a data frame in the ultra-wideband signal data stream after SECDED decoding, viterbi decoding and Reed-Solomon decoding.
The UWB ultra wide band receiving baseband SOC system on chip based on the ASIP is characterized in that: the ASIP processing unit is internally programmed with a spi boot module, the data input end of the ASIP processing unit is connected with a flash memory, and the ASIP processing unit is started through the flash memory and the spi boot module.
The UWB ultra wide band receiving baseband SOC system on chip based on the ASIP is characterized in that: the data input end and the data output end of the ASIP processing unit are connected with a JTAG module, and the test of the ASIP processing unit is realized by the JTAG module.
The invention adopts the architecture of a front-end data flow co-processing unit formed by an ASIC processing unit and ASIP to design the baseband chip of the ultra-wideband receiver, the modules with sensitive power consumption, high processing speed requirement and fixed algorithm in the ultra-wideband receiver are realized in the front-end data flow co-processing unit, and the algorithms with higher flexibility, such as SECDED decoding, viterbi decoding, reed-solomon decoding and the like, are realized in the ASIP, thereby not only ensuring the high performance and low power consumption of the chip, but also realizing the newly derived algorithm on the ASIP quickly and flexibly.
Drawings
Fig. 1 is a system architecture diagram of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in fig. 1, the system on chip of UWB ultra-wideband receiving baseband SOC based on ASIP includes a front-end data stream co-processing unit constructed by an ASIC processing unit, a data input end of the front-end data stream co-processing unit is connected to a radio frequency analog front end of an ultra-wideband receiver through a high-speed serial-parallel conversion interface, wherein the high-speed serial-parallel conversion interface divides a high-speed ultra-wideband signal data stream at the radio frequency analog front end of the ultra-wideband receiver into multiple data streams with the same frequency, and then sends the data streams to the front-end data stream co-processing unit for preprocessing.
The front-end data flow co-processing unit is internally programmed with a preamble detection preprocessing module and a data decoding preprocessing module, wherein the preamble detection preprocessing module presets a preamble, and the preamble detection preprocessing module in the front-end data flow co-processing unit carries out correlation operation preprocessing on the ultra-wideband signal data flow and the preset preamble to obtain the positions of a maximum correlation value, a minimum correlation value and a maximum correlation value; the data decoding preprocessing module performs decoding preprocessing on the physical layer header (i.e., PHR)) and the physical layer service data unit (i.e., PSDU) of the data frame in the ultra-wideband signal data stream.
Specifically, a preamble detection preprocessing module in the front-end data stream co-processing unit is composed of a correlation operation submodule and a position acquisition submodule, wherein the correlation operation submodule performs correlation operation preprocessing on the ultra-wideband signal data stream and a preset preamble to obtain a maximum correlation value and a minimum correlation value, and the position acquisition submodule acquires the position of the maximum correlation value, thereby completing the correlation operation preprocessing.
The data decoding preprocessing module in the front-end data stream co-processing unit is composed of an accumulation operation submodule and a rake submodule, wherein the accumulation operation submodule accumulates a physical layer header of a data frame in the ultra-wideband signal data stream and a physical layer service data unit part, and the rake submodule performs rake receiver processing which resists multipath fading on an accumulation result so as to finish decoding preprocessing.
The data output end of the front-end data flow co-processing unit is also connected with an FIFO memory, and the preprocessing result data of the front-end data flow co-processing unit, the data decoding preprocessing module are written into the FIFO memory and stored in the FIFO memory.
The system also comprises a back-end data stream processing unit constructed by the ASIP processing unit, wherein the data input end of the ASIP processing unit is connected with the FIFO memory. The interrupt signal input end of the ASIP processing unit is connected with the interrupt signal output end of the front-end data flow co-processing unit. The clock input end of the ASIP processing unit is connected with the clock output end of the front-end data flow co-processing unit, and the ASIP processing unit receives the clock signal of the front-end data flow co-processing unit so as to realize the clock synchronization of the front-end data flow co-processing unit and the ASIP processing unit. The ASIP processing unit is internally programmed with a spi boot module, the data input end of the ASIP processing unit is connected with a flash memory, and the ASIP processing unit is started through the flash memory and the spi boot module. The data input end and the data output end of the ASIP processing unit are connected with a JTAG module, and the test of the ASIP processing unit is realized by the JTAG module.
The ASIP processing unit is a dedicated processor designed for the application scenario of UWB receive baseband, and further calculates the preprocessing result of the data stream coprocessor to obtain the final processing result. The ASIP processing unit adds a UWB extension instruction set on the basis of a RISC instruction set, wherein the UWB extension instruction set comprises a vector instruction set and a scalar instruction set. Correspondingly, a vector processing unit and a scalar processing unit which correspond to the instructions are added in the ASIP.
Specifically, in the ASIP processing unit, a vector instruction set is added on the basis of the original RISC instruction set of the ASIP processing unit through the vector processing unit, and a scalar instruction set is added on the basis of the original RISC instruction set of the ASIP processing unit through the scalar processing unit. The ASIP processing unit is internally programmed with a UWB MAC layer scheduling module, a lead code detection post-processing module and a data decoding post-processing module, receives interrupt signals from a lead detection preprocessing module and a data decoding preprocessing module in the front-end data flow co-processing unit and enters an interrupt service program, and reads the positions of the maximum correlation value, the minimum correlation value and the maximum correlation value which are obtained by preprocessing the lead detection preprocessing module and the physical layer header and the physical layer service data unit part of a data frame which is obtained by decoding preprocessing of the data decoding preprocessing module from an FIFO memory; a lead code detection post-processing module in the ASIP processing unit calls a scalar instruction set of a scalar processing unit through a UWB MAC layer scheduling module to calculate time information, signal-to-noise ratio information and signal pulse information of the ultra-wideband signal according to the maximum correlation value, the minimum correlation value and the position of the maximum correlation value; the data decoding post-processing module in the ASIP processing unit calls a scalar instruction set of the scalar processing unit and a vector instruction set of the vector processing unit simultaneously through a UWB MAC layer scheduling module so as to decode a physical layer header and a physical layer service data unit part of a data frame subjected to decoding preprocessing, and further obtain the physical layer header and the physical layer service data unit part of the data frame in the ultra-wideband signal data stream, wherein:
a scalar processing unit in the ASIP processing unit comprises an arithmetic logic unit, a multiply-accumulate processing unit, an SECDED processing unit, a CORDIC processing unit and a finite field operation unit, wherein arithmetic logic instructions are added to the scalar processing unit through the arithmetic logic unit, multiply-accumulate instructions are added through the multiply-accumulate processing unit, SECDED instructions are added through the SECDED processing unit, CORDIC instructions are added through the CORDIC processing unit, finite field operation instructions are added through the finite field operation unit, and a scalar instruction set is formed by the arithmetic logic instructions, the multiply-accumulate instructions, the SECDED instructions, the CORDIC instructions and the finite field operation instructions;
and a lead code detection post-processing module in the ASIP processing unit calls a CORDIC instruction, a multiply-accumulate instruction and an arithmetic logic instruction of a scalar processing unit through a UWB MAC layer scheduling module so as to calculate the maximum correlation value, the minimum correlation value and the position of the maximum correlation value, and obtain time information, signal-to-noise ratio information and signal pulse information of the ultra-wideband signal.
The vector processing unit in the ASIP processing unit comprises an 8-bit arithmetic logic unit ALU, a 16-bit arithmetic logic unit ALU, a 128-bit arithmetic logic unit ALU and a vector finite field processing unit, wherein the vector processing unit adds 8-bit arithmetic logic instructions through the 8-bit arithmetic logic unit ALU, 16-bit arithmetic logic instructions through the 16-bit arithmetic logic unit ALU, 128-bit arithmetic logic instructions through the 128-bit arithmetic logic unit ALU and vector finite field processing instructions through the vector finite field processing unit, and a vector instruction set is formed by the 8-bit arithmetic logic instructions, the 16-bit arithmetic logic instructions, the 128-bit arithmetic logic instructions and the vector finite field processing instructions;
a data decoding post-processing module in the ASIP processing unit calls an SECDED instruction of a scalar processing unit through a UWB MAC layer scheduling module so as to perform SECDED decoding on a physical layer header and a physical layer service data unit part of a data frame subjected to decoding preprocessing; a data decoding post-processing module in the ASIP processing unit calls a finite field operation instruction of a scalar processing unit through a UWB MAC layer scheduling module, and an 8-bit arithmetic logic instruction, a 16-bit arithmetic logic instruction, a 128-bit arithmetic logic instruction and a vector finite field processing instruction in a vector processing unit so as to perform viterbi decoding and Reed-Solomon decoding on a physical layer header and a physical layer service data unit part of a data frame subjected to decoding preprocessing; and obtaining a physical layer header and a physical layer service data unit part of a data frame in the ultra-wideband signal data stream after SECDED decoding, viterbi decoding and Reed-Solomon decoding.
In the present invention, the ASIP processing unit is implemented using an ASIP designer tool design by Synopsys, inc. A special UWB receiver ASIP processing unit is designed on the basis of a RISC processor by using an ASIP designer. The design of ASIP is a process of iterative optimization based on an algorithm. The RISC processor is first implemented in the nML language of Synopsys, inc, and the data bit width, memory size, etc. are modified according to the particular data characteristics of the UWB receiver. The algorithm to be implemented on ASIP is implemented in C language and compiled using ASIP designer. And finally obtaining a verilog HDL model of the ASIP through the optimization of an ASIP designer tool. And fusing the front-end data flow co-processing unit and a verilog model of the ASIP by using verilog language, thereby completing the design of the whole UWB receiver baseband chip.
In the invention, the ASIP processing unit can also set a data transmission and positioning algorithm customized by a user through programming according to the user requirement.
The embodiments of the present invention are described only for the preferred embodiments of the present invention, and not for the limitation of the concept and scope of the present invention, and various modifications and improvements made to the technical solution of the present invention by those skilled in the art without departing from the design concept of the present invention shall fall into the protection scope of the present invention, and the technical content of the present invention which is claimed is fully set forth in the claims.
Claims (8)
1. UWB ultra wide band receiving baseband SOC system on chip based on ASIP, its characterized in that: the ultra-wideband signal preprocessing method comprises a front-end data flow co-processing unit constructed by an ASIC (application specific integrated circuit) processing unit, wherein the data input end of the front-end data flow co-processing unit is connected with the radio frequency analog front end of an ultra-wideband receiver through a high-speed serial-parallel conversion interface, and the front-end data flow co-processing unit acquires and preprocesses ultra-wideband signal data flow from the radio frequency analog front end of the ultra-wideband receiver;
the front-end data flow co-processing unit is internally programmed with a preamble detection preprocessing module and a data decoding preprocessing module, wherein the preamble detection preprocessing module presets a preamble, and the preamble detection preprocessing module in the front-end data flow co-processing unit carries out correlation operation preprocessing on the ultra-wideband signal data flow and the preset preamble to obtain the positions of a maximum correlation value, a minimum correlation value and a maximum correlation value; the data decoding preprocessing module carries out decoding preprocessing on a physical layer header and a physical layer service data unit part of a data frame in the ultra-wideband signal data stream;
the data output end of the front-end data flow co-processing unit is also connected with an FIFO memory, and the preprocessing result data of the front-end data flow co-processing unit, the data decoding preprocessing module and the front-end data flow co-processing unit are respectively written into and stored in the FIFO memory;
the system also comprises a back-end data stream processing unit constructed by the ASIP processing unit, wherein the data input end of the ASIP processing unit is connected with the FIFO memory, the interrupt signal input end of the ASIP processing unit is connected with the interrupt signal output end of the front-end data stream co-processing unit, the ASIP processing unit is additionally provided with a vector processing unit and a scalar processing unit, a vector instruction set is added on the basis of the original RISC instruction set of the ASIP processing unit through the vector processing unit, and a scalar instruction set is added on the basis of the original RISC instruction set of the ASIP processing unit through the scalar processing unit;
the ASIP processing unit is internally programmed with a UWB MAC layer scheduling module, a lead code detection post-processing module and a data decoding post-processing module, receives interrupt signals from a lead detection preprocessing module and a data decoding preprocessing module in the front-end data flow co-processing unit and enters an interrupt service program, and reads the positions of the maximum correlation value, the minimum correlation value and the maximum correlation value which are obtained by preprocessing the lead detection preprocessing module and the physical layer header and the physical layer service data unit part of a data frame which is obtained by decoding preprocessing of the data decoding preprocessing module from an FIFO memory; a lead code detection post-processing module in the ASIP processing unit calls a scalar instruction set of a scalar processing unit through a UWB MAC layer scheduling module to calculate time information, signal-to-noise ratio information and signal pulse information of the ultra-wideband signal according to the maximum correlation value, the minimum correlation value and the position of the maximum correlation value; and a data decoding post-processing module in the ASIP processing unit calls a scalar instruction set of the scalar processing unit and a vector instruction set of the vector processing unit simultaneously through a UWB MAC layer scheduling module so as to decode a physical layer header and a physical layer service data unit part of the data frame subjected to decoding preprocessing, and further obtain the physical layer header and the physical layer service data unit part of the data frame in the ultra-wideband signal data stream.
2. The ASIP-based UWB ultra-wideband receiving baseband SOC system-on-a-chip of claim 1, wherein: the clock input end of the ASIP processing unit is connected with the clock output end of the front-end data flow co-processing unit, and the ASIP processing unit receives the clock signal of the front-end data flow co-processing unit so as to realize the clock synchronization of the front-end data flow co-processing unit and the ASIP processing unit.
3. The ASIP-based UWB ultra-wideband receiving baseband SOC system-on-a-chip of claim 1, wherein: the front-end data flow co-processing unit comprises a front detection preprocessing module, a front detection preprocessing module and a position acquisition module, wherein the front detection preprocessing module comprises a correlation operation submodule and a position acquisition submodule, the correlation operation submodule carries out correlation operation preprocessing on the ultra-wideband signal data flow and a preset lead code to obtain a maximum correlation value and a minimum correlation value, and the position acquisition submodule acquires the position of the maximum correlation value so as to finish the correlation operation preprocessing.
4. The ASIP-based UWB ultra-wideband receiving baseband SOC system-on-a-chip of claim 1, wherein: the data decoding preprocessing module in the front-end data stream co-processing unit consists of an accumulation operation submodule and a rake submodule, wherein the accumulation operation submodule accumulates a physical layer header of a data frame in the ultra-wideband signal data stream and a physical layer service data unit part, and the rake submodule performs rake receiver processing for resisting multipath fading on an accumulation result so as to finish decoding preprocessing.
5. The ASIP-based UWB ultra-wideband receiving baseband SOC system-on-a-chip of claim 1, wherein: scalar processing units in the ASIP processing units comprise arithmetic logic units, multiply-accumulate processing units, SECDED processing units, CORDIC processing units and finite field operation units, arithmetic logic instructions are added to the scalar processing units through the arithmetic logic units, multiply-accumulate instructions are added through the multiply-accumulate processing units, SECDED instructions are added through the SECDED processing units, CORDIC instructions are added through the CORDIC processing units, finite field operation instructions are added through the finite field operation units, and scalar instruction sets are formed by the arithmetic logic instructions, the multiply-accumulate instructions, the SECDED instructions, the CORDIC instructions and the finite field operation instructions;
and a lead code detection post-processing module in the ASIP processing unit calls a CORDIC instruction, a multiply-accumulate instruction and an arithmetic logic instruction of a scalar processing unit through a UWB MAC layer scheduling module so as to calculate the maximum correlation value, the minimum correlation value and the position of the maximum correlation value, and obtain time information, signal-to-noise ratio information and signal pulse information of the ultra-wideband signal.
6. The ASIP-based UWB ultra-wideband receiving baseband SOC system-on-a-chip of claim 1, wherein: the Vector processing unit in the ASIP processing unit comprises an 8-bit arithmetic logic unit ALU, a 16-bit arithmetic logic unit ALU, a 128-bit arithmetic logic unit ALU and a Vector finite field processing unit, wherein the Vector processing unit adds an 8-bit arithmetic logic instruction through the 8-bit arithmetic logic unit ALU, adds a 16-bit arithmetic logic instruction through the 16-bit arithmetic logic unit ALU, adds a 128-bit arithmetic logic instruction through the 128-bit arithmetic logic unit ALU and adds a Vector finite field processing instruction through the Vector finite field processing unit, and a Vector instruction set is formed by the 8-bit arithmetic logic instruction, the 16-bit arithmetic logic instruction, the 128-bit arithmetic logic instruction and the Vector finite field processing instruction;
a data decoding post-processing module in the ASIP processing unit calls an SECDED instruction of a scalar processing unit through a UWB MAC layer scheduling module so as to perform SECDED decoding on a physical layer header and a physical layer service data unit part of a data frame subjected to decoding preprocessing; a data decoding post-processing module in the ASIP processing unit calls a finite field operation instruction of a scalar processing unit through a UWB MAC layer scheduling module, and an 8-bit arithmetic logic instruction, a 16-bit arithmetic logic instruction, a 128-bit arithmetic logic instruction and a vector finite field processing instruction in a vector processing unit so as to perform viterbi decoding and Reed-Solomon decoding on a physical layer header and a physical layer service data unit part of a data frame subjected to decoding preprocessing; and obtaining a physical layer header and a physical layer service data unit part of a data frame in the ultra-wideband signal data stream after SECDED decoding, viterbi decoding and Reed-Solomon decoding.
7. The ASIP-based UWB ultra-wideband receiving baseband SOC system-on-a-chip of claim 1, wherein: the ASIP processing unit is internally programmed with a spi boot module, the data input end of the ASIP processing unit is connected with a flash memory, and the ASIP processing unit is started through the flash memory and the spi boot module.
8. The ASIP-based UWB ultra-wideband receiving baseband SOC system-on-a-chip of claim 1, wherein: the data input end and the data output end of the ASIP processing unit are connected with a JTAG module, and the test of the ASIP processing unit is realized by the JTAG module.
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