CN101420245B - Scheduling method and device in TD-SCDMA baseband processing - Google Patents
Scheduling method and device in TD-SCDMA baseband processing Download PDFInfo
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Abstract
The present invention discloses a scheduling control method and device in the TD-SCDMA base-band processing According to the method, related operation procedure is divided into a plurality of streamline beats and a starting time point is determined, 'information elements' are scheduled and controlled by using the starting time point as the core code, the operation time count values and the starting time points in the scheduling control information elements are compared in order, if the comparing result is equal, corresponding scheduling control signals are generated according to the carrier wave number, the time slot time and the beat number in the information element, and then an execution of a corresponding arithmetic operation module is started. The device comprises a ROM storage, a ROM controller, a time point counter, a time point comparator and a scheduling control signal decoder. Based on the scheduling control method with a fixed time point, accurate scheduling can be achieved and software and hardware are easy to realize. The device can complete complicated scheduling tasks which need high-performance CPU and DSP by only utilizing a few of hardware circuits.
Description
Technical field
The invention belongs to the wireless communication baseband processing technology field, the method and apparatus that is used for carrying out multicarrier multi-slot computing scheduling controlling of realizing based on FPGA or ASIC during particularly wireless communication baseband is processed.
Background technology
Base-Band Processing is defined in from the digital intermediate frequency to the transmission channel and is disposed, and comprises channel up-downgoing processing and base band measurement etc.Be exactly specifically, descending behind MAC layer receive data, according to the channel attribute that is configured, carry out coding, modulation, spread spectrum, the scrambling of transmission channel, add synchronous power control information and form burst, export at last the IQ baseband digital signal, carry out processing to transmitter (TX) behind the down beam shaping; Up direction, from carrying out direction of arrival (DOA) estimation and channel estimating, matched filtering, joint-detection after antenna feeder equipment receives the IQ base band data, last demodulation, decoding form the needed data of MAC layer, give the MAC layer exactly.In addition, also to carry out the processing of NBAP order, the processing of frame processor (FP) control frame and the calibration of antenna.
TD-SCDMA is a tdd systems, comes word from the time slot angle, and the processing of ascending time slot has occupied the time of the overwhelming majority of processor.Each processing up or descending time slot can be divided into symbol level and chip-level again, symbol level mainly is exactly the encoding and decoding of transmission channel, chip-level mainly is exactly modulation /demodulation, spectrum-spreading and scrambling of physical channel etc., and wherein the processing of the chip-level of ascending time slot has occupied most time.
The scheduling controlling that TD-SCDMA baseband chip level is processed each calculation process module is very complicated, the operand of some of them algoritic module is quite large, and concerning based on the TD-SCDMA of time division duplex (TDD), the processing time of every subframe is fixed as 5ms, so very sensitive to the calculation process time of algoritic module.It is impossible mission that whole serials of all algoritic modules are carried out present DSP device or CPU.So the scheduling controlling of existing processing scheme based on DSP or CPU roughly adopts following methods:
The DSP scheme---adopt the multi-DSP co-treatment, per 4 DSP process 1 carrier wave, the Processing tasks of every DSP is pressed time slot and is divided, 4 DSP share the processing of processing different time-gap by the operand homeostatic principle, every DSP Processing tasks can be prepared, such as DSP0 processing 0,1 time slot, and DSP1 processes 2,5 time slots, DSP2 processes descending pilot frequency, 3,6 time slots, and DSP3 processes GpUp, 4 time slots.This scheme shortcoming is a lot: autgmentability is poor; It is many to consume the DSP device, and cost is high; Each time slot of same subframe divides at multi-DSP to be processed, and scheduling controlling, signaling and NBAP parameter configuration are very complicated.
The CPU scheme---substantially only have at present the multi-core CPU of a Motorola can finish the Base-Band Processing task of TD-SCDMA, its scheme principle also is each algorithm unit to be distributed to a plurality of CPU process nuclear and carry out respectively computing.The shortcoming of this scheme is also a lot: can satisfy the CPU of this disposal ability seldom; Scheduling controlling is equally very complicated, need to process at a plurality of CPU and frequently carry out the big data quantity operation between the nuclear.
Summary of the invention
The technical problem to be solved in the present invention is hardware implementation complexity and the cost of facilitating TD-SCDMA Base-Band Processing multicarrier multi-slot scheduling controlling, proposes a kind of dispatch control method and device based on fixed time point.The characteristics of divisional processing when this dispatch control method and device combine TD-SCDMA can be accomplished very accurate scheduling, and are easy to the software and hardware realization.
For solving the problems of the technologies described above, the dispatch control method in the TD-SCDMA Base-Band Processing that the present invention proposes is such:
The rule of (1) not conflicting according to the use of the length in processing time and calculation process resource is divided into several streamline beats with TD-SCDMA Baseband processing algorithm computing flow process;
(2) be reference by the required processing time of maximum operand, determine the initial time point of each beat, the corresponding initial time point of each beat;
(3) unit take the initial time point as the core encoder scheduling control information, each scheduling control information unit comprises initial time point, joint time signature, carrier number and these four information of timeslot number, subframe head with each subframe begins, each scheduling control information unit according to the moment point in it by being arranged in order from small to large;
(4) each subframe begins to carry out counting operation time according to the subframe leader will that receives, this count value is identical with moment point information unit in the scheduling control information unit, with this operation time count value successively with the scheduling control information unit that preserves in moment point information compare, compare with the moment point in real-time operation time count value and first scheduling control information unit first, if the moment point and next the real-time counting value that equate then get in the next scheduling control information unit compare, if unequal then compare with the moment point in the current scheduling control information unit and next real-time counting value always, compare until equate the moment point of just taking off successively in the scheduling control information unit.The like, to the last the moment point information in scheduling control information unit and operation time count value equate, the moment point of this subframe scheduling control relatively finishes, when moment point information and operation time, count value equated at every turn in scheduling control information unit, according to the carrier number in this scheduling control information unit, timeslot number and the corresponding scheduling control signal of joint time signature Information generation, the execution of the related algorithm computing module of startup direction of arrival estimation and channel estimating, matched filtering, joint-detection, the processing of reconciling at last, decode.
In the said method, the number of the related algorithm computing module that each beat comprises is not quite similar.
In the said method, moment point can represent with single clock number, also can unite with number of chips and clock number to represent.
For realizing said method, the dispatching control device that the present invention proposes comprises ROM memory, ROM controller, moment point counter, moment point comparator and scheduling control signal decoder.
The ROM memory, be used for preserving each scheduling control information unit, and the ROM that inputs according to the ROM controller reads address and control signal, moment point information output with scheduling control information unit arrives the moment point comparator respectively, will save time signature, carrier number and timeslot number information output in the scheduling control information unit to the scheduling control signal decoder.
The ROM controller is used for realizing ROM memory read access control signal and reads address generation, produces the ROM memory according to the moment point comparison information from the input of moment point comparator and reads address and control signal, exports to the ROM memory.
The moment point counter is used for realizing counting operation time, and its output is connected to the moment point comparator, and each subframe begins to carry out counting operation time according to the subframe leader will that receives.
The moment point comparator, be used for realizing the moment point data relatively, to compare with the pre-stored moment point information of inputting from the ROM memory from the real-time moment point information of moment point counter input, compare with the moment point in real-time operation time count value and first scheduling control information unit first, if the moment point and next the real-time counting value that equate then get in the next scheduling control information unit compare, if unequal then compare with the moment point in the current scheduling control information unit and next real-time counting value always, compare until equate the moment point of just taking off successively in the scheduling control information unit.The like, to the last the moment point information in scheduling control information unit and operation time count value equate that the moment point of this subframe scheduling control relatively finishes, and with the comparative result information output to ROM controller and scheduling control signal decoder;
The scheduling control signal decoder, be used for realizing the generation of scheduling control signal, when moment point information and operation time, count value equated at every turn in scheduling control information unit, according to the carrier number in this information word, timeslot number and the corresponding scheduling control signal of joint time signature Information generation, the execution of the related algorithm computing module of startup direction of arrival estimation and channel estimating, matched filtering, joint-detection, the processing of reconciling at last, decode.
In the said apparatus, scheduling control information unit of each address line of ROM memory storage begins with the subframe head of each subframe, each scheduling control information unit according to the moment point in it by being arranged in order from small to large.
In the said apparatus, when moment point and real-time moment point equate at every turn in scheduling control information unit, the scheduling control signal decoder starts the execution of related algorithm computing module according to the carrier number in this information word, timeslot number and the corresponding scheduling control signal of joint time signature Information generation.
The inventive method has guaranteed that based on the dispatch control method of fixed time point scheduling controlling can not clash, and can accomplish very accurate scheduling, and the method simplification is easy to software and hardware and realizes.Dispatching control device of the present invention can accurately produce the scheduling controlling to the computing of TD-SCDMA Base-Band Processing, utilizes seldom hardware circuit to finish to need the scheduler task of the complexity that high-performance CPU and DSP just can finish.The present invention can greatly improve calculation process efficient, realizes accurately flexibly streamline and parallel processing, can the hard-wired advantage of fine performance, and make and utilize hardware to realize that TD-SCDMA base band algorithm process becomes practical.No matter utilize FPGA or ASIC to realize all having avoided use built-in with CPU nuclear and DSP calculation process nuclear, guaranteed low-cost realization, reduce computational complexity.In addition, realize and propose although the present invention is based on to optimize hardware, be equally applicable to the simplified design of DSP and CPU software handling procedure.
Description of drawings
Fig. 1 is that 3 uplink scheduling controls of 6 carrier waves realize schematic diagram;
Fig. 2 is dispatching control device the first example structure schematic diagram of the present invention;
Fig. 3 is dispatching control device the second example structure schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail.
Among the present invention, suppose that 1 ascending time slot of each carrier wave comprises M beat, M initial time point namely arranged, then X corresponding X*Y*M moment point of carrier wave Y ascending time slot.Below take adopt the inventive method and device to 6 carrier waves 3 time slot TD-SCDMA Base-Band Processing computings carry out scheduling controlling and describe as example.
At first, the rule of not conflicting according to the use of the length in processing time and calculation process resource is divided into 5 streamline beats with each algorithm processing module of each ascending time slot.
Then, the processing time required by maximum operand is reference, determines the initial time point of each beat, and the corresponding initial time point of each beat then produces altogether X*Y*M=6*3*5=90 initial time point.
Next, take the initial time point as core encoder scheduling controlling " information word ", each scheduling control information unit comprises moment point, joint time signature, carrier number and timeslot number, these four information assembly units are obtained { moment point, the joint time signature, carrier number, timeslot number } scheduling control information unit, " { } " is used for representing assembly unit here.If moment point information represents that with a bit joint time signature information represents that with the b bit carrier number information represents that with the c bit timeslot number information represents that with the d bit then each scheduling control information unit content is the a+b+c+d bit.Subframe head with each subframe begins, 90 scheduling control information units according to the moment point in it by being arranged in order from small to large.
Afterwards, each subframe begins to carry out counting operation time according to the subframe leader will that receives, and this count value is identical with moment point information unit in the scheduling control information unit.Because every subframe comprises 6400 chips, carry out frequency f (MHz) according to circuit, every chip comprises again (f/1.28) individual clock cycle, suppose that it is 215.04MHz that circuit is carried out frequency, then f/1.28 equals 168, it is 1075200 that the clock periodicity that every subframe comprises or the moment count, and namely operation time, count range was 0 to 1075199.Moment point information in the scheduling control information unit of this count value and preservation is compared operation time: compare with the moment point in real-time operation time count value and first scheduling control information unit first, if the moment point and next the real-time counting value that equate then get in the next scheduling control information unit compare, if unequal then compare with the moment point in the current scheduling control information unit and next real-time counting value always, compare until equate the moment point of just taking off successively in the scheduling control information unit.The like, to the last the moment point information in scheduling control information unit and operation time count value equate that the moment point of this subframe scheduling control relatively finishes.When moment point information and operation time, count value equated at every turn in the scheduling control information unit, according to the carrier number in this information word, timeslot number and the corresponding scheduling control signal of joint time signature Information generation, start the execution of related algorithm computing module.
Adopt the inventive method and device to 6 carrier waves 3 time slot TD-SCDMA Base-Band Processing computings carry out the realization schematic diagram of scheduling controlling referring to Fig. 1.
Realize above-mentioned dispatch control method, the apparatus structure that scheduling controlling is carried out in 3 time slot TD-SCDMA Base-Band Processing computings to 6 carrier waves comprises ROM memory, ROM controller, moment point counter, moment point comparator and scheduling control signal decoder as shown in Figure 2.
The ROM memory is used for preserving each scheduling control information unit, and the ROM that inputs according to the ROM controller reads address and control signal, moment point information output with scheduling control information unit arrives the moment point comparator respectively, will save time signature, carrier number and timeslot number information output in the scheduling control information unit to the scheduling control signal decoder.The size of this ROM memory is that the degree of depth is 90 address lines, and width is 42 bits.The content that store each address of corresponding stored device is a scheduling control information unit, and the width of ROM memory is the data bit width of scheduling control information unit.Scheduling control information unit comprises number of chips, clock periodicity, joint time signature, carrier number and timeslot number.Wherein, number of chips span [0,6399] represents with 13 Bit datas; The span [0,1075199] of constantly counting represents with 21 Bit datas; Joint time signature span [0,4] represents with 3 Bit datas; Carrier number span [0,5] represents with 3 Bit datas; Timeslot number span [0,2] represents with 2 Bit datas.
The ROM controller is used for realizing ROM memory read access control signal and reads address generation, produces the ROM memory according to the moment point comparison information from the input of moment point comparator and reads address and control signal, exports to the ROM memory.ROM reads address clear 0 when receiving subframe leader will signal, when satisfying the moment point counter values and equal the moment point of scheduling control information unit in the ROM memory of current address, ROM reads the address increases by 1, and generate ROM and read enable signal, in order to take out the scheduling control information metadata among the next address ROM.This address is increased at most 89, and namely address span [0,89] is increased to 89 rear addresses clear 0.
The moment point counter is used for realizing counting operation time, and its output is connected to the moment point comparator.The moment point counter receives subframe leader will to begin from 0 counting, and each increases by 1 clock cycle, until count down to 1075199 clear 0 or with new subframe leader will clear 0.
The moment point comparator, be used for judging moment that moment point Counter Value and current ROM read the scheduling control information unit that takes out the address count whether consistent, if positive effective impulse marker equal then that export a clock cycle width is given ROM controller and scheduling control signal decoder.The ROM controller utilizes this pulse signal to generate new reading enable signal and read the address; The scheduling control signal decoder produces each correct beat scheduling control signal according to this pulse signal and scheduling control information unit.
The scheduling control signal decoder, be used for realizing the generation of scheduling control signal, count when equating when the moment in the scheduling control information unit that moment point Counter Value and current ROM read to take out the address, joint time signature, carrier number and timeslot number information in the ROM memory scheduling control information unit of reading according to current ROM address generate the scheduling control signal of the appointment beat of corresponding carriers and time slot.
Suppose that it is 215.04MHz that circuit is carried out frequency, then every chip comprises 168 clock cycle, and every subframe comprises 6400 chips, therefore can determine moment point with number of chips and clock number.Be that the information that each moment point comprises is C the clock cycle of L chip, then the moment point information data is (L, C), and wherein the span of L is [0,6399], and the span of C is [0,167].So, to carry out the device of scheduling controlling can also be as shown in Figure 3 structure in 3 time slot TD-SCDMA Base-Band Processing computings to 6 carrier waves, be that the moment point counter comprises chip count device and clock counter, the moment point comparator comprises number of chips comparator and clock number comparator.The chip count device is exported to the number of chips comparator; Clock counter is exported to the clock number comparator.
The count range of clock counter since 0 to 167: from receiving subframe leader will from 0 counting, each increases by 1 clock cycle, whenever meter by 167 o'clock, clock counter is clear 0, again since 0 counting, so circulation; The count range of chip count device since 0 to 6399: from receiving subframe leader will from 0 counting, whenever the clock counter value equals at 167 o'clock, chip count device value increases by 1, until count down to 6399 clear 0 or clear 0 with new subframe leader will, so circulation.
The number of chips comparator is used for judging whether the number of chips in the scheduling control information unit that chip count device value and current ROM read to take out the address is consistent, and clock comparator is used for judging whether the clock number in the scheduling control information unit that clock counter value and current ROM read to take out the address is consistent, exports the positive effective impulse marker of a clock cycle width if the comparative result of two comparators all equates and gives ROM controller and scheduling control signal decoder.The ROM controller utilizes this pulse signal to generate new reading enable signal and read the address; Joint time signature, carrier number and timeslot number data in the ROM memory scheduling control information unit that the scheduling control signal decoder is read according to current ROM address generate the scheduling control signal of the appointment beat of corresponding carriers and time slot.
Because clock periodicity span [0,167] represents to get final product with 8 Bit datas, is 90 address lines so the size of ROM memory is the degree of depth, width is 29 bits.Wherein, number of chips span [0,6399] represents with 13 Bit datas; Clock periodicity span [0,167] represents with 8 Bit datas; Joint time signature span [0,4] represents with 3 Bit datas; Carrier number span [0,5] represents with 3 Bit datas; Timeslot number span [0,2] represents with 2 Bit datas.
Claims (8)
1. the dispatch control method in the TD-SCDMA Base-Band Processing is characterized in that comprising:
The rule of (1) not conflicting according to the use of the length in processing time and calculation process resource is divided into several streamline beats with TD-SCDMA Baseband processing algorithm computing flow process;
(2) be reference by the required processing time of maximum operand, determine the initial time point of each beat, the corresponding initial time point of each beat;
(3) unit take the initial time point as the core encoder scheduling control information, each scheduling control information unit comprises described initial time point, joint time signature, carrier number and these four information of timeslot number, subframe head with each subframe begins, each scheduling control information unit according to the moment point in it by being arranged in order from small to large;
(4) each subframe begins to carry out counting operation time according to the subframe leader will that receives, this count value is identical with moment point information unit in the scheduling control information unit, with this operation time count value successively with the scheduling control information unit that preserves in moment point information compare, compare with the moment point in real-time operation time count value and first scheduling control information unit first, if the moment point and next the real-time counting value that equate then get in the next scheduling control information unit compare, if unequal then compare with the moment point in the current scheduling control information unit and next real-time counting value always, compare until equate the moment point of just taking off successively in the scheduling control information unit; The like, to the last the moment point information in scheduling control information unit and operation time count value equate, the moment point of this subframe scheduling control relatively finishes, when moment point information and operation time, count value equated at every turn in scheduling control information unit, according to the carrier number in this scheduling control information unit, timeslot number and the corresponding scheduling control signal of joint time signature Information generation, the execution of the related algorithm computing module of startup direction of arrival estimation and channel estimating, matched filtering, joint-detection, the processing of reconciling at last, decode.
2. dispatch control method according to claim 1 is characterized in that, the number of the described related algorithm computing module that each beat comprises is not quite similar.
3. dispatch control method according to claim 1 is characterized in that, described moment point represents with single clock number.
4. dispatch control method according to claim 1 is characterized in that, described moment point is united with number of chips and clock number and represented.
5. a dispatching control device of realizing the described method of claim 1 is characterized in that comprising ROM memory, ROM controller, moment point counter, moment point comparator and scheduling control signal decoder;
Described ROM memory be used for to be preserved each scheduling control information unit, and each scheduling control information unit of address line storage begins with the subframe head of each subframe, each scheduling control information unit according to the moment point in it by being arranged in order from small to large; The ROM memory is read address and control signal according to the ROM of ROM controller input, moment point information output with scheduling control information unit arrives the moment point comparator respectively, will save time signature, carrier number and timeslot number information output in the scheduling control information unit to the scheduling control signal decoder;
Described ROM controller is used for realizing ROM memory read access control signal and reads address generation, produces the ROM memory according to the moment point comparison information from the input of moment point comparator and reads address and control signal, exports to the ROM memory;
Described moment point counter is used for realizing counting operation time, and its output is connected to the moment point comparator, and each subframe begins to carry out counting operation time according to the subframe leader will that receives;
Described moment point comparator, be used for realizing the moment point data relatively, to compare with the pre-stored moment point information of inputting from the ROM memory from the real-time moment point information of moment point counter input, compare with the moment point in real-time operation time count value and first scheduling control information unit first, if the moment point and next the real-time counting value that equate then get in the next scheduling control information unit compare, if unequal then compare with the moment point in the current scheduling control information unit and next real-time counting value always, compare until equate the moment point of just taking off successively in the scheduling control information unit; The like, to the last the moment point information in scheduling control information unit and operation time count value equate that the moment point of this subframe scheduling control relatively finishes, and with the comparative result information output to ROM controller and scheduling control signal decoder;
Described scheduling control signal decoder, be used for realizing the generation of scheduling control signal, when moment point information and operation time, count value equated at every turn in scheduling control information unit, according to the carrier number in this information word, timeslot number and the corresponding scheduling control signal of joint time signature Information generation, the execution of the related algorithm computing module of startup direction of arrival estimation and channel estimating, matched filtering, joint-detection, the processing of reconciling at last, decode.
6. dispatching control device according to claim 5, it is characterized in that, the size of described ROM memory is that the degree of depth is 90 address lines, width is 42 bits, wherein 13 bits are used for the expression number of chips, and 21 bits are used for expression counts constantly, and 3 bits are used for expression joint time signature, 3 bits are used for the expression carrier number, and 2 bits are used for the expression timeslot number;
Described moment point counter receives subframe leader will to begin from 0 counting, and each increases by 1 clock cycle, until count down to 1075199 clear 0 or with new subframe leader will clear 0.
7. dispatching control device according to claim 5 is characterized in that, described moment point counter comprises chip count device and clock counter; Described moment point comparator comprises number of chips comparator and clock number comparator; The chip count device is exported to the number of chips comparator, and clock counter is exported to the clock number comparator;
The number of chips comparator is used for judging whether the number of chips in the scheduling control information unit that chip count device value and current ROM read to take out the address is consistent, and clock comparator is used for judging whether the clock number in the scheduling control information unit that clock counter value and current ROM read to take out the address is consistent; Export the positive effective impulse marker of a clock cycle width if the comparative result of two comparators all equates and give ROM controller and scheduling control signal decoder.
8. dispatching control device according to claim 7 is characterized in that, the count range of described clock counter since 0 to 167: from receiving that subframe leader will is from 0 counting, each clock cycle increases by 1, whenever counting by 167 o'clock clock counter clear 0, again since 0 counting, so circulation;
The count range of described chip count device since 0 to 6399: from receiving subframe leader will from 0 counting, whenever the clock counter value equals at 167 o'clock, chip count device value increases by 1, until count down to 6399 clear 0 or clear 0 with new subframe leader will, so circulation;
The size of described ROM memory is that the degree of depth is 90 address lines, and width is 29 bits, and wherein 13 bits are used for the expression number of chips, 8 bits are used for the expression clock periodicity, 3 bits are used for expression joint time signature, and 3 bits are used for the expression carrier number, and 2 bits are used for the expression timeslot number.
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| CN1622477A (en) * | 2004-12-15 | 2005-06-01 | 展讯通信（上海）有限公司 | A method for implementing sending and receiving control of TD-SCDMA system under different conditions |
| CN1675947A (en) * | 2002-08-22 | 2005-09-28 | 日本电气株式会社 | Non-hit hard handover control device and method |
| WO2007073622A1 (en) * | 2005-12-29 | 2007-07-05 | Zte Corporation | Digital baseband processing controller and baseband real time control method |
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| CN1675947A (en) * | 2002-08-22 | 2005-09-28 | 日本电气株式会社 | Non-hit hard handover control device and method |
| CN1622477A (en) * | 2004-12-15 | 2005-06-01 | 展讯通信（上海）有限公司 | A method for implementing sending and receiving control of TD-SCDMA system under different conditions |
| WO2007073622A1 (en) * | 2005-12-29 | 2007-07-05 | Zte Corporation | Digital baseband processing controller and baseband real time control method |
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