CN111628788B - Extremely fast error correction decoding method and device - Google Patents
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Abstract
The invention discloses an extremely fast error correction decoding method, which comprises the following steps that a primary shift decoding circuit and a secondary shift decoding circuit simultaneously receive an information code stream of a transmitting end; the primary shift decoding circuit performs spontaneous operation under the condition of no input until the upper 8 bits are all 0, the secondary shift decoding circuit also performs spontaneous operation synchronously, the N1 counter counts the number of spontaneous operation to obtain an N1 value, the lower 8 bits of data of the primary shift decoding circuit are error mode values, the error mode values and the values of the secondary shift decoding circuit are spliced into addressing addresses, the distance values between corresponding 8bit code words, namely N2 values, are extracted from a memory, and an error position i is calculated. The invention greatly improves the speed of error correction decoding. The error correction decoding processing speed is obviously improved compared with the existing scheme.
Description
Technical Field
The invention belongs to the field of magnetic disk storage technology in communication, and particularly relates to an extremely fast error correction decoding method and an extremely fast error correction decoding device.
Background
In the fields of communication and disk storage, the problem of information transmission and access errors needs to be solved. Fire code, which is capable of correcting "single multi-bit burst errors", is widely used as a theoretical basis to solve this problem. The code system and the related algorithm are used for finding out the place where the error occurs in the information code stream and correcting the place.
However, the current method for correcting and shifting the French code has the following problems:
1. inefficient, hundreds of clock cycles are required to complete the computation. For example, when calculating 4080-bit fire code error correction decoding, a maximum of 270 clock cycles are required for the required autonomous operation.
2. The speed is unstable and the speed difference is extremely large. Due to the randomness of burst errors in the information code stream, the clock period required for completing calculation is tens to hundreds of different when error correction decoding is performed.
3. Speed instability causes the hardware error correction circuit/chip design to have to look like "low speed". That is, the error correction circuit/chip must be designed in the slowest (most consumed clock cycles) case, which reduces the processing speed of the overall information system.
Disclosure of Invention
The invention aims to overcome the defects and shortcomings of the prior art, and provides a very fast error correction decoding method, a very fast error correction decoding device and a very simple error correction decoding device by utilizing the cycle characteristic of a cycle code, so that N2 spontaneous operation time in the existing scheme is completely eliminated, the spontaneous operation is reduced from 270 clock Cycles (CLK) at most to 15CLK at most, and the error correction decoding speed is greatly improved. The error correction decoding processing speed of the invention is improved by 18 times compared with the existing scheme under the same condition.
In order to achieve the above object, the present invention adopts the following technical measures:
the existing Fire code error correction is divided into the following three steps:
step 1, calculating an error mode value B (x) and an N1 value.
Due to the primary shift decoding circuit ((X) 16 +1) circuit) with 16 cycles, where for burst errors of no more than 8 bits, the primary shift decoding circuit is operated autonomously no more than 15 times without input, the upper 8 bits of the circuit have to be all zeros, and the lower 8 bits hold the error pattern value B (x). The value of the spontaneous times N1 is put into a hardware 4-bit (bit) N1 counter for storage.
And 2, obtaining an N2 value, wherein the spontaneous operation times are N2.
The primary shift decoding circuit stops and the error pattern value B (x) is fixed at the lower 8 bits of the primary shift decoding circuit. The secondary shift decoding circuit is then operated spontaneously N2 times (N2 takes a value somewhere in the middle of 0 to 255). When the content of the secondary shift decoding circuit is equal to the error mode value B (x) (compared by the congruent comparison circuit), the current spontaneous operation secondary value is the value of N2. The value of N2 is stored in the hardware "N2 bit counter (8 bit counter)" of fig. 1.
And step 3, calculating the position of the burst error.
The high 4 bits and the low 4 bits of N2 (8 bits) are subjected to cross transposition to obtain new 8-bit binary numbers, and then the binary numbers of 12 bits are obtained by splicing the values of N1 (4 bits), namely the positions of burst errors in the information code stream. That is, the value of the position i of B (x) is obtained. Thus, the error correction decoding process is completed.
The invention uses the 'Chinese remainder theorem' to correct the Fire code, and uses the same counter assembly method to avoid the multiplication and addition operation, to confirm the decoding speed and realize easily.
The invention is different in that the existing scheme is further improved and perfected. That is, the cyclic nature of cyclic codes is utilized to achieve extremely fast decoding of Fire codes. As shown in fig. 2:
the invention eliminates the congruent comparison (8-bit) circuit and the N2-bit counter (8-bit counter) in hardware. The required N2 spontaneous operation time is completely eliminated algorithmically.
An extremely fast error correction decoding method, comprising the steps of:
step 1, a primary shift decoding circuit and a secondary shift decoding circuit simultaneously receive an information code stream d (x) of a transmitting end;
step 2, after the primary shift decoding circuit receives the information code stream d (x), performing spontaneous operation for no more than 15 times under no input condition until the high 8 bits of the primary shift decoding circuit measured by the all-zero detection circuit are all 0, performing spontaneous operation by the secondary shift decoding circuit simultaneously while performing spontaneous operation by the primary shift decoding circuit, counting the number of times of spontaneous operation by an N1 counter to obtain an N1 value, wherein the low 8 bits of data of the primary shift decoding circuit are error mode values B (x),
step 3, splicing the error mode value and the value of the secondary shift decoding circuit into a 16-bit addressing address, storing a distance value between 8-bit code words corresponding to the addressing address in a storage unit of a memory, namely an N2 value,
the upper 8 bits and the lower 8 bits of the N2 value are interchanged to obtain an N2 'value, the N2' value is taken as the upper 8 bits, and the N1 value is taken as the lower 4 bits to be spliced into an error position i.
An extremely fast error correction decoding device comprises a primary shift decoding circuit, an all-zero detection circuit, a secondary shift decoding circuit, an N1 counter, a memory and a controller.
The primary shift decoding circuit and the secondary shift decoding circuit simultaneously receive the information code stream of the transmitting end,
after the primary shift decoding circuit receives the information code stream, the primary shift decoding circuit performs spontaneous operation for no more than 15 times under no input condition until the 8 high bits of the primary shift decoding circuit measured by the all-zero detection circuit are all 0, the secondary shift decoding circuit performs spontaneous operation synchronously while the primary shift decoding circuit performs spontaneous operation, the N1 counter counts the number of times of spontaneous operation to obtain an N1 value,
the controller reads the lower 8 bits of data of the primary shift decoding circuit as an error pattern value,
the controller splices the error mode value and the value of the secondary shift decoding circuit into a 16-bit addressing address, a storage unit corresponding to the addressing address in the memory stores a corresponding distance value between 8-bit code words, namely an N2 value, the controller reads the N2 value,
the controller exchanges the upper 8 bits and the lower 8 bits of the N2 value to obtain an N2 'value, the N2' value is used as the upper 8 bits, and the N1 value is used as the lower 4 bits to be spliced into an error position i.
Through the technical measures: the method for realizing extremely rapid decoding of Fire (Fire) codes by utilizing the cyclic characteristics of cyclic codes solves the following technical problems and difficulties. B. The invention relates to a method for eliminating N2 spontaneous operation time. C. The invention does not need an 8-bit comparison circuit and an 8-bit N2 counter in the existing scheme, and the error correction decoding circuit is more concise and efficient. D. The error correction decoding time and the random fluctuation of the invention are far smaller than those of the prior art, and are only influenced by spontaneous operation of 0-15 and not influenced by operation of 0-255 of N2. Therefore, the decoding speed is faster, and the fluctuation of the decoding speed is smaller, which means that the information error correction and the information communication rate are obviously improved after the invention is applied.
The spontaneous operation frequency range of the existing scheme is 0-270 (15+255) of Max (N1+N2); the spontaneous operation frequency range of the invention is 0-15 and Max (N1); if each autonomous operation takes 1 clock Cycle (CLK), then the existing scheme would take 270CLK in a worst case scenario, while the present invention only requires 15CLK. Meanwhile, in the design of an error correction system, a worst case, i.e. "short-board effect", must be considered. Therefore, in the circuit time sequence design, the design speed of the existing scheme can only be 270CLK, and the design speed after the invention is adopted can reach 15CLK, and the time sequence speed is improved by 18 times.
Compared with the prior art, the invention has the following advantages and positive effects:
the invention provides a more concise error correction decoding scheme by utilizing the cycle characteristic of the cycle code, completely eliminates the N2 spontaneous operation time in the existing scheme, reduces the spontaneous operation from 270 clock Cycles (CLK) at most to 15CLK at most, and greatly improves the error correction decoding speed. The error correction decoding processing speed of the invention is improved by 18 times compared with the existing scheme under the same condition.
The hardware design of the invention cancels an 8-bit comparison circuit and an 8-bit N2 counter circuit adopted by the prior proposal, and the circuit of the invention is more concise.
The random volatility of the invention in the error correction decoding processing time is much smaller than that of the prior proposal, and the random volatility of the proposal is 0 to 15 clock cycles; the original scheme is 0 to 270 clock cycles; the volatility is only 1/18 (15/270) of the original scheme. Is only affected by spontaneous operation of 0.ltoreq.N1.ltoreq.15, and is not affected by operation of 0.ltoreq.N2.ltoreq.255 at all. The decoding processing time random fluctuation range of the existing scheme is as follows: 0 to 270; whereas the random fluctuation range of the present invention is only 0 to 15.
Drawings
FIG. 1 is a schematic diagram of a conventional Fire error correction decoding scheme;
FIG. 2 is a schematic diagram of an extremely fast error correction decoding device;
fig. 3 is an example data diagram of an error correction decoding for an extremely fast error correction decoding method.
Detailed Description
The present invention will be further described in detail below in conjunction with the following examples, for the purpose of facilitating understanding and practicing the present invention by those of ordinary skill in the art, it being understood that the examples described herein are for the purpose of illustration and explanation only and are not intended to limit the invention.
Example 1:
an extremely fast error correction decoding device comprises a primary shift decoding circuit ((X) 16 +1) circuit), an all-zero detection circuit, a secondary shift decoding circuit (P (x) circuit), an N1 counter, a memory, and a controller.
The primary shift decoding circuit and the secondary shift decoding circuit simultaneously receive the information code stream of the transmitting end,
after the primary shift decoding circuit receives the information code stream, the primary shift decoding circuit performs spontaneous operation for no more than 15 times under no input condition until the 8 high bits of the primary shift decoding circuit measured by the all-zero detection circuit are all 0, the secondary shift decoding circuit performs spontaneous operation synchronously while the primary shift decoding circuit performs spontaneous operation, the N1 counter counts the number of times of spontaneous operation to obtain an N1 value,
the controller reads the lower 8 bits of data of the primary shift decoding circuit as an error pattern value,
the controller splices the error mode value and the value of the secondary shift decoding circuit into a 16-bit addressing address, a storage unit corresponding to the addressing address in the memory stores a corresponding distance value between 8-bit code words, namely an N2 value, the controller reads the N2 value,
the controller exchanges the upper 8 bits and the lower 8 bits of the N2 value to obtain an N2 'value, the N2' value is used as the upper 8 bits, and the N1 value is used as the lower 4 bits to be spliced into an error position i.
An extremely fast error correction decoding method, comprising the steps of:
step 1, the primary shift decoding circuit and the secondary shift decoding circuit simultaneously receive an information code stream d (x) of a transmitting end, wherein the information code stream d (x) from the transmitting end comprises an original information code C (x) and a burst error E (x), and the information code stream d (x) represents a received code stream comprising the burst error after transmission.
The error correction decoding process of the invention is divided into two stages, namely, error mode code B (x) and error position i. I.e. "how wrong" and "where wrong" are obtained.
Step 2, calculating an error mode value B (x), specifically:
after the primary shift decoding circuit receives the information code stream d (x), the primary shift decoding circuit performs spontaneous operation for no more than 15 times under no input condition until the upper 8 bits of the primary shift decoding circuit measured by the all-zero detection circuit are all 0, the secondary shift decoding circuit performs spontaneous operation synchronously while the primary shift decoding circuit performs spontaneous operation, the N1 counter counts the number of times of spontaneous operation to obtain an N1 value, the lower 8 bits of data of the primary shift decoding circuit is an error mode value B (x),
after the information code stream d (X) enters the primary shift decoding circuit and the secondary shift decoding circuit, the primary shift decoding circuit ((X) 16 +1) circuit) for a burst error of not more than 8 bits, the primary shift decoding circuit is autonomously operated no more than 15 times without input, the upper 8 bits of the primary shift decoding circuit are all zeros, and the lower 8 bits of the primary shift decoding circuit store the error pattern value B (x).
For example, if an error in d (x) occurs at bits 43 to 36 (as shown in FIG. 3), the 43, 42, 39, 38, 36 bits are in error. The error polynomial may be expressed as:
E(x)＝X 43 +X 42 +X 39 +X 38 +X 36
＝X 36 (X 7 +X 6 +X 3 +X 2 +X 0 )
＝X 36 (1100 1101) 2
＝X 36 (CD) H
where error pattern value B (x) = (CD) H, and error location i=36.
When d (X) =c (X) +e (X) =x 36 (CD) H After the secondary shift decoding circuit also performs the spontaneous operation synchronously, the content remained in the secondary shift decoding circuit is (46) H The content remaining in the primary shift decoding circuit is (0 CD 0) H 。
In this stage, the primary shift decoding circuit is operated spontaneously no more than 15 times without input, and when n1=12, the content of the primary shift decoding circuit becomes (00 CD) H At this timeThe upper 8 bits of the primary shift decoding circuit are all 0 (detected by the all-zero detection circuit), and the content stored in the lower 8 bits of the primary shift decoding circuit is the error mode value B (x) = (CD) H . The corresponding secondary shift decoding circuit is also operated spontaneously N1 times in synchronism, and the content of the secondary shift decoding circuit becomes (B9) H . The number of spontaneous times N1 (12 times) is automatically counted by the N1 counter when the spontaneous operation is performed.
Step 3, calculating an error position i, which specifically comprises the following steps:
the error mode value and the value of the secondary shift decoding circuit are spliced into a 16-bit addressing address, a storage unit corresponding to the addressing address in a memory stores a distance value between corresponding 8-bit code words, namely an N2 value,
the upper 8 bits and the lower 8 bits of the N2 value are interchanged to obtain an N2 'value, the N2' value is taken as the upper 8 bits, and the N1 value is taken as the lower 4 bits to be spliced into an error position i.
Alternatively, step 3 is: the error mode value and the value of the secondary shift decoding circuit are spliced into a 16-bit addressing address, a storage unit corresponding to the addressing address in a memory stores an N2 'value of the crossing of the upper 4 bits and the lower 4 bits of the distance value between the corresponding 8-bit code words, the N2' value is used as the upper 8 bits, and the N1 value is spliced into an error position i as the lower 4 bits.
Value of secondary shift decoding circuit= (B9) H And error pattern value B (x) = (CD) H Addressing addresses spliced into a 16-bit memory (AD 0-7, AD8-15 spliced into memory addressing addresses as shown in FIG. 2), e.g. (B9 CD) H Or (CDB 9) H . The N2 value is then fetched directly by hardware addressing in the memory location of the addressing address of the memory. The memory is 64KB NVRAM or NOR FLASH or other type of random access memory. The distance value between the primitive polynomials P (X) = (x8+x4+x3+x2+1) codewords, which is the N2 value described in the existing scheme, is stored, and represents the spontaneous times that need to pass from one codeword to another codeword. See table 1.
Table 1: primitive polynomial p (X) = (X) 8 +x 4 +x 3 +x 2 +1) distance between codewords
As above, for example, the value of the secondary shift decoding circuit= (B9) H And error pattern value B (x) = (CD) H The corresponding N2 value is (CF) H 。
The upper 4 bits and the lower 4 bits of the N2 value are interchanged, as N2 = (CF) H The value after the exchange is N2' = (FC) H . And splicing the value with the value of the N1 counter to form a new value of 12bit, wherein the new value is the position i where the burst error occurs.
As in this example n1= (12) d ＝(C) H ，N2＝(CF) H After splicing, i= (FCC) is obtained H =4044. This value represents error pattern B (x) = (CD) H ＝(1100 1101) 2 Zero order term to X 4079 Is 4044 bits, to X 0 The distance of (a) is 35 bits (the start point of the error position is 36 th bit), and the position is correctly matched with the question.
Thus, the scheme of the invention completes the whole error correction decoding process by only using N1 (=12) spontaneous operations compared with the existing scheme. In general, the spontaneous times range is 0-15 and N1-15. Whereas the number of spontaneous times n of the existing scheme is in the range of [0, N1 MAX +N2 MAX ]I.e., 0.ltoreq.n.ltoreq.270 (15+255).
The memory of fig. 2 may be optimized as a sixteen-bit register that may be implemented by an address latch or similarly functioning logic device that outputs the N2 value address code to the "upper computer". The table 1 is stored in the memory by the upper computer and is used by the upper computer according to the address code of the N2 value. The hardware cost of the memory can be saved, or the error correction application of the upper computer can be met more flexibly.
The N2 value stored in "table 1" may also be converted into an N2 cross code, i.e., the N2' value may be stored directly, thus eliminating the step of cross-permuting the upper 4 bits with the lower 4 bits of the later N2 code. In the second stage of the present invention, the N2 code after cross substitution is fetched through the memory addressing access, so that the extra cross substitution operation on the hardware circuit is not needed, and the speed is faster.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (2)
1. An extremely fast error correction decoding method, comprising the steps of:
step 1, a primary shift decoding circuit and a secondary shift decoding circuit simultaneously receive an information code stream d (x) of a transmitting end;
step 2, after the primary shift decoding circuit receives the information code stream d (x), performing spontaneous operation for no more than 15 times under no input condition until the high 8 bits of the primary shift decoding circuit measured by the all-zero detection circuit are all 0, performing spontaneous operation by the secondary shift decoding circuit simultaneously while performing spontaneous operation by the primary shift decoding circuit, counting the number of times of spontaneous operation by an N1 counter to obtain an N1 value, wherein the low 8 bits of data of the primary shift decoding circuit are error mode values B (x),
step 3, splicing the error mode value and the value of the secondary shift decoding circuit into a 16-bit addressing address, storing a distance value between 8-bit code words corresponding to the addressing address in a storage unit of a memory, namely an N2 value,
the upper 8 bits and the lower 8 bits of the N2 value are interchanged to obtain an N2 'value, the N2' value is taken as the upper 8 bits, and the N1 value is taken as the lower 4 bits to be spliced into an error position i.
2. The ultra-fast error correction decoding device comprises a primary shift decoding circuit, and is characterized by further comprising an all-zero detection circuit, a secondary shift decoding circuit, an N1 counter, a memory and a controller;
the primary shift decoding circuit and the secondary shift decoding circuit simultaneously receive the information code stream of the transmitting end,
after the primary shift decoding circuit receives the information code stream, the primary shift decoding circuit performs spontaneous operation for no more than 15 times under no input condition until the 8 high bits of the primary shift decoding circuit measured by the all-zero detection circuit are all 0, the secondary shift decoding circuit performs spontaneous operation synchronously while the primary shift decoding circuit performs spontaneous operation, the N1 counter counts the number of times of spontaneous operation to obtain an N1 value,
the controller reads the lower 8 bits of data of the primary shift decoding circuit as an error pattern value,
the controller splices the error mode value and the value of the secondary shift decoding circuit into a 16-bit addressing address, a storage unit corresponding to the addressing address in the memory stores a corresponding distance value between 8-bit code words, namely an N2 value, the controller reads the N2 value,
the controller exchanges the upper 8 bits and the lower 8 bits of the N2 value to obtain an N2 'value, the N2' value is used as the upper 8 bits, and the N1 value is used as the lower 4 bits to be spliced into an error position i.
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| CN103166649B (en) * | 2011-12-19 | 2016-06-15 | 国际商业机器公司 | For method, device and the decoder of decode cycle code |
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| CN101621299A (en) * | 2008-07-04 | 2010-01-06 | 华为技术有限公司 | Burst correcting method, equipment and device |
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