CN111628078B - Synaptic transistor based on two-dimensional and three-dimensional perovskite composite structure and preparation method thereof - Google Patents
Synaptic transistor based on two-dimensional and three-dimensional perovskite composite structure and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a synapse transistor based on a two-dimensional and three-dimensional perovskite composite structure and a manufacturing method thereof, which mainly solve the problem that the simulated synapse behavior of the existing two-terminal perovskite synapse device is inaccurate, and the synapse transistor comprises a glass substrate (1), a transparent oxide gate electrode (2), a perovskite region (3), a source electrode (4), a drain electrode (5) and a packaging protective layer (6) from bottom to top. The ionic dielectric layer is made of a three-dimensional perovskite material, and the conductive channel layer is made of a two-dimensional perovskite material; modulating carrier transport in the two-dimensional perovskite material by utilizing an electric field formed by ion migration in the three-dimensional perovskite material; the grid of the device simulates a presynaptic film as an input end; the source and drain of the device simulate the postsynaptic membrane to read the postsynaptic current, the invention can simultaneously regulate two processes of carrier transport and grid control, realize the regulation and control of the source and drain current, improve the accuracy of synaptic transistor on the simulation of synaptic behavior, and can be used for simulating human neural synapse and constructing a neural network system.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a synapse transistor and a preparation method thereof, which can be used for simulating human nerve synapses and constructing a neural network system.
Background
Data information-based emerging technologies such as artificial intelligence, big data, internet of things and the like are deeply changing human lives and leading people to enter an intelligent information era. However, in the face of ever expanding data information, conventional computers have been unable to meet the demands for flexible processing and storage of large amounts of information due to the physical separation of computing units and memory, i.e., the von neumann bottleneck. How to improve the efficiency of storage and operation becomes a problem that human beings have to face. In contrast, the highly parallel nonlinear information processing capability of the human brain shows obvious advantages, and a series of complex processes such as learning, perception, recognition, memory, thinking and the like can be efficiently completed under the working conditions of low energy consumption of 20W and low frequency of 10 Hz. The powerful ability of the human brain lies in the low-power, high-speed and miniaturized neural network system composed of billions of neurons and billions of synapses, which are the "core devices" for information transmission in the system. Therefore, the development of artificial synapse devices, the construction of nervous systems, has become an urgent need and a necessity of choice in the intelligent information era. It is of great research interest to fully mimic the function of biological synapses with a single device, but traditional Si-based CMOS technology cannot accomplish this challenge. In recent years, the continuous emergence of a plurality of new materials, new devices and new mechanisms brings new opportunities for the development of artificial synapse devices.
Among many new materials, perovskite materials with both electronic and ionic conductivity have become important potential materials for artificial synapse devices due to unique material properties including tunable band gap, easy regulation of carriers, ultra-flexibility, low-temperature synthesis process at < 150 ℃, and rapid ion migration. The reported perovskite synapse device takes a two-terminal memristor as a main stream, and the conductive filament theory is a main resistance change mechanism, so that synaptic plasticity and a learning and memorizing process are simulated. However, the disadvantage of this structure is that the conduction path is single, and the signal transmission and adjustment operations cannot be performed simultaneously, so that the artificial synapses at the two ends cannot simultaneously perform signal transmission and learning. Compared with the three-terminal structure field effect transistor, the three-terminal structure field effect transistor can regulate and control a conducting channel between the source and the drain through the grid voltage, and further accurately control the source and drain current. The conductive channel and the gate can be considered as a signal transmission and conditioning module, respectively. Therefore, by virtue of the natural advantages of the device mechanism, the field effect transistor type three-terminal synapse device will dominate over the two-terminal structure device.
However, research on three-terminal perovskite-based synaptic devices is very lacked at present, and no report related to three-terminal perovskite synaptic transistors exists at home and abroad. A major problem with three-terminal perovskite synapse transistors is that ion transport behavior in halide perovskite materials limits device performance. For a typical three-dimensional organic-inorganic perovskite polycrystalline thin film, the transport of carriers in the transverse direction and the interface in a transistor device is particularly easily influenced by the crystal face state of the polycrystalline thin film and defects generally existing in crystal grains. For example, due to the ionic semiconductor properties of perovskite, when a gate voltage of a certain strength is applied to a synaptic transistor, an ion shielding effect is formed at the interface of the perovskite material and the dielectric, so that the gate voltage is disabled, and the transmission of carriers in a channel cannot be effectively regulated. Therefore, it is difficult to obtain a high-performance three-terminal synaptic transistor by directly using the three-dimensional perovskite polycrystalline thin film as a channel material.
Disclosure of Invention
The invention aims to provide a synaptic transistor based on a two-dimensional and three-dimensional perovskite composite structure and a preparation method thereof aiming at the defects of the prior art so as to effectively regulate and control the transmission of current carriers in a channel and obtain a high-performance three-terminal synaptic transistor.
The technical idea of the invention is as follows: on the basis that a three-dimensional perovskite material is reserved as a grid to be used as an input end, a two-dimensional perovskite material is additionally adopted as a conductive channel layer, so that the phenomenon of regulation failure caused by only adopting a traditional three-dimensional perovskite structure is avoided while signal transmission and signal regulation are realized.
According to the above thought, the technical scheme of the invention is realized as follows:
a synapse transistor based on two-dimensional and three-dimensional perovskite composite structure, comprising from bottom to top: glass substrate, transparent oxide gate electrode, perovskite area, source electrode, drain electrode, encapsulation protective layer, its characterized in that:
the perovskite region is divided into an ion dielectric layer, an ion barrier layer and a conductive channel layer;
the ion dielectric layer adopts a three-dimensional perovskite material, is used as a grid electrode of a synaptic transistor and is used for simulating a biological nerve presynaptic membrane;
the ion barrier layer is made of oxide materials and is used for preventing ions in the ion dielectric layer from flowing into the conductive channel layer;
the conducting channel layer is made of a two-dimensional perovskite material and is used for effectively achieving signal transfer.
Preferably, the glass substrate is made of conductive glass with light transmittance of more than 80%, so that light can enter the device from one side of the substrate.
Preferably, the transparent oxide grid is made of FTO or ITO materials.
Preferably, the three-dimensional perovskite material adopted by the ionic dielectric layer is organic-inorganic hybrid perovskite CH with the thickness of 300-500nm 3 NH 3 PbI 3 Or pure inorganic perovskite CsPbBr 3 。
Preferably, the oxide material adopted by the ion barrier layer is Al with the thickness of 10-20nm 2 O 3 Or MoO 3 。
Preferably, the two-dimensional perovskite material adopted by the conductive channel layer is 100-300nm thick (PEA) 2 PbBr 4 Or (PEA) 2 SnI 4 。
Preferably, Au with the thickness of 100-200nm is adopted for the source electrode and the drain electrode, and the distance between the source electrode and the drain electrode is 50-200 μm.
Preferably, the encapsulation protective layer is polymethyl methacrylate PMMA with the thickness of 150-300 nm.
According to the above thought, the manufacturing method of the synapse transistor based on the two-dimensional and three-dimensional perovskite composite structure is characterized by comprising the following steps:
carrying out ultrasonic cleaning on the glass substrate coated with the transparent oxide for 15-20min by sequentially using acetone, ethanol and deionized water, and drying by using nitrogen;
carrying out ultraviolet ozone treatment on the surface of the cleaned conductive glass for 20-25 min;
spin coating pure inorganic perovskite CsPbBr on the surface of conductive glass treated by ultraviolet ozone 3 Precursor solution of (A) or organic-inorganic hybrid perovskite CH 3 NH 3 PbI 3 And annealing to obtain the crystal CsPbBr with the thickness of 300-500nm 3 Or crystalline CH 3 NH 3 PbI 3 A thin film ionic dielectric layer;
in CsPbBr 3 Or CH 3 NH 3 PbI 3 Al with the thickness of 10-20nm is grown on the thin film ion dielectric layer 2 O 3 Or MoO 3 An ion blocking layer;
in Al 2 O 3 Or MoO 3 The ion barrier layer is first vapor-deposited with two-dimensional (PEA) by thermal evaporation process 2 PbBr 4 Single crystal powder, and annealing crystallization at 120 deg.C for 20min to prepare two-dimensional (PEA) with thickness of 100-300nm 2 PbBr 4 A conductive channel layer;
in two dimensions (PEA) 2 PbBr 4 Depositing an Au metal source electrode with the thickness of 100-200nm on the conductive channel layer by using a thermal evaporation process;
in two dimensions (PEA) 2 PbBr 4 Depositing an Au metal drain electrode with the thickness of 100-200nm on the conductive channel layer by using a thermal evaporation process;
in two dimensions (PEA) 2 PbBr 4 And the conductive channel layer, the Au metal source electrode layer and the Au metal drain electrode layer are coated with the polymethyl methacrylate PMMA with the thickness of 150-300nm in a spin coating manner, so that the device is packaged and protected.
Compared with the prior art, the invention has the following advantages:
first, the invention adopts a three-terminal synapse structure, regulates and controls the conducting channel between the source and the drain through the grid voltage, and accurately controls the source and the drain current, so that the conducting channel and the grid can be respectively regarded as a signal transmission and signal regulation module, and the transmission and the regulation of signals can be realized at the same time.
Secondly, the perovskite with adjustable band gap, easy regulation of current carriers, super flexibility, electron and ion conductivity is adopted as the core material of the three-terminal synapse structure, so that the rapid migration of ions can be realized.
Thirdly, the three-dimensional perovskite layer is used as the ion medium layer and the two-dimensional perovskite layer is used as the conductive channel layer, so that the ion medium layer and the conductive channel layer can be separated in space on the basis of keeping the strong ion migration capability of the three-dimensional perovskite layer and the transverse conductivity and stability of the two-dimensional perovskite layer, and the ion shielding effect is avoided.
Fourthly, the invention can simultaneously realize carrier transport and grid control regulation to simulate biological nerve synapse behavior, obtain an artificial synapse transistor, and regulate ion migration in ionic medium by different modes of voltage excitation, illumination excitation and thermal excitation, thereby regulating source and drain current.
Drawings
FIG. 1 is a diagram of a conventional biological synapse structure;
FIG. 2 is a schematic diagram of a synaptic transistor structure according to the present invention;
FIG. 3 is a schematic diagram of a process for fabricating a synaptic transistor according to the present invention.
Detailed Description
The embodiments of the invention will be further described with reference to the accompanying drawings and embodiments:
referring to fig. 1, the biological synapse refers to a portion where two neurons or a neuron and an effector cell contact each other and thereby transmit information, and is mainly composed of a presynaptic membrane, a synaptic cleft, and a postsynaptic module. The action principle of the biological synapse is as follows: the impulse travels to the presynaptic membrane, which opens an ion channel, allowing the contained transmitter to bind to a portion of the presynaptic membrane and enter the synaptic cleft; then, the transmitter in the synaptic cleft binds to the receptor in the postsynaptic membrane again, and the information transmission is completed.
The example is based on the information transmission process of biological synapse, simulates the three-terminal structure of the biological synapse, and adopts a synapse device with a two-dimensional and three-dimensional perovskite composite structure to simultaneously realize the processes of information regulation and transmission. The three-dimensional perovskite material is used as a grid electrode of a synaptic transistor, is used for simulating a biological nerve presynaptic membrane and plays a role in stimulating a pulse input end in information transmission; the source and drain electrodes of the synaptic transistor are used as a postsynaptic membrane for reading the postsynaptic current; the carrier transport in the two-dimensional perovskite material is modulated by an electric field formed by ion migration in the three-dimensional perovskite material, and the method is used for simulating the propagation of neurotransmitter.
Referring to fig. 2, the synapse transistor based on two-dimensional and three-dimensional perovskite composite structure of the present example comprises a glass substrate 1, a transparent oxide gate electrode 2, a perovskite region 3, a source electrode 4, a drain electrode 5, and an encapsulation protection layer 6. Wherein the perovskite region 3 is divided into an ion medium layer 31, an ion barrier layer 32 and a conductive channel layer 33;
the conductive glass 1 is used as the bottommost layer of the synaptic transistor, a transparent oxide gate electrode layer 2 is arranged on the conductive glass 1, a perovskite area 3 is arranged on the transparent oxide gate electrode layer 2, the perovskite area is respectively provided with an ion dielectric layer 31, an ion barrier layer 32 and a conductive channel layer 33 from bottom to top, the positions, close to the boundary, of two ends above the conductive channel layer 33 are a source metal electrode layer 4 and a drain metal electrode layer 5, and a packaging protective layer 6 is arranged above the conductive channel layer 33 and the source drain metal electrode layer.
The glass substrate 1 adopts conductive glass with the light transmittance of more than 80 percent, so that light can enter the device from one side of the substrate; the transparent oxide grid 2 is made of FTO or ITO material; the three-dimensional perovskite material adopted by the ion dielectric layer 31 is organic-inorganic hybrid perovskite CH with the thickness of 300-500nm 3 NH 3 PbI 3 Or pure inorganic perovskite CsPbBr 3 (ii) a The ion barrier layer 32 is made of an oxide material, which is Al with a thickness of 10-20nm 2 O 3 Or MoO 3 (ii) a The conductive channel layer 33 is a two-dimensional perovskite material having a thickness of 100-300nm (PEA) 2 PbBr 4 (ii) a The source electrode 4 and the drain electrode 5 both adopt Au with the thickness of 100-200nm, and the Au is arranged between the source electrode 4 and the drain electrode 5The pitch of (a) is 50-200 μm; the encapsulation protection layer 6 adopts polymethyl methacrylate PMMA with the thickness of 150-300 nm.
Referring to fig. 3, the present example is a method for fabricating a synapse transistor based on two-dimensional and three-dimensional perovskite composite structures, giving the following four examples:
example 1: manufacturing FTO oxidized gate electrode and Al 2 O 3 And the ion barrier layer is a pure inorganic three-dimensional perovskite synaptic transistor.
Step 1: the conductive substrate is processed.
As shown in fig. 3a, the conductive substrate is composed of a substrate including a glass substrate and an FTO transparent oxide gate electrode, and is ultrasonically cleaned for 15min by sequentially using acetone, ethanol and deionized water, and is blow-dried by high-purity nitrogen; and carrying out UV-ozone treatment on the surface of the cleaned conductive substrate for 20min to obtain a gate electrode of the synaptic transistor.
Step 2: growing a perovskite area.
2.1) As shown in FIG. 3b, spin-coating PbBr on the surface of the conductive substrate after the UV ozone treatment at a concentration of 1mol/L and a rotation speed of 2000r/min 2 DMF solution of (b) for 30s and thermal annealing at a temperature of 90 ℃ for a time period of 1h to obtain PbBr 2 A layer; then PbBr 2 CsBr is coated on the layer in a spin way under the conditions of 0.07mol/L concentration and 2000r/min rotation speed 2 Is carried out for 30s at the temperature of 250 ℃ for 5min, and is repeated for 6 times to obtain three-dimensional CsPbBr with the thickness of 300nm 3 An ion medium layer;
2.2) growing Al on the ion dielectric layer by using an atomic layer deposition process as shown in FIG. 3c 2 O 3 Ion barrier layer, i.e. Al grown to a thickness of 10nm at a temperature of 300 ℃ and a cycle number of 250 2 O 3 An ion blocking layer;
2.3) As shown in FIG. 3d, two-dimensional (PEA) is first evaporated on the ion-blocking layer by thermal evaporation 2 PbBr 4 Single crystal powder, i.e. two-dimensional (PEA) grown at an evaporation temperature of 200 ℃ and an evaporation rate of 0.05nm/s 2 PbBr 4 (ii) a Two dimension Pair (PEA) 2 PbBr 4 Performing annealing crystallization at 120 deg.C for 20min to obtain two-dimensional (PEA) with thickness of 100nm 2 PbBr 4 A conductive channel layer.
And step 3: and growing a source drain electrode.
As shown in fig. 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation, and the source and drain metal electrodes with a thickness of 100nm are grown at an evaporation rate of 0.1nm/s, keeping the source-drain spacing at 100 μm.
And 4, step 4: and (5) packaging the synaptic transistor.
As shown in fig. 3f, a chlorobenzene solution of PMMA is spin-coated on the conductive channel layer and the source drain metal layer at a concentration of 10mg/mL and a rotation speed of 2000r/min for 60s to generate a 150nm thick encapsulation protection layer, so as to encapsulate and protect the device. And finishing the manufacture of the synapse transistor based on the two-dimensional and three-dimensional perovskite composite structure.
Example 2: manufacturing ITO (indium tin oxide) gate electrode and MoO (molybdenum oxide) 3 An organic-inorganic hybrid three-dimensional perovskite synapse transistor of an ion blocking layer.
The method comprises the following steps: the conductive substrate is processed.
As shown in fig. 3a, the conductive substrate is composed of a substrate including a glass substrate and an ITO transparent oxide gate electrode, and is ultrasonically cleaned for 15min by sequentially using acetone, ethanol and deionized water, and is dried by high-purity nitrogen; and carrying out UV-ozone treatment on the surface of the cleaned conductive substrate for 20min to obtain a gate electrode of the synaptic transistor.
Step two: growing a perovskite area.
2a) As shown in FIG. 3b, PbI is spin-coated on the surface of the conductive substrate after the UV ozone treatment under the conditions of concentration of 1.4mol/L and rotation speed of 3000r/min 2 45s in DMF to obtain PbI 2 A layer; then PbI 2 The layer is spin-coated with CH at a concentration of 100mg/mL and a rotation speed of 3000r/min 3 NH 3 I of isopropanol solution for 45s, and carrying out thermal annealing for 10min under the nitrogen atmosphere at the temperature of 100 ℃ to obtain three-dimensional CH with the thickness of 400nm 3 NH 3 PbI 3 An ionic medium layer;
2b) as shown in fig. 3c, MoO is grown on the ion medium layer by thermal evaporation process 3 An ion barrier layer for growing MoO with a thickness of 15nm at an evaporation temperature of 650 ℃ and an evaporation rate of 0.05nm/s 3 An ion blocking layer;
2c) as shown in FIG. 3d, a thermal evaporation process is used to evaporate two-dimensional (PEA) on the ion-blocking layer 2 PbBr 4 Single crystal powder, i.e. two-dimensional (PEA) grown at an evaporation temperature of 200 ℃ and an evaporation rate of 0.05nm/s 2 PbBr 4 (ii) a Two dimension Pair (PEA) 2 PbBr 4 Performing annealing crystallization at 120 deg.C for 20min to obtain two-dimensional (PEA) with thickness of 200nm 2 PbBr 4 A conductive channel layer.
Step three: and growing source and drain electrodes.
As shown in fig. 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation, and the source and drain metal electrodes with the thickness of 150nm are grown under the condition that the evaporation rate is 0.1nm/s, and the source-drain spacing is kept at 100 μm.
Step four: and (5) packaging the synaptic transistor.
As shown in fig. 3f, a chlorobenzene solution of PMMA is spin-coated on the conductive channel layer and the source drain metal layer for 60s at a concentration of 10mg/mL and a rotation speed of 2000r/min to generate a 200nm thick encapsulation protection layer, so as to encapsulate and protect the device. And finishing the manufacture of the synapse transistor based on the two-dimensional and three-dimensional perovskite composite structure.
Example 3: manufacturing FTO oxidized gate electrode and Al 2 O 3 An organic-inorganic hybrid three-dimensional perovskite synapse transistor of an ion blocking layer.
Step A: the conductive substrate is processed.
The specific implementation of this step is the same as step 1 of example 1.
And B, step B: growing a perovskite area.
B1) As shown in FIG. 3b, PbI is spin-coated on the surface of the conductive substrate after the UV ozone treatment under the conditions of concentration of 1.4mol/L and rotation speed of 3000r/min 2 45s of DMF to obtain PbI 2 A layer;then PbI 2 The layer is spin-coated with CH under the conditions of the concentration of 100mg/mL and the rotating speed of 3000r/min 3 NH 3 I of isopropanol solution for 45s, and carrying out thermal annealing for 10min under the nitrogen atmosphere at the temperature of 100 ℃ to obtain three-dimensional CH with the thickness of 500nm 3 NH 3 PbI 3 An ion medium layer;
B2) growing Al on the ion dielectric layer by using an atomic layer deposition process, as shown in FIG. 3c 2 O 3 Ion barrier layer, i.e. Al grown to a thickness of 20nm at a temperature of 300 ℃ and a cycle number of 250 2 O 3 An ion blocking layer;
B3) as shown in FIG. 3d, a thermal evaporation process is used to evaporate two-dimensional (PEA) on the ion-blocking layer 2 PbBr 4 Single crystal powder, i.e. two-dimensional (PEA) grown at an evaporation temperature of 200 ℃ and an evaporation rate of 0.05nm/s 2 PbBr 4 (ii) a Two dimension (PEA) 2 PbBr 4 Performing annealing crystallization at 120 deg.C for 20min to obtain two-dimensional (PEA) with thickness of 300nm 2 PbBr 4 A conductive channel layer.
And step 3: and growing a source drain electrode.
As shown in fig. 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation, and source and drain metal electrodes with a thickness of 200nm are grown at an evaporation rate of 0.1nm/s, keeping the source-drain spacing at 100 μm.
And 4, step 4: and (5) packaging the synapse transistor.
As shown in fig. 3f, a chlorobenzene solution of PMMA is spin-coated on the conductive channel layer and the source drain metal layer for 60s at a concentration of 10mg/mL and a rotation speed of 2000r/min to generate a packaging protective layer with a thickness of 300nm, so as to package and protect the device. And finishing the manufacture of the synapse transistor based on the two-dimensional and three-dimensional perovskite composite structure.
Example 4: manufacturing ITO (indium tin oxide) gate electrode and MoO (molybdenum oxide) 3 And the ion barrier layer is a pure inorganic three-dimensional perovskite synaptic transistor.
The first step is as follows: the conductive substrate is processed.
The specific implementation of this step is the same as step one of example 2
The second step is that: growing a perovskite area.
First, as shown in FIG. 3b, the surface of the conductive substrate after the UV ozone treatment is spin-coated with PbBr at a concentration of 1mol/L and a rotation speed of 2000r/min 2 DMF solution of (b) for 30s and thermal annealing at a temperature of 90 ℃ for a time period of 1h to obtain PbBr 2 A layer; then PbBr 2 CsBr is spin-coated on the layer under the conditions of concentration of 0.07mol/L and rotating speed of 2000r/min 2 Is subjected to thermal annealing at 250 ℃ for 5min for 6 times to obtain three-dimensional CsPbBr with thickness of 450nm for 30s 3 An ion medium layer;
next, as shown in FIG. 3c, MoO is grown on the ion medium layer by thermal evaporation process 3 An ion barrier layer for growing MoO with a thickness of 15nm at an evaporation temperature of 650 ℃ and an evaporation rate of 0.05nm/s 3 An ion blocking layer;
then, as shown in FIG. 3d, a two-dimensional (PEA) vapor deposition process is performed on the ion-blocking layer using a thermal evaporation process 2 PbBr 4 Single crystal powder, i.e. two-dimensional (PEA) grown at an evaporation temperature of 200 ℃ and an evaporation rate of 0.05nm/s 2 PbBr 4 (ii) a Two dimension (PEA) 2 PbBr 4 Performing annealing crystallization at 120 deg.C for 20min to obtain two-dimensional (PEA) with thickness of 150nm 2 PbBr 4 A conductive channel layer.
The third step: and growing a source drain electrode.
As shown in fig. 3e, source and drain metal Au pattern electrodes are deposited on the conductive channel layer by thermal evaporation process, and the source and drain metal electrodes with a thickness of 180nm are grown under the condition that the evaporation rate is 0.1nm/s, and the source-drain spacing is kept at 100 μm.
The fourth step: and (5) packaging the synapse transistor.
As shown in fig. 3f, a chlorobenzene solution of PMMA is spin-coated on the conductive channel layer and the source drain metal layer for 60s at a concentration of 10mg/mL and a rotation speed of 2000r/min to generate a packaging protective layer with a thickness of 250nm, so as to package and protect the device. And finishing the manufacture of the synapse transistor based on the two-dimensional and three-dimensional perovskite composite structure.
The foregoing description is only illustrative of four specific embodiments of the invention, and it will be apparent to those skilled in the art that various modifications and variations can be made in the form and detail of the method according to the invention without departing from the spirit and scope of the invention, but such modifications and variations are within the scope of the claims appended hereto.
Claims (12)
1. A synapse transistor based on two-dimensional and three-dimensional perovskite composite structure, comprising from bottom to top: glass substrate (1), transparent oxide gate electrode (2), perovskite district (3), source electrode (4), drain electrode (5), encapsulation protective layer (6), its characterized in that:
the perovskite area (3) is divided into an ion medium layer (31), an ion barrier layer (32) and a conductive channel layer (33) from bottom to top;
the ionic dielectric layer (31) is made of a three-dimensional perovskite material, is used as a grid electrode of a synaptic transistor and is used for simulating a biological nerve presynaptic membrane;
the ion barrier layer (32) is made of oxide materials and is used for preventing ions in the ion medium layer (31) from flowing into the conductive channel layer (33);
the conducting channel layer (33) is made of two-dimensional perovskite material and is used for effectively realizing signal transfer.
2. A transistor according to claim 1, characterized in that the glass substrate (1) is made of a conductive glass with a light transmission of more than 80%, so that light can enter the device from the substrate side.
3. Transistor according to claim 1, characterized in that the transparent oxide gate electrode (2) is made of FTO or ITO material.
4. The transistor of claim 1, wherein:
the three-dimensional perovskite material adopted by the ion dielectric layer (31) is 300-500nm thickOrganic-inorganic hybrid perovskite CH 3 NH 3 PbI 3 Or pure inorganic perovskite CsPbBr 3 ；
The oxide material adopted by the ion barrier layer (32) is Al with the thickness of 10-20nm 2 O 3 Or MoO 3 ；
The two-dimensional perovskite material adopted by the conductive channel layer (33) is 100-300nm thick (PEA) 2 PbBr 4 。
5. The transistor of claim 1, wherein the source electrode (4) and the drain electrode (5) are both made of Au with a thickness of 100-200nm, and the distance between the source electrode (4) and the drain electrode (5) is 50-200 μm.
6. The transistor according to claim 1, wherein the protective encapsulation layer (6) is PMMA with a thickness of 150-300 nm.
7. A manufacturing method of a synapse transistor based on two-dimensional and three-dimensional perovskite composite structures is characterized by comprising the following steps:
1) carrying out ultrasonic cleaning on the glass substrate coated with the transparent oxide for 15-20min by sequentially using acetone, ethanol and deionized water, and drying by using nitrogen;
2) carrying out ultraviolet ozone treatment on the surface of the cleaned conductive glass for 20-25min to form a gate electrode of a synaptic transistor;
3) spin coating pure inorganic perovskite CsPbBr on the surface of conductive glass treated by ultraviolet ozone 3 Precursor solution of (A) or organic-inorganic hybrid perovskite CH 3 NH 3 PbI 3 And annealing to obtain the crystal CsPbBr with the thickness of 300-500nm 3 Or crystalline CH 3 NH 3 PbI 3 A thin film ionic dielectric layer;
4) in CsPbBr 3 Or CH 3 NH 3 PbI 3 Growing Al with the thickness of 10-20nm on the thin film ion dielectric layer 2 O 3 Or MoO 3 An ion blocking layer;
5) in the presence of Al 2 O 3 Or MoO 3 The ion barrier layer is first vapor-deposited with two-dimensional (PEA) by thermal evaporation process 2 PbBr 4 Single crystal powder, and annealing crystallization at 120 deg.C for 20min to prepare two-dimensional (PEA) with thickness of 100-300nm 2 PbBr 4 A conductive channel layer;
6) two dimensions (PEA) 2 PbBr 4 And depositing an Au metal source electrode with the thickness of 100-200nm on the conductive channel layer by using a thermal evaporation process:
7) in two dimensions (PEA) 2 PbBr 4 And depositing an Au metal drain electrode with the thickness of 100-200nm on the conductive channel layer by using a thermal evaporation process:
8) in two dimensions (PEA) 2 PbBr 4 And the conductive channel layer, the Au metal source electrode layer and the Au metal drain electrode layer are coated with the polymethyl methacrylate PMMA with the thickness of 150-300nm in a spin coating manner, so that the device is packaged and protected.
8. The method of claim 7, wherein 3) spin-on pure inorganic perovskite CsPbBr 3 And annealing to achieve the following:
firstly, spin-coating PbBr on FTO conductive glass surface treated by ultraviolet ozone under the conditions of concentration of 1mol/L, rotating speed of 2000r/min and time of 30s 2 And thermal annealing at 90 ℃ for 1h to obtain PbBr 2 A layer;
then, PbBr is added 2 Spin-coating CsBr on the layer at the concentration of 0.07mol/L, the rotation speed of 2000r/min and the time of 30s 2 The thermal annealing is carried out for 5min at the temperature of 250 ℃, and the thermal annealing is repeated for 6 times to obtain the three-dimensional CsPbBr with the thickness of 300-500nm 3 And an ion medium layer.
9. The method as claimed in claim 7, wherein the inorganic-inorganic hybrid perovskite CH in 3) is spin-coated 3 NH 3 PbI 3 And annealing to realize the following steps:
firstly, spin-coating PbI on the surface of ITO conductive glass treated by ultraviolet ozone under the conditions of concentration of 1.4mol/L, rotating speed of 3000r/min and time of 45s 2 DMF solution of (2) to obtain PbI 2 A layer;
second step in PbI 2 Spin-coating CH on the layer at a concentration of 100mg/mL, a rotation speed of 3000r/min and a time of 45s 3 NH 3 I in isopropanol; and performing thermal annealing at 100 deg.C for 10min to obtain three-dimensional CH with thickness of 300-500nm 3 NH 3 PbI 3 And an ion medium layer.
10. The method of claim 7, wherein Al is grown in 4) 2 O 3 Or MoO 3 The process conditions of the ion barrier layer are as follows:
growing Al 2 O 3 Adopting an ozone method, wherein the temperature is 300 ℃, and the cycle number is 250;
growth of MoO 3 The method adopts a thermal evaporation method, the temperature of which is 650 ℃, and the evaporation rate is 0.05 nm/s.
11. The method of claim 7, wherein the thermal evaporation processes adopted in 5), 6) and 7) are respectively as follows:
said 5) Medium growth two-dimensional (PEA) 2 PbBr 4 The thermal evaporation process of the conductive channel layer comprises the following steps: the evaporation temperature is 200 ℃, and the evaporation rate is 0.05 nm/s;
the thermal evaporation process for growing the Au material source electrode in the step 6) comprises the following steps: the evaporation rate is 0.1 nm/s;
the thermal evaporation process for growing the Au material drain electrode in the step 7) comprises the following steps: the evaporation rate was 0.1 nm/s.
12. The method of claim 7, wherein the process conditions of 8) spin coating the encapsulation protection layer are: the concentration of polymethyl methacrylate PMMA is 10mg/mL, the rotating speed is 2000r/min, and the time is 60 s.
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